KR20050085898A - Semiconductor test device - Google Patents

Abstract

At an edge timing of a system clock output from a DUT, a recovery clock synchronized with the internal clock having a higher speed than the system clock is acquired. A semiconductor test device includes: flip-flops (21a to 21n) for inputting the system clock of DUT1; a delay circuit (22) for successively inputting a strobe delayed by a predetermined timing interval to an FF (21) and outputting the time-series level data; a time interpolator (20) having an encoder (28) for inputting the time-series level data output from the FF (21) and encoding it to position data indicating the edge timing; and a plurality of registers (41a to 41n) for successively storing position data from the encoder (28) and outputting it at a predetermined timing. The semiconductor test device further includes: a digital filter (40) for outputting the position data from the register (41) as a recovery clock and a data side selector (30) for selecting output data from the DUT1 by using the recovery clock as a selection signal.

Description

Semiconductor Test Equipment {SEMICONDUCTOR TEST DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor test apparatus which determines whether or not the device under test is compared by comparing output data output from the device under test with predetermined expected value data, and more particularly, an internal clock that is faster than the system clock of the device The present invention relates to a semiconductor test apparatus suitable for a test of a high speed device, for example, represented by an ODR (Octal Data Rate) type device in which data is output at a data rate.

Generally, a semiconductor test apparatus (LSI tester) for testing a semiconductor device inputs a predetermined test pattern signal to a device under test (DUT) to be a test target, and outputs the output from the device under test. By comparing the data with a predetermined expected value pattern signal and determining the coincidence or inconsistency, the quality of the device under test is detected and determined.

With reference to FIG. 8, this kind of semiconductor test apparatus is demonstrated. 8 is a block diagram showing a schematic configuration of a conventional general semiconductor test apparatus (LSI tester).

As shown in FIG. 8, the conventional LSI tester 110 includes a level comparator 111 for level comparing the output data of the device under test (DUT) 101 with a comparison voltage and an output of the device under test 101. And a pattern comparator 112 for comparing the data with a predetermined expected value, a flip-flop 121 for inputting the output data of the device under test 101 into the pattern comparator 112 at a predetermined timing.

In the conventional semiconductor test apparatus having such a configuration, first, a predetermined test pattern signal is input to the device under test 101 from a pattern generator (not shown), and the predetermined signal is output as output data from the device under test 101. . The output data output from the device under test 101 is input to the level comparator 111. The output data input to the level comparator 111 is level compared with the comparison voltage and output to the flip-flop 121.

In the flip-flop 121, the signal from the level comparator 111 is held as input data, and output data is output at a predetermined timing using a strobe from a timing generator (not shown) as a clock signal. The output data output from the flip-flop 121 is input to the pattern comparator 112, compared with predetermined expected value data output from the pattern generator in the tester, and a comparison result is output. As a result of this comparison, the coincidence and inconsistency between the output data and the expected value is detected, and determination of pass / fail of the device under test 101 is performed.

As described above, in the conventional semiconductor test apparatus (LSI tester), output data output from the device under test is acquired at the timing of the strobe output at a predetermined timing inside the tester, and the strobe is provided independently of the device under test. It was a timing signal output from a timing generator. By the way, in the conventional semiconductor test apparatus which acquires the output data of the device under test by the independent timing signal output from the tester as described above, an internal clock which is faster than the system clock is generated inside the device, and output at the timing of the internal clock. A problem arises in that it cannot cope with a test of a high-speed device in which data is output.

In recent years, the progress of speeding up LSI has been remarkable, and new semiconductor devices represented by, for example, ODR (Octal Data Rate) type devices have been provided in order to speed up data transfer. In this kind of device, as shown in FIG. 9, an internal clock of frequency n times the system clock of the device 101 is generated by a PLL circuit or the like, and data output is performed at a timing of an internal clock faster than the system clock. It is. For example, an ODR-type device generates an internal clock four times the system clock, and outputs data at a double data rate (DDR) in synchronization with the rising and falling edges of the internal clock. Data output of eight times the data rate is realized. DDR transmits data at the timing of both the rising edge and the falling edge of each clock signal. Compared to the SDR (Single Data Rate) method, data transfer is performed only at the rising edge (or falling edge) of the clock. Double data transfers are possible in clock cycles.

When a test is performed on such a device, data must be acquired at both edge timings of the rise and fall of the system clock of the device and at the data rate of the internal clock output at a frequency several times the system clock.

However, as described above, in the conventional semiconductor test apparatus, output data from the device under test is acquired by a timing signal output from a timing generator independent of the device under test. For this reason, the output data could not be acquired at the edge timing of the clock output from the device under test, nor could it be obtained at the data rate of the internal clock of frequency several times the system clock.

That is, in the structure of the conventional semiconductor test apparatus, it was not possible to test the device in which data is output at the edge timing of the system clock and at the data rate of the internal clock which is faster than the system clock.

The present invention has been proposed to solve the problem of the conventional technology, and acquires the system clock output from the device under test, and at the edge timing of the rising or falling of the system clock, the internal clock is faster than the system clock. By acquiring a recovery clock of frequency, a high speed represented by a device under test, for example, an ODR (Octal Data Rate) type device, in which data is output at the edge timing of the system clock and at a data rate of an internal clock that is faster than the system clock. An object of the present invention is to provide a semiconductor test apparatus that enables the device to be tested.

<Start of invention>

In order to achieve the above object, the semiconductor test apparatus of the present invention inputs a clock output from a device under test, as described in claim 1, and the clock is formed by a plurality of strobes having a constant timing interval. Acquire and output as time data as level data, and selectively input level data indicating edge timings of the rising and / or falling edges of the level data, and output position data indicating the edge timing of the selected level data. A second time interpolator for inputting a first time interpolator and output data output from the device under test, obtaining the output data by a plurality of strobes having a constant timing interval, and outputting the output data as level data in time series; Input position data output from the first time interpolator, A digital filter for holding and outputting a recovery clock indicating a predetermined edge timing from one or more position data, and level data of time series output from the second time interpolator, and outputting the corresponding level data from the digital filter. And a data selection circuit for selecting from the edge timing of the recovery clock to be output as the data under measurement of the device under test.

According to the semiconductor test apparatus of the present invention having such a configuration, first, by providing the first and second time interpolators, the clock and output data output from the device under test can be obtained as time series level data. The level data of this time series represents the edge timing which is the signal change point of the clock (and output data) of the device under test. Therefore, by inputting the system clock signal output from the device under test into the time interpolator and acquiring the level data and the position data indicating the edge timing thereof, the position data is used as the timing signal for acquiring the output data of the device under test. It is available.

In particular, the present invention includes an edge selector and selectively outputs time series level data acquired by the time interpolator as level data indicating timings of rising edge of clock, falling edge, or rising and falling edges. can do. As a result, the output data can be acquired at the edge timings of both the rising edge and the falling edge of the clock under test, and the DDR type device can be supported.

In addition, by enabling the selective output of the level data of the rising edge and the falling edge of the clock in this way, for example, when the falling edge (or rising edge) has poor precision in a DDR device, the rising edge (or falling edge) The output data can also be acquired using only).

Further, in the test apparatus of the present invention, the recovery clock is further provided with a digital filter to hold and store the position data of the clock acquired by the time interpolator, for example, to be corrected at a desired timing such as n times the frequency of the system clock. Can be output as

Although the first time interpolator can acquire the level data and the position data indicating the edge timing of the clock, for example, when the device under test outputs the data according to an internal clock of n times the system clock, 1 / Even when the edge timing of the system clock of frequency n is obtained, only one rising edge or falling edge can be detected once every n cycles, and the signal change point (rising edge or falling edge) cannot be detected in another cycle. As a result, the timing edge of the internal clock of frequency n times can be acquired only once in n cycles.

In addition, the clock signal output from the device under test has jitter, and the edge timing indicated by the obtained level data and position data may not be an appropriate timing as a timing signal for acquiring the test data.

Therefore, by inputting and storing the position data of the system clock of the device under test, which is obtained by the time interpolator, to the digital filter, for example, a clock signal indicating the edge timing of a period corresponding to an internal clock of frequency n times the system clock, for example. As a result, the corrected recovery clock can be output at an accurate and proper timing. And a data selection circuit which selects output data of the device under test as the recovery clock as a selection signal, whereby time-level level data of the output data acquired by the time interpolator is compared with predetermined expected value data. Can select and print.

Thereby, even when the output data output from the device under test is output based on an internal clock that is faster than the system clock output from the device, and even when the system clock fluctuates due to jitter, an appropriate edge at a desired frequency can be obtained. A recovery clock indicating timing can be output.

As described above, according to the semiconductor test apparatus according to the present invention, a desired recovery clock can be obtained regardless of the frequency of the system clock of the device under test, the influence of jitter, or the like, and the recovery clock is used to output the output data of the device under test. It becomes possible to acquire, and even a high speed semiconductor device, such as an ODR type device, can test easily and reliably and accurately.

Specifically, as described in claim 2, the first time interpolator includes a plurality of parallel circuits connected in parallel for inputting a clock output from the device under test, and a plurality of strobes delayed at constant timing intervals. Level data indicating a rising edge and level data indicating a falling edge of a delay circuit for sequentially inputting to the sequential circuit of the sequential circuit and outputting the time series level data from the sequential circuit; Or an edge selector for selectively outputting level data indicating rising and falling edges, and an encoder for inputting the level data selected by the edge selector and encoding and outputting the position data indicating the edge timing. Position data output from one time interpolator A recovery clock having one or more registers connected in series for serially storing and outputting the stored position data at a predetermined timing, the recovery clock indicating a predetermined edge timing from one or more position data output from this register; The second time interpolator sequentially inputs a plurality of serially connected sequence circuits for inputting output data output from the device under test and a strobe delayed at a predetermined timing interval into the plurality of sequence circuits, A delay circuit for outputting time series level data from the circuit, wherein the data selection circuit selects one of the level data of the time series input from the second time interpolator, using the recovery clock output from the digital filter as the selection signal. Select the test diva Switch may be of a configuration that includes a selector for outputting as the measured data.

In addition, as described in claim 3, the edge selector includes a first AND circuit for inputting an inverted output of one order circuit and a non-inverted output of an interrupt sequence circuit, and a non-inverted output of one sequence circuit. Any one of a second AND circuit for inputting an inverted output of an ordered circuit of blocking and blocking, an OR circuit for inputting the outputs of the first and second AND circuits, and an output of the first AND circuit, the second AND circuit, and the OR circuit. It consists of a structure which consists of one or more selector circuits which consist of a selector which selects (n).

According to the semiconductor test apparatus of the present invention having such a configuration, the first and second time interpolators including the edge selector, the digital filter, and the data selection circuit can be divided into a sequential circuit, a delay circuit, an encoder, a register, a selector, an AND circuit, and an OR. It can be easily configured using existing means, such as a circuit. Thereby, the LSI tester does not become complicated, large, expensive, etc., and can implement | achieve the semiconductor test apparatus which concerns on this invention with a simple structure.

In addition, according to the semiconductor test apparatus of the present invention comprising a sequential circuit, a delay circuit, and a register, the time series in the time interpolator and the digital filter is changed by changing the number of sequential circuits, the number of registers, and the delay amount of the delay circuit. The bit width (number of sequential circuits and registers) and resolution (delay amount of delay circuit) of the level data and position data can be set to arbitrary values. As a result, various settings can be made according to the data rate, jitter width, and the like, thereby realizing a versatile and convenient semiconductor test apparatus that can cope with any LSI.

In addition, the sequential circuits and registers provided in the time interpolator and the digital filter can be simply configured using existing circuits such as flip-flops and latches. However, as long as output data from the device under test can be acquired at regular timing intervals and output as time series level data, position data indicating edge timing can be retained, stored, and output at a predetermined timing. In addition to flops and latches, any circuit configuration may be employed.

Then, the semiconductor test apparatus of the present invention, as described in claim 4, the digital filter detects the presence or absence of the edge of the position data input from the first time interpolator, and when the edge is detected, It is a structure provided with the edge detection circuit which outputs the stored position data.

According to the semiconductor test apparatus of the present invention having such a configuration, by providing the edge detection circuit, only the position data of the edge position indicating the signal change point is detected among the position data of the clock acquired by the first time interpolator. It can be stored and output as a reference position data as a register.

For example, in the case of the system clock of an ODR-type device, it becomes 1/8 of the data rate of output data. For this reason, only the position data of the rising or falling edge of the system clock acquired by the first time interpolator can detect the signal change point (rising edge and falling edge) only once for eight rising and falling edges of the output data. The output data output at the data rate of 8 times cannot be obtained.

Therefore, the present invention includes an edge detection circuit for detecting the presence or absence of an edge of the position data to be acquired, and stores the edge position detected position data in a register and outputs a recovery clock at the frequency timing of the internal clock based on the position data. I'm trying to. Thereby, the edge timing of the system clock of the device under test can be output at a predetermined frequency, and a recovery clock corresponding to the data rate of the output data of the device under test can be output.

In addition, by outputting the recovery clock based on the position data of the system clock at which the edge is detected in this way, even when the average value of the acquired position data is obtained and output as the recovery clock, the correct timing reflects the edge timing of the actual system clock. A recovery clock indicating the timing can be output, and more accurate and reliable semiconductor test can be performed.

Further, as described in claim 5, the register of the digital filter is configured to output the stored position data at a predetermined timing regardless of the presence or absence of the edge of the position data detected by the edge detection circuit.

According to the semiconductor test apparatus of the present invention having such a configuration, the previous cycle already stored in the register when the edge representing the signal change point of the position data of the clock acquired by the first time interpolator is not detected. The position data of the clock can be output at a predetermined timing, and the recovery clock can be output based on the position data of the previous cycle.

Of the position data of the clock output from the first time interpolator, as shown in claim 4 described above, only the position data where the edge is detected may be stored in a register to be used as a reference for the recovery clock. When the edge of the position data is not detected due to the like, for example, the position data that can be acquired decreases or the period in which the position data can be obtained may not be constant. For this reason, for example, when obtaining the average value of a plurality of position data and outputting the recovery clock, it is necessary to include a large number of registers in order to output the correct recovery clock. Therefore, in the present invention, when the edge of the acquired position data is not detected, the position data where the edge stored in the previous cycle is detected is outputted from the register so that the recovery clock can be output based on the position data. have.

Thereby, while acquiring the edge timing of the position data actually acquired, the acquisition cycle of a position data can be made constant, the number of installation of a register can be optimized, and a tester structure does not become complicated, large, and expensive, With a simple configuration, a highly reliable semiconductor test apparatus can be realized.

In addition, when the edge of the position data of the clock of the first time interpolator is not detected, it is possible to configure whether or not to output the position data of all cycles stored in the register as a reference of the recovery clock. Thereby, for example, by using only the actual edge timing of the clock of the device under test, when performing a more rigorous functional test or jitter analysis, only the position data where the edge is detected is selected, and the device under test is selected from the average value of a certain period. In the case of performing a logic test for checking the output data or the clock data, the position data can be selectively employed according to the test contents or the like, as well as the position data of all cycles already stored.

In addition, as described in claim 6, in the case where two or more registers are provided, the digital filter inputs position data respectively output from two or more registers, and calculates an average value of edge timings indicated by each position data. And an average value calculating circuit for outputting the average value as the recovery clock.

According to the semiconductor test apparatus of the present invention having such a configuration, the digital filter includes a plurality of registers and an average value calculating circuit for inputting position data of each register to store the position data output from the time interpolator in the plurality of registers. The average value of the plurality of position data can be calculated and output as a recovery clock. As a result, the average value of the edge timings represented by the plurality of position data can be used as the recovery clock according to the present invention, and the accurate and proper timing signal reflecting the edge timing of the actual system clock of each device under test can be obtained. Even when the edge of the clock is not detected or when the jitter timing changes due to jitter, a recovery clock that accurately represents the edge timing of the clock of the device under test can be obtained.

In addition, as described in claim 7, the digital filter selects one of the position data output from one of the two or more registers and the average value output from the average value calculating circuit, and outputs it as a recovery clock. It is a structure provided with a changeover switch.

According to the semiconductor test apparatus of the present invention having such a configuration, by providing an average value changeover switch, the recovery clock output from the digital filter selectively switches the average value of the position data output from a specific register and the position data of the plurality of registers. Can be output.

As a result, for example, when performing a functional test in consideration of the timing variation caused by jitter of the system clock of the device under test, the average value of a plurality of registers is output as a recovery clock, and the device under test is irrespective of the timing variation caused by jitter. When performing a logic test that checks the system clock or the output data itself, the recovery clock can be selectively used according to the test contents, such as using position data output from one register among a plurality of registers as a recovery clock. This makes it possible to realize a semiconductor test apparatus which is more versatile and expandable.

Further, as described in claim 8, the digital filter adds a predetermined correction value to the position data output from the register, corrects the edge timing indicated by the position data, and outputs it as a recovery clock. It is a structure provided with.

According to the semiconductor test apparatus of the present invention having such a configuration, by providing a timing correction circuit, a setup time, a hold time, and the like are set for an average value of position data output from one register or position data output from two or more registers. By adding the set value (correction value), it is possible to output the corrected recovery clock at an appropriate edge timing.

In general, in order to acquire the output data stably by the clock signal, it is necessary to consider the setup time (or hold time) of the output data with respect to the clock. Therefore, in the present invention, a timing correction circuit that adds a setup time or a hold time set value to position data output from a register of a digital filter provides a proper edge timing by adding the setup time or hold time of the output data. It is possible to output the corrected recovery clock. Thereby, the level data of the time series output from the time interpolator can be acquired by the recovery clock corrected at a more appropriate timing, and a more accurate and reliable semiconductor test apparatus can be provided.

In addition, as described in claim 9, in the semiconductor test apparatus of the present invention, a plurality of recovery clocks output from a digital filter are input, the phase difference of the edge timing indicated by each recovery clock is detected, and the device under test is tested. A jitter detection circuit for acquiring jitter of a clock of the clock is provided.

According to the semiconductor test apparatus of the present invention having such a configuration, a jitter detection circuit for inputting a plurality of recovery clocks is provided to subtract position data indicating the edge timing of each recovery clock, thereby detecting a phase difference between the recovery clocks. Can be. Further, the distribution of the phase difference can be obtained and output as distribution data indicating variation or expansion of the phase difference. The phase difference of the recovery clock represents the jitter of the system clock of the device under test. By acquiring the phase difference of the recovery clock and its distribution data, the clock and output data jitter analysis of the device under test can be performed.

As a result, in the present invention, there is no problem as in the case of using a conventional jitter measuring device, such as an error caused by an operation of an oscilloscope or the like, or a difficulty in measuring work. Jitter analysis of the output data and the clock of the device under test can be performed.

Moreover, the semiconductor test apparatus of this invention connects a 1st and 2nd time interpolator, respectively, as described in Claim 10, and predetermined | prescribed the data output from the said 1st and 2nd time interpolator is predetermined. It is a structure provided with the bus which distributes to a data selection circuit.

With such a configuration, in the semiconductor test apparatus of the present invention, time series level data output from the first and second time interpolators can be classified and input to a data selection circuit via a bus, so that a desired clock can be input to desired output data. The data to be measured can be obtained by assigning the data to the data selection circuit. As a result, even when a plurality of first and second time interpolators and data selection circuits are provided depending on the device under test, the data under measurement can be obtained by arbitrarily combining the respective clocks and the output data, thereby making it more versatile and convenient. This high LSI tester can be realized.

1 is a block diagram showing a configuration of a semiconductor test apparatus according to a first embodiment of the present invention.

Fig. 2 is a signal diagram showing an example of operation in Hold Edge mode for acquiring output data output in accordance with an internal clock at the timing of the recovery clock obtained from the system clock of the device under test.

Fig. 3 is a signal diagram showing an operation example of the Hold Edge mode-when SDR: Rige Edge is selected as the edge selector mode.

Fig. 4 is a signal diagram showing an operation example of the Hold Edge mode-when DDR: Both Edge is selected as the edge selector mode.

Fig. 5 is a signal diagram when the output data is acquired at the edge timing of the system clock when the mode switch of the digital filter is switched to Direct Edge-(a) shows the edge timing of the clock as the rising edge, and (b) -When data is acquired at both edges of rising and falling.

Fig. 6 is a signal diagram when a recovery clock is acquired at the edge timing of rising and falling of the system clock in the digital filter by switching the edge selector mode to SDR: Rise Edge mode.

7 is a block diagram showing a configuration of a semiconductor test apparatus according to a second embodiment of the present invention.

8 is a block diagram showing a schematic configuration of a conventional general semiconductor test apparatus.

9 is a block diagram showing a schematic configuration of a semiconductor device for outputting data at a data rate of an internal clock that is higher than the system clock.

<The best form to perform invention>

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of the semiconductor test apparatus which concerns on this invention is described with reference to drawings.

[First Embodiment]

First, with reference to FIGS. 1-6, the 1st Embodiment of the semiconductor test apparatus which concerns on this invention is described.

1 is a block diagram showing a configuration of a semiconductor test apparatus according to a first embodiment of the present invention. As shown in FIG. 1, the semiconductor test apparatus according to the present embodiment includes an LSI tester 10 that performs a functional test of the device under test (DUT) 1, and the LSI tester 10 is a device under test. By obtaining the output data output from (1) as the data to be measured and comparing it with predetermined expected value data, it is determined whether the device under test 1 is tested.

The device under test 1 outputs a predetermined output data by inputting a signal from a pattern generator or the like not shown, and outputs a clock signal (system clock).

Thus, the clock is output from the LSI itself. For example, the LSI using the above-described "RapidIO" (registered trademark), "HyperTranport" (registered trademark), or the like for converting a bus system from the PCI bus to "RapidIO" Bridge LSI and the like, and the test apparatus of the present embodiment is capable of testing such a device.

In the device under test 1 of the present embodiment, an internal clock of frequency n times the system clock is generated by the PLL circuit or the like as the device shown in Fig. 9, and at the timing of the internal clock which is faster than the system clock. A device for performing data output is configured.

As this kind of device, for example, there is an ODR type device. The ODR type device generates an internal clock four times the system clock, and outputs data in synchronization with the rising and falling edges of the internal clock (DDR: Double Data Rate), thereby providing an eight times data rate of the system clock. Data output is realized. In the semiconductor test apparatus of this embodiment, an accurate test can also be performed on such an ODR type device.

The LSI tester 10 inputs the clock and output data output from the device under test 1 to each channel (each source synchronous circuit), thereby providing a suitable edge at a desired frequency from the system clock of the device under test 1. The recovery clock indicating the timing is taken out, the output data is acquired at the timing indicated by the recovery clock, and output as the data under measurement.

Specifically, the LSI tester 10 includes a source synchronous circuit (clock recovery circuit) 10a on the clock side for inputting a clock signal output from the device under test 1 as shown in FIG. And source synchronous circuits 10b, 10c, ..., 10n (not shown) on the data side for inputting output data output from the device under test 1.

Each of the source synchronous circuits 10a, 10b, 10c, ... has the same configuration except that the digital filter 40 is provided on the clock side, and the clock or output data output from the device under test 1 is output. The output is obtained as a plurality of strobes each having a constant timing interval, and output as level data of the time series. The output data is selected and acquired at the edge timing of the clock of the device under test 1 using the level data of the time series. I can do it.

Each of the source synchronous circuits 10a, 10b, 10c, ... corresponds to a pin with respect to each clock and output data output from the device under test 1, so that circuits of substantially the same configuration are assigned one by one.

In this embodiment, as shown in FIG. 1, one source synchronous circuit 10a is provided on the clock side of the device under test 1, and one to n output data sides of the device under test 1 are provided. Source synchronous circuits 10b, 10c, ... are provided. The source synchronous circuit 10a on the clock side, unlike the source synchronous circuits 10a, 10b, 10c, ... on the data side, constitutes a clock recovery circuit having the digital filter 40.

Each of the source synchronous circuits 10a, 10b, 10c, ... is connected to each other via the time interpolator bus 50, and the predetermined channel is controlled by the time interpolator bus 50 as described later. Signal input and output are performed between (source synchronous circuits).

As shown in Fig. 1, each of the source synchronous circuits has substantially the same configuration on both the clock side and the output side. Specifically, each of the source synchronous circuits includes a level comparator 11 and a pattern comparator 12. The interpolator 20 and the digital filter 40 are provided.

The level comparator 11 inputs an output signal (clock or output data) from the device under test 1 as in the case of a conventional LSI tester, and compares the level with a predetermined comparison voltage to time interpolator 20. Output the signal to.

The pattern comparator 12 compares the output data of the device under test 1 selected by the selector 30 with a predetermined expected value through the time interpolator 20 and the digital filter 40 described later, and outputs a test result. do.

The time interpolator 20 acquires clock or output data output from the device under test 1 by a plurality of strobes having a constant timing interval, and outputs them as level data of time series.

Specifically, the time interpolator 20 includes flip-flops 21a to 21n serving as a plurality of sequential circuits, a delay circuit 22, an edge selector 23, and an encoder 28.

In the present embodiment, the plurality of flip-flops 21a to 21n consist of a group of D-type flip-flops connected in parallel, and input output signals (clock or output data) output from the device under test through the level comparator 11, respectively. Enter as data. Then, the strobe input through the delay circuit 22 is used as a clock signal to output data input at a predetermined timing.

The first flip flops 21a of the plurality of flip flops 21a to 21n are used for initial values, and output data of the second and subsequent flip flops 21b to 21n is input to the selector 30 described later.

Here, the plurality of order circuits included in each time interpolator 20 may be constituted by order circuits other than the flip-flops 21a to 21n of the present embodiment, for example, latches.

Thus, even if a latch is provided as a sequence circuit of the time interpolator 20, the effect similar to the case of this embodiment can be exhibited.

In addition, as long as the order circuit provided in the time interpolator 20 can acquire the clock and output data from the device under test 1 at regular timing intervals and can output it as level data of time series, it demonstrated in this embodiment. Any circuit configuration other than the flip flops 21a to 21n and the latch may be used.

The delay circuit 22 sequentially inputs strobes delayed at regular timing intervals to the clock terminals of the flip-flops 21a to 21n, and outputs time series level data from the flip-flops 21a to 21n.

Here, the number of the plurality of flip-flops 21a to 21n and the delay amount of the delay circuit 22 can be arbitrarily set and changed, and the bit width of the level data of time series obtained by the time interpolator 20 (the Number) or resolution (delay amount of delay circuit) can be set to a desired value.

Thereby, the level data of time series acquired can be variously set according to the data rate, jitter width, etc. of the device under test 1 as a test object, and it is possible to respond to any LSI.

The strobes input to the flip-flops 21a to 21n can be set to arbitrary timings and frequencies, and the timing and delay amounts of the inputs can be different on the clock side and the output data side. In this embodiment, different timing generators and the like are provided for each channel 10a to 10n of the source synchronous circuit, so that the strobe can be input independently from the clock side and the output data side (STRB shown in Fig. 1). Reference). This makes it possible to adjust the timing according to the phase difference between the clock output from the device under test 1 and the output data. The clock and output data output from the device under test 1 are not always in phase, and for example, the setup time may be negative or may be positive. Therefore, in such a case, the timing of the strobe is changed on the clock side and the output data side, respectively, so that the strobe can be adjusted to be output at a timing suitable for the clock and the output data having a phase difference.

The edge selector 23 inputs time series level data output from the flip-flops 21a to 21n, and the level data indicating the rising edge, the level data indicating the falling edge, or the rising edge and the falling edge of the corresponding level data. The level data indicated is selectively output.

Specifically, in the edge selector 23 of this embodiment, the selector circuit group consisting of two AND circuits 24 and 25, one OR circuit 26, and one selector 27 is flip-flop 21a. A plurality is provided corresponding to the output of -21n).

As shown in Fig. 1, the first AND circuit 24 (24a to 24n) has an inverted output of one of the plurality of flip-flops 21a to 21n (for example, 21a) and a flip-flop of blocking. An AND circuit for inputting the non-inverting output of (for example, 21b). The output of this first AND circuit 24 is selected as the level data for SDR indicating the rising edge of the clock (SDR: Rise Edge mode).

As shown in Fig. 1, the second AND circuit 25 (25a to 25n) has a non-inverted output of one of the plurality of flip-flops 21a to 21n (e.g., 21a) and a blocking flip. An AND circuit for inputting the inverted output of the flop (for example, 21b). The output of this second AND circuit 25 is selected as the level data for SDR indicating the falling edge of the clock (SDR: Fall Edge mode).

The OR circuits 26 (26a to 26n) are OR circuits for inputting the outputs of the first and second AND circuits 24 and 25, as shown in FIG. The output of this OR circuit 26 is selected as level data for DDR indicating the edges of the clock rising and falling (DDR: Both Edge mode).

The selectors 27 (27a to 27n) input respective outputs of the first AND circuit 24, the second AND circuit 25, and the OR circuit 26, as shown in FIG. It is a selection circuit which consists of a multiplexer etc. which select and output either one by switching.

With such an edge selector 23, when time series level data acquired by a plurality of strobes is input through the flip-flops 21a to 21n, by selecting the selectors 27a to 27n, the first AND circuit ( 24) output (rising edge only; SDR: rise edge mode), ② output of second AND circuit 25 (falling edge only; SDR: fall edge mode), ③ output of OR circuit 26 (rising and falling both sides) Any one of DDR: Both Edge mode, is selected and output, and the edge timing indicated by the selected level data is encoded by the encoder 28 of the cutoff.

Since the selector circuit groups constituting the edge selector 23 input the output of one flip-flop and the cut-off flip-flop among the outputs of the plurality of flip-flops 21a to 21n, the selector 27a The level data selected and output from ˜27n) is one bit less data than the level data output from the flip-flops 21a to 21n. For example, when five bits of level data are output from the five flip-flops 21a to 21e, the level data selected and output by the edge selector 23 is output through four selectors 27a to 27d. It is 4 bits of data.

Therefore, the number of circuits included in the edge selector 23, that is, the first AND circuits 24a to 24n, the second AND circuits 25a to 25n, the OR circuits 26a to 26n, and the selectors 27a to 27n. Is one (1 to n-1) fewer than the flip-flops 21a to 21n, respectively.

The encoder 28 inputs time series level data output from the plurality of selectors 27a to 27n of the edge selector 23, and encodes and outputs the level data. Specifically, data sequentially output from the flip-flops 21a to 21n at regular intervals is sequentially input to the encoder 28 through the selectors 27a to 27n of the edge selector 23, and all data is input. The encoding is performed at the prepared timing, and the result is output.

Thereby, the level data of time series output from the flip-flops 21a-21n is selected via the edge selector 23, and the selected level data is output as encoded position data.

In the present embodiment, position data encoded by the encoder 28 of the source synchronous circuit 10a on the clock side is input to the digital filter 40, whereby a recovery clock indicating the edge timing of the system lock of the device under test 1 is obtained. It is supposed to be acquired.

Then, in the source synchronous circuits 10b, 10c, ... on the output data side, the time series level data output from the flip-flops 21a to 21n are input directly to the selector 30 as input data. Of the level data input to the selector 30 of the, one data is selected by the recovery clock output from the digital filter 40, and the selected one data is output as the data under measurement of the device under test 1. .

In addition, in the source synchronous circuits 10b, 10c, ... on the output data side, the edge selector 23 and the encoder 28 are not used in this embodiment (see Fig. 1). Therefore, the edge selector 23 and the encoder 28 can be omitted for the time interpolator 20 on the output data side.

The selector 30 inputs time series level data output from the plurality of flip-flops 21a to 21n as input data, and a recovery clock output from the digital filter 40 or a position output from the encoder 28. It is a data selection circuit which inputs data as a selection signal. Then, at the edge timing indicated by the recovery clock (or the position data of the encoder 28), that is, the edge timing of the system clock of the device under test 1, at the frequency timing of the faster internal clock of the system clock under test. The output data of the device 1 is selected and acquired as the data under measurement of the device under test 1.

Specifically, the selector 30 is made of a multiplexer or the like, and each output of the flip-flops 21b to 21n except for the flip-flop 21a for initial values among the plurality of flip-flops is directly connected to the data input side. The time interpolator bus 50 is connected to the select signal terminal.

The level data of time series output from the flip-flops 21a to 21n on the output data side is directly input to the selector 30 on the output data side without being inputted through the edge selector 23 and the encoder 28 as input data. By the control of the time interpolator bus 50, the recovery clock acquired by the digital filter 40 on the clock side or the position data acquired by the encoder 28 on the clock side is selectively input as a selection signal.

As a result, in the selector 30 on the output data side, the time series level data output from the flip-flops 21a to 21n of the output data side time interpolator 20 is recovered from the digital filter 40 or the encoder. Using the positional data from (28) as the selection signal, one data is selected.

The output data of the device under test 1 selected by the selector 30 is output to the pattern comparator 12, and is compared with a predetermined expected value by the pattern comparator 12, so that the test result is output.

The selection signal of the selector 30 is switched by the changeover switch 47 of the digital filter 40 described later.

On the other hand, the time-series level data output from the flip-flops 21a to 21n on the clock side are directly input to the selector 30 on the clock side without being inputted through the edge selector 23 and the encoder 28 as input data. By the control of the switching switch 47 of one digital filter 40, the position data acquired by the encoder 28 on the clock side, or the recovery clock acquired by the digital filter 40 on the clock side is selectively selected as a selection signal. Is entered.

As a result, in the selector 3 on the clock side, the system clock of the device under test 1 is selected as data, and the level of the time series output from the flip-flops 21a to 21n of the clock side time interpolator 20. Using the clock of the device under test 1 acquired as data as the recovery clock from the digital filter 40 or the position data from the encoder 28 as a selection signal, the edge timing that is the signal change point of the clock of the device is determined. It can acquire by the level data shown. Therefore, when the expected value is set for the clock of the device under test 1, the clock data output through the selector 30 can be compared with the predetermined expected value by the pattern comparator 12 on the clock side.

Here, the selector 30 on the clock side and the output data side switches the selection signal to be input by the control of the time interpolator bus 50, so that the desired selector 30 can be used.

Specifically, when the output data of the device under test 1 is compared with the expected value by using the selector 30 on the output data side, the digital filter 40 is connected via the time interpolator bus 50. The recovery clock or the signal from the encoder 28 on the clock side is input to the selector 30 on the output side as a selection signal. In this case, the selector 30 (and pattern comparator 12) on the clock side is not used.

On the other hand, when the clock of the device under test 1 is compared with the expected value by using the selector 30 on the clock side, the recovery clock of the digital filter 40 under the control of the time interpolator bus 50, Alternatively, the signal from the encoder 28 on the clock side is not input to the selector 30 on the output side. In this case, the selector 30 (and the pattern comparator 12) on the output data side is not used.

As described above, in the present embodiment, the selector 30 on the clock side and the output data side selectively receives the output signal from the time interpolator 20 in accordance with the test contents and the like. As a result, depending on the test contents and the like, the selector 30 may be provided on at least one of the source synchronous circuit on the clock side or the output data side, and the selector 30 on either the clock side or the output data side may be omitted. do.

The digital filter 40 is provided in the source synchronous circuit 10a on the clock side, and inputs and holds the position data of the clock output from the encoder 28 of the time interpolator 20 on the clock side. From the position data, a recovery clock indicating a predetermined edge timing is output. Specifically, the digital filter 40 includes a plurality of registers 41 (41a to 41n), an edge detection circuit 42, an edge changeover switch 43, an average value calculation circuit 44, and an average value changeover switch 45. And a timing correction circuit 46 and a mode changeover switch.

The plurality of registers 41a to 41n consist of a predetermined number (1 to n) of register groups connected in series as shown in Fig. 1, and are output from the encoder 28 of the time interpolator 20 on the clock side. The stored position data is sequentially stored, and the stored position data is output at a predetermined timing. For example, when the encoder 28 outputs 3-bit position data, each register 41a to 41n inputs and stores 3-bit position data, and a predetermined trigger signal is input to store the registers 41a to 41n. 3-bit position data is output.

More specifically, in the registers 41a to 41n, first, the position data of the encoder 28 is input to and stored in the register 41a at the foremost end, and the position data is output at a predetermined timing, so that the disconnection is performed in series. Are sequentially input to the registers 41b to 41n. The position data output from the last register n is input to an average value calculating circuit 44 which will be described later.

The position data output from each of the registers 41a to 41n is input to the blocking register and also to the average value calculating circuit 44, respectively. As a result, the average value calculating circuit 44 calculates the average value of the edge timings indicated by the position data of the registers 41a to 41n.

The position data output from the most recent register 41a is also input to the average value changeover switch 45 described later. Thereby, either position data is selected from the average value of the position data output from the average value calculation circuit 44, and the position data output from the frontmost register 41a.

The number of registers 41a to 41n according to the present embodiment can be arbitrarily set and changed, and the number of position data to be acquired and the resolution of the average value of the position data can be adjusted according to the number of registers 41a to 41n. Can be.

In other words, the registers 41a to 41n may include at least one register 41a for inputting position data output from the time interpolator, and the data rate, jitter width, and the like of the device under test 1 to be tested. Therefore, the optimal number can be achieved.

Then, strobes are input to these registers 41a to 41n at predetermined timings, and position data is outputted at arbitrary timings.

The edge detection circuit 42 detects the presence or absence of an edge of position data input from the encoder 28 of the time interpolator 20. When the edge is detected, the position data at which the edge is detected is stored in the register 41a at the foremost edge, and the position data already stored in each of the registers 41a to 41n is output.

As for the position data of the clock acquired by the time interpolator 20, a signal change point (rising edge or falling edge) is detected at regular intervals according to the clock frequency. Therefore, when position data is acquired by strobes faster than the clock period in each of the registers 41a to 41n, data which does not have a signal change point (rising edge or falling edge) is also acquired, in which case the edge is included in the position data. The timing will not appear. For this reason, even if such position data is stored in the registers 41a to 41n, the edge timing edge of the clock cannot be obtained from the position data.

Therefore, in this embodiment, the edge detection circuit 42 which detects the presence or absence of the edge of the position data acquired by the encoder 28 is provided, so that only the position data where the edge was detected is sequentially stored and output in the registers 41a to 41n. The recovery clock is obtained based on this position data.

Specifically, the edge detection circuit 42 inputs the position data from the encoder 28 and detects the presence or absence of the edge of the position data. When the edge of the position data is detected, the enable signal is output to the frontmost register 41a ("E" shown in FIG. 1), and the frontmost register 41a is made available for data input. . As a result, the position data where the edge is detected is stored in the register 41a at the foremost stage. On the other hand, when the edge of the position data is not detected, the edge detection circuit 42 does not output the enable signal. Therefore, when the edge of the position data is not detected, the most recent register 41a becomes incapable of input, and the position data where the edge is not detected is not stored in the register 41a.

The edge detection circuit 42 then inputs the enable signal back into the pulser 42a ("P" shown in FIG. 2), converts it into a trigger signal input to each of the registers 41a to 41n, and The trigger signal is input to each of the registers 41a to 41n, and the position data stored in each of the registers 41a to 41n is output at a predetermined timing.

As a result, only the position data of the position data acquired by the time interpolator 20 is detected in the registers 41a to 41n as position data which is a reference of the recovery clock, and is output as the position data at which the edge indicating the signal change point is detected. do. When the edge of the position data is not detected, the edge of the position data is detected in the subsequent cycle, so that the position data stored in each of the registers 41a to 41n is output.

By providing such an edge detection circuit 42, even when the edge of the system clock of the device under test 1 is not detected, a recovery clock can be acquired based on the position data already stored, and the frequency of the system clock can be obtained. Even when data is acquired at a faster timing, the accurate recovery clock can be output stably.

In addition, when the edge detection circuit 42 is provided in this manner and the recovery clock is output based only on the position data at which the edge is detected, the average value of the position data is calculated by the average value calculation circuit 44 to be described later and output as the recovery clock. In addition, a recovery clock indicating an accurate timing reflecting the actual edge timing of the system clock can be output.

The edge changeover switch 43 is connected to the edge detection circuit 42 and is input to the registers 41a to 41n through the pulser 42a of the edge detection circuit 42 and the time interpolator 20. Switching means for selectively switching the strobe output from the delay circuit 22. FIG.

When only the position data whose edge is detected by the control of the edge detection circuit 42 described above is stored in a register and used as a reference for the recovery clock, the edge of the position data may not be detected depending on the clock frequency, so that the position data may be acquired. There may be less position data. Therefore, in the present embodiment, an edge change switch 43 serving as a signal switching means is provided so that the strobe outputted at a predetermined timing can be input to the registers 41a to 41n, and the presence or absence of the edge of the acquired position data is present. Regardless of this, the recovery clock can be acquired by sequentially outputting predetermined position data.

Specifically, the edge change switch 43 is a timing signal (trigger signal) for outputting position data stored in the registers 41a to 41n, and is output from the pulser 42a of the edge detection circuit 42 described above. The mode for inputting the trigger signal (1) Edge Sync Mode shown in FIG. 2 and the mode for inputting the strobe output from the delay circuit 22 of the time interpolator 20 (2) are continuously connected. .

Then, this edge selector switch 43 is switched to select the strobe of the delay circuit 22 so that the delay circuit 22 of the time interpolator 20 is applied to the (2) Continuously Mode and the registers 41a to 41n. The strobe signal output at a predetermined timing can be inputted from the terminal, and position data can be output from each of the registers 41a to 41n regardless of the presence or absence of edge detection.

In the continuous mode, the enable signal is not input to the register 41a at the foremost end. Therefore, the position data stored in the register 41a is kept as it is, and the registers at the front end of the register 41b to 41n after the interruption. The position data output from (41a to 41n-1) is stored. Therefore, when the edges of the position data are detected, each of the registers 41a to 41n sequentially stores and outputs the position data as in the case of the edge detection circuit 42 described above. If is not detected, the position data of all cycles already stored are sequentially output and stored in the register of interruption. As a result, in this continuous mode, position data indicating the edge timing is sequentially output at the timing of the strobe of the delay circuit 22 regardless of whether edge data is detected or not.

Thus, in this embodiment, by providing the edge change switch 43, when the edge of the position data from the time interpolator 20 is not detected, position data is output from the register 41 which becomes a reference | standard of a recovery clock. You can select whether or not (① Edge Sync Mode) or output position data of all cycles stored in the register (②Continuously Mode). Thus, for example, by using only the actual edge timing of the system clock of the device under test, when performing a more rigorous functional test or jitter analysis, only the position data where the edge is detected is selected (①Edge Sync Mode), When performing a logic test that checks the output data or clock data of the device under test from the average value of the period, the position data may be selectively selected depending on the test contents and the like, such as using the position data of all cycles already stored (②Continuously Mode). It can be adopted.

The average value calculating circuit 44 inputs position data respectively output from the plurality of registers 41a to 41n, calculates an average value of edge timings indicated by each position data, and outputs the average value as a recovery clock. Specifically, the average value calculating circuit 44 inputs the position data output from the registers 41a to 41n, adds all the position data, and registers the addition result of the adding circuit 44a. The division circuit 44b divided by the number n is provided.

By providing such an average value calculation circuit 44, it is possible to calculate an average value of a plurality of position data stored in each of the registers 41a to 41n, and output the average value as a recovery clock. As a result, the recovery clock can be an accurate and proper timing signal reflecting the edge timing of the actual clock of each device under test, and even when the edge of the clock is not detected or when the edge timing changes due to jitter, It is possible to obtain a more accurate recovery clock based on the average value.

The average value changeover switch 45 is a switching means for selecting one of an average value output from the average value calculation circuit 44 and position data output from one of the plurality of registers 41 and outputting it as a recovery clock.

Specifically, in the present embodiment, the average value changeover switch 45 is selectively connected to the output side of the average value calculating circuit 44 and the output side of the register 41a at the foremost stage, and the average value of the plurality of position data described above. 2), or outputting position data output from the frontmost register 41a, that is, position data acquired in the current test cycle (same as ②Sampling Mode). It is supposed to be.

Thereby, as a recovery clock output from the digital filter 40, the position data output from a specific register (in this embodiment, the most recent register 41a) and the average value of the position data of a plurality of registers are selectively output. Therefore, the recovery clock can be selectively divided according to the test contents and the like. For example, when performing a functional test in consideration of the timing variation caused by jitter, the system clock of the device under test is outputted as a recovery clock (1) Smoothing mode, and irrespective of the timing variation caused by jitter. When performing a logic test that checks the clock data of the test device itself, the division of a plurality of registers using position data output from one register (most register 41a) as a recovery clock (2 Sampling Mode) It becomes possible to use.

The timing correction circuit 46 adds a predetermined correction value to the position data output via the average value changeover switch 45, corrects the edge timing indicated by the position data, and outputs it as a recovery clock. Specifically, the timing correction circuit 46 is connected to the output side of the average value changeover switch 45 as shown in FIG. 1, and the correction value register Tsd is used for the position data output from the average value changeover switch 45. The predetermined correction value stored in Thd Reg) 46a is added.

The position data output from the timing correction circuit 46 becomes a recovery clock finally output from the digital filter 40.

The correction value stored in the correction value register 46a becomes a setting value which sets the setup time and hold time of the output data of the device under test 1 in this embodiment. In general, in order to acquire the output data stably by the clock signal, it is necessary to consider the setup time and the hold time of the output data with respect to the clock. Therefore, in the present embodiment, the correction value indicating the set values of the setup time and the hold time is stored in the correction value register 46a, and the position data output from one register (the most recent register 41a) or all the registers. The set value of the setup time or the hold time can be added to the timing correction circuit 46 with respect to the average value of the position data of 41a to 41n.

Here, the set value of the setup time or the hold time can be set in accordance with the resolution of the level data acquired by the time interpolator 20.

For example, when the clock of the device under test 1 is acquired with an 8-bit strobe, it can be set as a value for changing the edge timing of the position data by an arbitrary number of bits within the range of the 8-bit strobe. Specifically, it can be set to "0", "+1", "-2" or the like as the setting value. With this setting value, the edge timing of the position data is set within the range of, for example, an 8-bit strobe. Correction such as slowing down by 1 bit or faster by 2 bits can be performed. As a result, the recovery clock corrected at the appropriate edge timing can be output by adding the setup time and the hold time of the output data.

The recovery clock output from the timing correction circuit 46 is input to the selector 30 as a selection signal, so that the level clock data output from the time interpolator 20 can be acquired by the recovery clock corrected at an appropriate timing. It becomes possible.

The mode changeover switch 47 selects one of the position data output from the encoder 28 on the clock side and the recovery clock output from the timing correction circuit 46 of the digital filter 40, thereby selecting the clock side and output data. It is a switching means output to the selector 30 on the side as a selection signal.

Specifically, in the present embodiment, the mode changeover switch 47 is selectively connected to the output side of the encoder 28 on the clock side and the output side of the timing correction circuit 46 of the digital filter 40. 28 can be switched between acquiring position data (1) Direct Edge shown in FIG. 1 and acquiring a recovery clock obtained by the digital filter 40 (2) Hold Edge. By switching the mode switching switch 47, when the output data is output at the timing of the system clock of the device as in the case of a normal SDR type device, for example, (1) Direct Edge is selected, and a device like the ODR type device is selected. ② Hold Edge can be selected when testing a device that outputs data at the data rate of the internal clock that is higher than the system clock.

In the present embodiment, the digital filter 40 described above is provided only in the source synchronous circuit 10a on the clock side, and is not provided in the source synchronous circuits 10b, 10c, ... on the data side. However, the digital filter 40 may be provided in the source synchronous circuits 10b, 10c, ... on the output data side. In this way, the source synchronous circuits on the clock side and the output data side can be configured in exactly the same configuration. For example, a plurality of source synchronous circuits corresponding to papine can be configured in the LSI tester in the same configuration. The clock and output data of the device under test can be allocated to any channel of the device, the assignment operation can be performed easily and efficiently, and the data pin and the clock pin can be arbitrarily replaced.

Further, if the digital synchronous filter 40 is also provided in the source synchronous circuits 10b, 10c, ... on the output data side, the clock is multiplexed to the output data inside the device, for example, represented by a serializer and deserializer (SERDES). Also, a test can be performed by recovering the multiplexed clock with the digital filter 40 even for a device to which output data is output at the edge timing of the multiplexed clock.

The time interpolator bus 50 is a transmission line connecting the source synchronous circuit 10a on the clock side and the source synchronous circuits 10b, 10c, ... on the output data side, respectively. As shown in Fig. 1, the time interpolator bus 50 of this embodiment includes a select terminal of the selector 30 of each channel (source synchronous circuit) on the output data side, and a timing correction circuit of the digital filter 40 ( 46 is connected to the output terminal of the encoder 28 on the clock side, and to which selector 30 of each channel on the output data side is the recovery clock of the digital filter 40 or the clock side encoder 28. Switch control for inputting the position data of &quot;) as a selection signal.

Although not shown in FIG. 1, a plurality of time interpolator buses 50 for classifying data into a plurality of source synchronous circuits are provided corresponding to each source synchronous circuit (each channel).

In addition, the information of which channel of the recovery clock of the digital filter 40 or the signal of the clock side encoder 28 is input as a selection signal is normally given beforehand to the selector 30 of which channel. Therefore, according to the information, the switch can be set to ON / OFF before using the test apparatus. The ON / OFF control information can be written to a control register or the like not shown.

By providing such a time interpolator bus 50, the recovery clock acquired by the digital filter 40 on the clock side can be input to the desired selector 30 on the output data side as a selection signal. Thereby, the output data acquired by the desired channel can be acquired as data under measurement.

Therefore, even when a plurality of source synchronous circuits including the selector 30 are provided in accordance with the configuration, data rate, jitter width, and the like of the device under test 1, the data under measurement is acquired by arbitrarily combining the clock data and the output data. can do. For example, when a plurality of clocks and output data are output from the device under test 1, the clock pin and the data pin are arbitrarily replaced, such as "clock 1 and output data 1" and "clock 2 and output data 2". can do. In this case, data to be measured can be acquired independently at the timing of "clock 1" for "output data 1" and at "clock 2" for "output data 2".

In addition, the selector 30 on the clock side stores the recovery clock of the digital filter 40 or the position data of the clock side encoder 28 through the mode changeover switch 47 without passing through the time interpolator bus 50. It is directly input as a selection signal. Thereby, for example, the signal of "clock 1" is acquired as the data under measurement at the timing of "clock 1".

Next, the test operation | movement in the semiconductor test apparatus which concerns on this embodiment which consists of the above structures is demonstrated.

First, when a predetermined test pattern signal is input to the device under test 1 from a pattern generator (not shown) provided in the test apparatus, the predetermined clock (system clock) and output corresponding to the pattern signal from the device under test 1 are output. The data is output.

The clock and output data output from the device under test 1 are input to respective source synchronous circuits 10a, 10b, 10c, ... connected to each output terminal.

The clock and output data input to the respective source synchronous circuits are input to the level comparator 11, level compared with the comparison voltage, and then input to each time interpolator 20.

The signal (clock or output data) input to each time interpolator 20 is first input to a plurality of flip-flops 21a to 21n connected in parallel. The strobe is input to the clock terminals of the flip-flops 21a to 21n to which the clock or output data is input by the delay circuit 22 at regular timing intervals. As a result, the clock or output data input from each of the flip-flops 21a to 21n is acquired and output as level data of time series.

Then, in the source synchronous circuit 10a on the clock side, time-level level data output from the flip-flops 21a to 21n is input to the edge selector 23.

The level data input to the edge selector 23 is input to the plurality of selectors 27a to 27n through the first and second AND circuits 24 and 25 and the OR circuit 26 to change the edge select signal. One signal is selected and output. The level data output from these selectors 27a to 27n is only the rising edge (output of the first AND circuit 24) indicated by the level data (only the falling edge) (the output of the second AND circuit 25), (3) It is output as level data indicating the timing of either the edges of the rising and falling (output of the OR circuit 26).

The level data acquired by this edge selector 23 is input to the encoder 28 and encoded.

The level data encoded by the encoder 28 becomes position data indicating the edge timing of the system clock of the device under test 1 (1) rising edge, 2) falling edge, or 3) both rising and falling edges. This position data is input to the digital filter 40 and acquired as a recovery clock corrected at an appropriate timing.

The level data of the time series output from the flip-flops 21a to 21n are directly input to the selector 30 on the clock side as input data. When the clock has an expected value, the clock data is acquired and the pattern comparator 12 It is possible to determine whether or not.

In the digital filter 40, the position data of the system clock output from the encoder 28 is input to the register 41a at the foremost stage and sequentially input to the blocking registers 41b to 41n.

First, position data is input to the edge detection circuit 42, and the presence or absence of the edge is detected. At this time, the enable signal output from the edge detection circuit 42 is used as a timing signal (trigger signal) for outputting the position data stored in the registers 41a to 41n by switching the edge changeover switch 43. Either mode is selected from the case of input (① Edge Sync Mode shown in FIG. 2) and the input of the strobe signal output from the delay circuit 22 of the time interpolator 20 (samely, ② Continuously Mode). do.

(1) When Edge Sync Mode is selected, the edge detection circuit 42 inputs the position data from the encoder 28 to detect the presence or absence of an edge. When the edge of the position data is detected, the edge detection circuit 42 enters the register 41a at the foremost register. Input the enable signal. As a result, only the position data where the edge is detected is stored in the register 41a at the foremost stage.

The edge detection circuit 42 converts the enable signal into a trigger signal through the pulser 42a, inputs the trigger signal to each of the registers 41a to 41n, and is stored in each of the registers 41a to 41n. Output position data.

As a result, only the position data of the position data acquired by the time interpolator 20 is detected, in which the edge indicating the signal change point is detected, in the registers 41a to 41n sequentially as the position data as the reference for the recovery clock. When the edge of the position data is not detected, the edge of the position data is detected in the subsequent cycle, so that the position data stored in each of the registers 41a to 41n is output.

On the other hand, when (2) Continuously Mode is selected, the strobe signal is input from the delay circuit 22 of the time interpolator 20 to the registers 41a to 41n regardless of the presence or absence of edge detection in the edge detection circuit 42.

When the edges of the position data of the system clock are detected in each of the registers 41a to 41n, the position data is sequentially stored and output as in the case of the edge detection circuit 42 described above. If the edge of the position data is not detected, the position data of all cycles already stored is output and stored in the register for blocking.

As a result, in continuous mode, position data indicating the edge timing is continuously output at the timing of the strobe of the delay circuit 22, regardless of the edge detection of the position data, and stored and output in each register 41a to 41n. do.

The position data output from the registers 41a to 41n is input to the average value calculating circuit 44, and the average value of the edge timing indicated by each position data is calculated.

Then, by switching the average value changeover switch 45, whether the average value output from the average value calculation circuit 44 is output (①Smoothing Mode) or the position data output from the frontmost register 41a is output as it is (②Sampling Mode). ) Is switched, and any position data is output to the timing correction circuit 46.

The timing correction circuit 46 adds the set value (correction value) of the setup time or hold time stored in the correction value register 46a, and outputs the position data as a recovery clock corrected at an appropriate edge timing.

The recovery clock output from the timing correction circuit 46 is sent to the source synchronous circuit on the predetermined output data side via the mode switching switch 47 and the time interpolator bus 50, and the corresponding output data side. The selector 30 is input as a selection signal.

First, when (1) Direct Edge is selected by switching of the mode switching switch 47, the position data output from the encoder 28 on the clock side is selected by the selector 30 on the output data side via the time interpolator bus 50. It is input as a signal. As a result, the selector 30 on the output data side selects the output data of the device at the edge timing of the system clock output from the device under test 1.

On the output data side, the time series level data obtained from the flip-flops 21a to 21n are input as input data to the selector 30 as it is, except for the data of the flip-flop 21a for initial values, and the selector ( In 30), the timing data from the encoder 28 on the clock side is used as the selection signal, one data is selected from the level data of time series representing the output data, and this data is output as the data under measurement.

Thereby, in this mode (①Direct Edge), an SDR type device test in which output data is output at the timing of the system clock of the device can be performed.

On the other hand, when (2) Hold Edge is selected by switching the mode switching switch 47, the recovery clock output from the digital filter 40 on the clock side of the selector 30 on the output data side is transferred via the time interpolator bus 50. It is input as a selection signal. Thereby, the selector 30 on the output data side uses the recovery clock acquired by the digital filter 40 as the selection signal, and output data of the device under test 1 is selected at the edge timing indicated by the recovery clock.

Therefore, in this mode (2 Hold Edge), it is possible to test a device in which output data is output at a data rate of an internal clock that is higher than the system clock of the device, such as an ODR type device.

The output data selected and output by the selector 30 on the output data side is input to the pattern comparator 12, compared with predetermined expected value data output from the pattern generator in the tester, and a comparison result is output.

By the comparison result, the coincidence and inconsistency between the output data and the expected value is detected, and the determination of Pass / Fail of the device under test 1 is performed. In other words, if the output of the selector 30 matches the expected value, the pass is judged, and in the case of a mismatch, the fail is determined.

Similarly, in the selector 30 on the clock side, the time series level data of the clocks acquired by the flip-flops 21a to 21n are transferred to the selector 30 on the clock side as it is except for the data of the flip-flop 21a for the initial value. Since it is input as input data, the selector 30 on the clock side uses the position data (① Direct Edge) from the encoder 28 on the clock side or the recovery clock (② Hold Edge) from the digital filter 40 as a selection signal. Among the level data of the time series representing the system clock, one data is selected, and this data is output as the measured data of the clock.

Thereby, by inputting the data output from the selector 30 on the clock side into the pattern comparator 12, the system clock of the device under test 1 can be compared with the predetermined expected value data, and the comparison result with the expected value. As a result, the coincidence and inconsistency between the clock data and the expected value can be detected, and determination of pass / fail of the device under test 1 can be performed using only the clock signal.

EXAMPLE

Hereinafter, with reference to FIGS. 2-6, a specific Example is described.

[Default Behavior of Hold Edge Mode]

First, with reference to FIG. 2, the basic operation | movement at the time of acquiring the output data of the device under test 1 using the recovery clock obtained by the digital filter 40 in the semiconductor test apparatus which concerns on this embodiment is demonstrated. 2 is a signal diagram showing an example of operation of the Hold Edge mode in which output data output in accordance with the internal clock is acquired at the timing of the recovery clock obtained from the system clock of the device under test 1.

In the example shown in FIG. 2, the device under test 1 is an ODR-type device in which data is output in synchronization with both edges of rising and falling of an internal clock four times the frequency of the system clock, which is eight times the system clock. The output data is output at the data rate of. Therefore, in the test apparatus of this embodiment, the test is performed in the Hold Edge mode using the recovery clock.

In the time interpolator 20 of each source synchronous circuit, the system clock and output data output from the device under test 1 are used as level data of the number of bits "4" at the frequency timing of the internal clock of the device under test 1. Is acquired. In the edge selector 23 of the time interpolator 20, SDR: Rise Edge is selected, and in the digital filter 40, the edge change switch 43 is in a ②Continuously Mode, and the average value change switch 46 is in a ①Smoothing Mode, The mode changeover switch 47 is set at ② Hold Edge (see FIG. 1).

As shown in Fig. 2, first, only the rising edge of the clock is acquired by the 4-bit strobe by the flip-flops 21a to 21n on the clock side of the system clock output from the device under test 1 (SDR: Rise Edge).

In the example of FIG. 2, the edge timing at which the system clock goes from "L" to "H" is shown in the third bit position of the 4-bit strobe.

This system clock is first input to the flip-flops 21a to 21n, and level data of "0011" ("H" from the position of the number of bits "3") is obtained, for example. This level data is selected via the edge selector 23, and is encoded by the encoder 28 into position data (e.g., "10") indicating the number of bits "3". Thereby, the timing data output from the time interpolator 20 becomes position data "10" which shows the number of bits "3", for example.

This position data is sequentially input to the registers 41a to 41n of the digital filter 40.

In the digital filter 40, ②Continuously Mode is selected as the edge change switch 43. When the edge of the position data is detected, the position data is output. When the edge is not detected, the position data of the entire cycle is output. In the registers 41a to 41n, position data (e.g., "10") indicating the number of bits "3" is stored and output sequentially from the most recent register 41a.

In the digital filter 40, the average value changeover switch 46 selects the smoothing mode, and the average value of the n position data outputted from the n registers is calculated, and " 10 " representing the average value bit number " 3 " Is output.

The set value of the setup time is added to the timing correction circuit 46 with respect to this average value. In the example shown in FIG. 2, the setup time "0" is added, and the position data after the correction is "10", for example.

This position data is output as a recovery clock and input to each selector 30 on the output data side via the time interpolator bus 50.

In the selector 30 on the output data side, first, output data of the device under test 1 obtained by the flip-flops 21a to 21n of the time interpolator 20 is directly input to each input terminal. At the same time, the recovery clock is input as a selection signal from the digital filter 40 to each selector 30 on the output data side.

As a result, the selector 30 on the output data side uses the recovery clock as a selection signal, and as shown in Fig. 2, the data of the input terminal corresponding to "10" (the number of bits "3") indicated by the recovery clock is internal. It is selected (input) in the cycle of the clock, and as a result, the predetermined "H" or "L" data is output from the selector 30.

The data output from the selector 30 is compared with a predetermined expected value by the pattern comparator 12, and the result (pass / fail shown in FIG. 2) is stored in a fail analysis memory (not shown).

[Hold Edge Mode]

Next, an embodiment in the case where the edge selector 23 on the clock side is switched in the Hold Edge mode shown in FIG. 2 will be described with reference to FIGS. 3 and 4. 3 and 4 are signal diagrams illustrating an operation example of a hold edge mode similarly to FIG. 2, and FIG. 3 is a diagram illustrating DDR: Both Edge when SDR: Rise Edge is selected as a mode of the edge selector 23. This is the case. In the example shown in Figs. 3 and 4, similarly to the basic operation shown in Fig. 2, output data is acquired by the strobe of the bit number " 4 ", but the number of bits of the strobe can be arbitrarily changed.

First, as shown in FIG. 3, when the selection signals of the selectors 27a to 27n of the edge selector 23 are switched and the output of the first AND circuit 24 is selected (SDR: Rise Edge), the device under test Position data of only the timing of the rising edge of the system clock of (1) is acquired. In the example shown in Fig. 3, the edge timing from "L" to "H" of the clock is acquired at the "third bit" position of the 4-bit strobe in the first cycle of the system clock.

The position data " 10 " representing the " third bit " is stored in the digital filter 40, and is output at the frequency timing of the internal clock, and this position data is used as the recovery clock by the selector 30 on the output data side. Is entered.

When SDR: Rise Edge is selected as the edge selector 23 in this manner, output data is acquired at the edge timing of only the rising edge of the system clock. In addition, the case where the position data of only the falling edge of the system clock is acquired (SDR: Fall Edge) is also the same as the case of obtaining the position data of only the rising edge.

Next, as shown in Fig. 4, when the selection signals of the selectors 27a to 27n of the edge selector 23 are switched to select the output of the OR circuit 26 (DDR: Both Edge), the device under test ( Position data of timings of both edges of the rising and falling of the system clock of 1) is acquired. In the example shown in Fig. 4, in the first cycle of the system clock, the edge timing at which the clock goes from "L" to "H" is acquired at the "third bit" position of the 4-bit strobe, and the clock is from "H". It is a case where the edge timing which becomes "L" is acquired in the "second bit" position of a 4-bit strobe.

The digital filter 40 stores position data (for example, "10") indicating the rising edge "third bit" and position data (for example "01") indicating the falling edge "second bit". It is stored sequentially and output at the frequency timing of the internal clock. This position data is input to each selector 30 on the output data side as a recovery clock.

In this DDR: Both Edge, as shown in Fig. 4, the output data of the device under test 1 is obtained at the "third bit" edge timing of rising and falling at the first to second cycles of the internal clock, In the third to fourth cycles, output data is acquired at the "second bit" edge timing of rising and falling. Therefore, in this case, it is possible to acquire data with further improved tracking performance as compared with the case of SDR: Rise Edge (or Fall Edge) shown in FIG.

[Direct Edge Mode]

Next, the Example at the time of switching the mode changeover switch 47 of the digital filter 40 to Direct Edge in the test apparatus of this embodiment is demonstrated with reference to FIG. FIG. 5 is a signal diagram when the output data is acquired at the edge timing of the system clock when the mode changeover switch 47 of the digital filter 40 is switched to Direct Edge, and (a) increases the edge timing of the clock. At the edge, (b) is the case of acquiring data at both edges of rising and falling.

In the test apparatus of the present embodiment, by switching the mode changeover switch 47 to Direct Edge, position data acquired by the encoder 28 on the clock side is input to the selector on the output side, and the device is operated like a normal SDR or DDR type device. The device in which the output data is output at the timing synchronized with the system clock can be tested.

First, as shown in Fig. 5A, when the output data is acquired at the timing of the rising edge of the clock for the SDR type device, the selection signals of the selectors 27a to 27n of the edge selector 23 are applied. By switching, the output of the first AND circuit 24 is selected (SDR: Rise Edge). As a result, the output data of the device under test 1 is acquired at the timing of the rising edge of the clock of the device under test 1.

In the example shown in Fig. 5A, output data is acquired at the timing of the "third bit" position of the 8-bit strobe at the first cycle, and at the timing of the "third bit" position at the second cycle as well.

In addition, when the output data is acquired at the timing of the falling edge of the clock with respect to the SDR type device, the selection signal of the selectors 27a to 27n of the edge selector 23 is switched to convert the second AND circuit 25. By selecting the output (SDR: Fall Edge), the same can be done.

Next, when the output data is acquired at the edge timings of both the rising and falling of the system clock, the selection signal of the selectors 27a to 27n of the edge selector 23 is switched to the DDR type device, and the OR circuit is switched. Select the output of (26) (DDR: Both Edge). Thereby, the output data of the device under test 1 is acquired at the timing of both the rising and falling edges of the clock of the device under test 1.

In the example shown in Fig. 5B, the output data is output at the "third bit" timing of the 4-bit strobe at the rising edge of the clock and at the timing of the "third bit" position of the 4-bit at the falling edge. Is acquired.

Similarly, output data is acquired at the "third bit" timing of four bits at the rising edge of the clock at the second cycle, and at the timing of the "third bit" position at the falling edge. Thereby, the output data of a normal DDR type device can be acquired at the timing of DDR synchronized with a system clock.

It is of course also possible to test the conventional SDR and DDR type devices as described above using the recovery clock obtained by the digital filter 40. By using the recovery clock acquired by the digital filter 40 with respect to the DDR-type device, only an edge timing having good precision is used, for example, in the case of a device having a poor precision of either the rising edge or the falling edge of the system clock. Data can be obtained.

For example, as shown in Fig. 6A, when the precision of the falling edge of the system clock is poor, when data is acquired at the timing of the falling edge, the data becomes normal even if the timing of the data is normal.

Therefore, in such a case, the edge selector 23 is switched to SDR: Rise Edge mode, and the digital filter 40 acquires the recovery clock at the edge timing of rising of the system clock. By acquiring the output data at the edge timing of the recovery clock, as shown in Fig. 6B, the output data can be acquired at the data rate of DDR and at the timing of the rising edge of the system clock with good accuracy. Can be.

As described above, according to the semiconductor test apparatus according to the present embodiment, first, by providing the time interpolator 20 in each channel of the source synchronous circuit, the clock and the output data output from the device under test 1 are obtained in time series. Can be acquired as level data. The level data of this time series represents the edge timing which is a signal change point of the clock (and output data) of the device under test 1. Therefore, by inputting the system clock signal output from the device under test 1 into the time interpolator 20 and acquiring the level data and the position data indicating the edge timing thereof, the position data of the device under test 1 is obtained. It can be used as a timing signal for acquiring output data.

In particular, in the present embodiment, the edge selector 23 is provided in the time interpolator 20 on the clock side, and the level data of the time series acquired by the time interpolator 20 is used as the rising edge or the falling edge of the clock. Or it can output selectively as level data which shows the timing of both edges of a rise and a fall. As a result, the output data can be obtained at the edge timings of both the rising edge and the falling edge of the clock of the device under test 1, and it is possible to cope with the DDR type device.

In the present embodiment, the digital synchronous filter 40 is provided in the source synchronous circuit 10a on the clock side to hold and store the position data of the clock acquired by the time interpolator 20, and to multiply the frequency of the system clock. Can be output as a recovery clock corrected at a desired timing.

The time interpolator 20 on the clock side can acquire level data and position data indicating the edge timing of the clock. However, as described above, when the device under test 1 is an ODR-type device that outputs data at both edge timings of rising and falling of an internal clock four times the frequency of the system clock, the system clock of one-fourth frequency is used. Even when the rising edge (or falling edge) of is obtained, only one rising edge (or falling edge) can be detected once every eight times. In other cycles, the signal change point (rising or falling edge) cannot be detected, and as a result, the timing edge of the internal clock of four times the frequency can only be acquired once every eight times. In addition, the clock signal output from the device under test 1 has jitter, and the edge timing indicated by the clock position data may not be an appropriate timing as a timing signal for acquiring the test data.

Therefore, by inputting and storing the position data of the system clock of the device under test 1 acquired by the time interpolator 20 on the clock side to the digital filter 40, it corresponds to an internal clock of n times the frequency of the system clock. As a clock signal indicating one edge timing, a recovery clock corrected at an accurate and proper timing can be output.

The selector (data selection circuit) 30 that selects the output data of the device under test 1 as the recovery clock is used as the selection signal, so that the level data of time series of the output data acquired by the time interpolator 20 is provided. Can be selected and output as measured data to be compared with predetermined expected value data.

Thereby, even when the output data output from the device under test 1 is output based on an internal clock that is faster than the system clock output from the device, and even when the system clock fluctuates due to jitter, The recovery clock indicating the appropriate edge timing can be output.

In this manner, according to the semiconductor test apparatus according to the present embodiment, a recovery clock can be obtained which is not influenced by the frequency of the system clock of the device under test 1, the influence of jitter, or the like, and the test under test is performed using the recovery clock. Since the output data of the device 1 can be acquired, even if it is a high speed semiconductor device, such as an ODR type device, it becomes possible to perform an accurate test easily and reliably.

Second Embodiment

Next, with reference to FIG. 7, the 2nd Embodiment of the semiconductor test apparatus which concerns on this invention is described.

7 is a block diagram showing the configuration of a semiconductor test apparatus according to a second embodiment of the present invention. As shown in FIG. 7, the semiconductor test apparatus according to the present embodiment is a modified embodiment of the first embodiment described above, and is provided to a source synchronous circuit (clock recovery circuit) 10a on the clock side in the first embodiment. And the jitter detection circuit 60 is further provided.

Therefore, the other component part is the same as that of 1st Embodiment, The same component part is attached | subjected the same code | symbol as 1st Embodiment in drawing, and detailed description is abbreviate | omitted.

The jitter detection circuit 60 inputs the position data output from the registers 41a to 41n of the digital filter 40 and becomes a reference for the recovery clock, and detects the phase difference of the edge timing indicated by the position data, thereby detecting the phase difference. Is acquired and analyzed as jitter of the clock (system clock) of the device under test 1. Specifically, the jitter detection circuit 60 includes a subtraction circuit 61, a jitter limit value register 62, and a comparison determination circuit 63.

The subtraction circuit 61 inputs the two position data which are compared from the digital filter 40, and calculates the phase difference of the edge timing which each position data represents.

The position data (recovery clock) acquired by the digital filter 40 represents the edge timing of the clock of the device under test 1, and by subtracting the position data, the phase difference of the position data, that is, the device under test 1 The jitter width of the clock can be obtained.

For example, when the output data output from the device under test 1 is acquired with a 7-bit strobe, the position data indicating the edge timing is "-3, -2, -1, 0, +1, +2." 7 types of "+3" are acquired. Therefore, if the position data are subtracted from each other, the phase difference data obtained is "-6, -5, -4, -3, -2, -1, 0, +1, +2, +3, +4, + 5, + 6 ”. Then, when the position data indicating the number of bits "-2" and the position data indicating the number of bits "+1" are input to the subtraction circuit 61, for example, these position data are subtracted. When

"+1"-"-2" = "+ 3"

Thus, it is calculated that the phase difference of the position data is "+3".

Thus, the phase difference calculated by the subtraction circuit 61 shows the jitter width which the output data of the device under test 1 has, and by acquiring this phase difference, the jitter analysis of the device under test 1 can be performed. .

Here, in the present embodiment, the subtraction circuit 61 is connected to the output side of the resistor 41a at the foremost end of the digital filter 40, and through the jitter selector 61a, the blocking resistors 41b to 41n and the average value. The output side of the calculation circuit 44 is selectively connected to any one.

As a result, when the position data output from the register 41a at the foremost end and the position data of any one of the blocking registers 41b to 41n are inputted to the subtraction circuit 61 and subtracted (shown in FIG. 7). (1) When the cycle to cycle jitter, the position data of the foremost register 41a, and the position data representing the average value calculated by the average value calculating circuit 44 are subtracted (2 cycle to smoothing jitter shown in Fig. 7), It can be converted.

The jitter limit value register 62 stores a predetermined jitter limit value compared with the phase difference calculated by the subtraction circuit 61.

The comparison determination circuit 63 compares the phase difference calculated by the subtraction circuit 61 with the jitter limit value stored in the jitter limit value register 62, and determines the pass / fail. For example, when the phase difference calculated by the subtraction circuit 61 exceeds the jitter limit value, it is determined as "Fail", and when it does not exceed the jitter limit value, it is determined as "Pass".

The result of the judgment of the comparison judgment circuit 63 is stored in the fail analysis memory or the like, similarly to the result of the judgment of the success and failure in the pattern comparator 12 described in the first embodiment.

In this embodiment, as shown in FIG. 7, the decision change switch 64 is provided in the input part to a fail analysis memory, etc., and it is the mode which stores the result of the quality judgment in the pattern comparator 12 with respect to a fail analysis memory. (1) Data Exp Mode shown in FIG. 7 and a mode (samely, 2 Jitter Fail Mode) for storing the judgment result of the comparison judgment circuit 63 can be switched.

As described above, according to the semiconductor test apparatus according to the present embodiment, the jitter detection circuit 60 for inputting a plurality of recovery clocks includes subtraction of position data indicating the edge timing of each recovery clock, thereby providing a phase difference between the recovery clocks. Can be detected. In addition, the distribution of the phase difference detected by the jitter detection circuit 60 can be obtained and output as distribution data indicating the variation or enlargement of the phase difference.

The phase difference of the recovery clock represents the jitter of the clock signal multiplexed with the output data of the device under test 1, and by acquiring the phase difference of the recovery clock and its distribution data, the output data and multiplexing of the device under test 1 are obtained. The jitter analysis of the clock can be performed.

As a result, in the present embodiment, there is no problem as in the case of using a conventional jitter measuring instrument, such as an error caused by an operation of an oscilloscope or the like, or a difficulty in measuring operation. Jitter analysis of the clock (or output data) of the device under test can be performed.

As mentioned above, although preferred embodiment of the semiconductor test apparatus of this invention was described, the semiconductor test apparatus which concerns on this invention is not limited only to embodiment mentioned above, Of course, various changes are possible in the scope of this invention.

For example, although the test apparatus provided with the jitter detection circuit which acquires and analyzes the jitter of the device under test was shown in 2nd Embodiment mentioned above, as a means of detecting and analyzing jitter, jitter detection shown in 2nd Embodiment It is not limited to the circuit but may include other jitter analysis means.

For example, the phase difference of the recovery clock detected by the jitter detection circuit shown in the second embodiment is input, the distribution of the phase difference is acquired, and output as jitter distribution data of the output data of the LSI under measurement. A distribution circuit can be provided.

Further, the position data output from the time interpolator described in the first and second embodiments and the corresponding recovery clock output from the digital filter are input, and the phase difference between the edge timing indicated by the position data and the recovery clock is detected. And a jitter distribution circuit for acquiring the distribution of the phase difference and outputting it as distribution data of jitter of the clock or output data of the device under test.

That is, the clock recovery circuit constituting the semiconductor test apparatus according to the present invention acquires a recovery clock based on a time interpolator for acquiring output data of the device under test as level data in time series and the level data acquired by the time interpolator. Since it can also be combined with all the circuits, apparatuses, etc. as long as it has a digital filter which can output, the use, the objective, etc. as a semiconductor test apparatus are not specifically limited.

As described above, according to the semiconductor test apparatus of the present invention, by providing the time interpolator and the digital filter, the system clock output from the device under test is obtained, and the system clock is generated at the edge timing of the rising or falling of the system clock. It is possible to obtain a recovery clock at a higher frequency of the internal clock.

As a result, the device under test can be reliably tested at the edge timing of the system clock of the device under test and the data is output at the data rate of the internal clock that is higher than the system clock. A semiconductor test apparatus suitable for the test of the present invention can be provided.

Claims (10)

A clock output from the device under test is input, the clock is obtained by a plurality of strobes having a constant timing interval, and output as a level data of time series, and the edge of the rising edge and / or falling edge of the level data. A first time interpolator for selectively inputting level data indicating timing and outputting position data indicating edge timing of the selected level data; A second time interpolator which inputs output data output from the device under test, obtains the output data by a plurality of strobes having a constant timing interval, and outputs the output data as level data in time series; A digital filter for inputting and holding position data output from the first time interpolator, and outputting a recovery clock indicating a predetermined edge timing from one or more position data; A data selection circuit for inputting time-level level data output from the second time interpolator, selecting the level data at the edge timing of the recovery clock output from the digital filter, and outputting the data as measured data of the device under test. Semiconductor test apparatus comprising a. The method of claim 1, The first time interpolator is A plurality of parallel circuits connected in parallel for inputting a clock output from the device under test and a delay circuit for sequentially inputting strobes delayed at constant timing intervals to the plurality of circuits, and outputting time-level level data from the sequence circuit. And an edge selector for selectively outputting the level data indicating the rising edge, the level data indicating the falling edge, or the level data indicating the rising and falling edges of the time series of level data output from the plurality of sequence circuits; An encoder for inputting the selected level data, encoding and outputting the position data indicating the edge timing, Digital filter, One or more positions output from this register, including one or more registers connected in series for sequentially storing the position data output from the first time interpolator and outputting the stored position data at a predetermined timing. From the data, a recovery clock indicating a predetermined edge timing is output, The second time interpolator is A delay in which a plurality of parallel circuits connected in parallel for inputting output data output from the device under test and a strobe delayed at a constant timing interval are sequentially input to the plurality of circuits, and the level data of the time series is output from the sequence circuit. Including circuits, The data selection circuit is A semiconductor test including a selector which selects one data from the level data of time series input from a 2nd time interpolator using the recovery clock output from a digital filter as a selection signal, and outputs it as the data under test of the device under test. Device. The method of claim 2, Edge selector, A first AND circuit for inputting an inverted output of one sequence circuit and a non-inverted output of a sequence circuit of the next stage; a second AND circuit for inputting a non-inverted output of one sequence circuit and an inverted output of the sequence circuit of the next stage; And an OR circuit for inputting the outputs of the first and second AND circuits, and a semiconductor comprising one or more selector circuits including a selector for selecting any one of the outputs of the first AND circuit, the second AND circuit, and the OR circuit. tester. The method according to claim 2 or 3, Digital filter, And an edge detection circuit for detecting the presence or absence of an edge of position data input from the first time interpolator, and outputting the position data stored in a register when an edge is detected. The method of claim 4, wherein The register of the digital filter A semiconductor test apparatus that outputs stored position data at a predetermined timing regardless of whether edges of position data detected by an edge detection circuit are present. The method according to any one of claims 2 to 5, If more than one register is included, the digital filter And an average value calculating circuit for inputting position data respectively output from two or more registers, calculating an average value of edge timings indicated by each position data, and outputting the average value as a recovery clock. The method of claim 6, Digital filter, And a mean value changeover switch for selecting one of position data output from one of two or more registers and an average value output from an average value calculating circuit, and outputting the selected value as a recovery clock. The method according to any one of claims 2 to 7, Digital filter, And a timing correction circuit which adds a predetermined correction value to the position data output from the register, corrects the edge timing indicated by the position data, and outputs it as a recovery clock. The method according to any one of claims 1 to 8, And a jitter detection circuit which inputs a plurality of recovery clocks output from a digital filter, detects a phase difference of edge timing indicated by each recovery clock, and acquires jitter of a clock of a device under test. The method according to any one of claims 1 to 9, And a bus connecting the first and second time interpolators, respectively, and distributing data output from the first and second time interpolators to a predetermined data selection circuit.