KR20050079433A - Semiconductor devices having a planar metal-insulator-metal capacitor and methods of fabricating the same - Google Patents

Abstract

Provided are a semiconductor device having an MI capacitor and a method of manufacturing the same. The semiconductor device includes an interlayer insulating film formed on a semiconductor substrate and a lower wiring formed in the interlayer insulating film. The lower electrode and the dielectric layer pattern are sequentially stacked on the predetermined region of the lower wiring, and the upper electrode is stacked on the dielectric layer pattern. Sidewalls of the upper electrode and an edge of the dielectric layer pattern are covered with a spacer. The entire surface of the semiconductor substrate having the spacer and the upper electrode is covered with a capping film.

Description

Semiconductor devices having a planar metal-insulator-metal capacitor and methods of fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a flat plate type M capacitor and a method of manufacturing the same.

In order to manufacture high performance semiconductor devices, metal wiring with low electrical resistance and high reliability is required. With such metal wires, copper wires are in the spotlight as potential candidates. However, the copper wiring is difficult to form using a general photo / etch process. Accordingly, the damascene process is widely used to form the copper wiring.

On the other hand, the semiconductor devices include discrete devices such as transistors, resistors and capacitors. Each of the capacitors is composed of an upper electrode and a lower electrode superimposed on each other, and a dielectric film interposed between these electrodes. The electrodes may be formed of a doped polysilicon film. However, the polysilicon film may be further oxidized in subsequent heat treatment processes. Accordingly, electrical characteristics of the capacitor may be changed.

In addition, depending on the magnitude of the voltage applied to the polysilicon electrodes, the capacitor may exhibit non-uniform capacitance. For example, when the electrodes are formed of a polysilicon film doped with n-type impurities and a negative voltage is applied to the upper electrode, holes are induced on the surface of the lower electrode. That is, a depletion layer may be formed on the surface of the lower electrode. The width of the depletion layer varies with the magnitude of the negative voltage. As a result, the capacitance of the capacitor may vary depending on the magnitude of the voltage applied to the electrodes. In other words, capacitors employing the electrodes made of the polysilicon film may exhibit a non linear characteristic. Therefore, the capacitors having the polysilicon electrodes are unsuitable for semiconductor devices requiring sophisticated characteristics, for example, semiconductor devices having analog circuits.

Recently, in order to solve the above problems, a capacitor having metal electrodes, i.e., an MCM capacitor, has been proposed. In particular, the MMC capacitor adopts a high-k dielectric layer to obtain high capacitance.

1 and 2 are cross-sectional views for explaining a conventional method of manufacturing a MI capacitor.

Referring to FIG. 1, an interlayer insulating layer 21 is formed on a semiconductor substrate 20, and first and second copper wires 30a and 30b are formed in the interlayer insulating layer 21 by using a damascene process. do. A lower electrode layer 31, a high dielectric layer 32, and an upper electrode layer 33 are sequentially formed on the copper wires 30a and 30b and the interlayer insulating layer 21. The high-k dielectric layer 32 is formed using reaction gases mainly containing oxygen. Therefore, if the high dielectric film 32 is directly formed on the copper wirings 30a and 30b, the copper wirings 30a and 30b may be oxidized while the high dielectric film 32 is formed. The lower electrode layer 31 prevents the copper wires 30a and 30b from being oxidized while the high dielectric layer 32 is formed.

Referring to FIG. 2, the lower electrode 31a sequentially stacked on the first copper wiring 30a by successively patterning the upper electrode layer 33, the high dielectric layer 32, and the lower electrode layer 31. The high dielectric film pattern 32a and the upper electrode 33a are formed. The lower electrode film 31 and the upper electrode film 33 are generally formed of a metal film. Therefore, chlorine-based etching gas is widely used to pattern the electrode layers 31 and 33. In this case, exposed areas 34 of the copper wires 30a and 30b are damaged, so that the reliability of the copper wires 30a and 30b, for example, electro-migration (EM) characteristics. Lowers.

Furthermore, etching damage is applied to the sidewalls of the high dielectric layer pattern 32a while the high dielectric layer 32 is patterned. This etching damage provides a leakage current path between the upper electrode 33a and the lower electrode 31a. In addition, while the lower electrode layer 31 is patterned, the lower electrode layer 31 is re-sputtered so that the metallic material 35 may be deposited on the sidewall of the high-k dielectric layer pattern 32a. have. The metallic material 35 also provides a leakage current path between the upper electrode 33a and the lower electrode 31a.

As described above, according to the related art, the etching damage applied to the sidewall of the high-k dielectric layer pattern reaches from the lower electrode border to the upper electrode border. In addition, a metal material may be deposited on sidewalls of the high-k dielectric pattern while the lower electrode layer is patterned. Accordingly, leakage current characteristics between the lower electrode and the upper electrode may be significantly reduced.

The technical problem to be solved by the present invention is to solve the problem of leakage current and deterioration of the electro-migration (EM) characteristics and flat plate-type metal-insulator between the damascene wiring to minimize the electrode resistance problem To provide a semiconductor device having a metal (MIM) capacitor and a method of manufacturing the same.

Embodiments of the present invention provide a semiconductor device having a flat metal-insulator-metal (MIM) capacitor. The device includes an interlayer insulating film formed on a semiconductor substrate and a lower wiring formed in the interlayer insulating film. The lower electrode and the dielectric film pattern are sequentially stacked on the predetermined area of the lower wiring. An upper electrode is provided on the dielectric layer pattern, and sidewalls of the upper electrode and an edge of the dielectric layer pattern are covered with a spacer. The entire surface of the semiconductor substrate having the spacer and the upper electrode is covered with a capping film.

Another embodiment of the present invention provides a method of manufacturing a semiconductor device having a flat metal-insulator-metal (MIM) capacitor. The method includes forming an interlayer insulating film on a semiconductor substrate and forming lower wirings using a damascene technique in the interlayer insulating film. A lower electrode film, a dielectric film, and an upper electrode film are sequentially formed on the lower wiring and the interlayer insulating film. The upper electrode layer is patterned to form an upper electrode on a predetermined region of the lower wiring, and a spacer is formed on sidewalls of the upper electrode. The dielectric layer and the lower electrode layer are etched using the upper electrode and the spacer as etching masks to form a lower electrode and a dielectric layer pattern. A capping film is formed on the entire surface of the semiconductor substrate having the lower electrode and the dielectric film pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Portions denoted by like reference numerals denote like elements throughout the specification.

3A through 3F are cross-sectional views illustrating semiconductor devices having MCM capacitors and fabricating methods thereof according to embodiments of the present invention.

First, with reference to FIG. 3F, semiconductor devices having MI capacitors according to embodiments of the present invention will be described.

Referring to FIG. 3F, an interlayer insulating layer 39 is stacked on the semiconductor substrate 38, and first and second lower interconnections 40a and 40b are formed in the interlayer insulating layer 39 by a damascene process. do. Each of the lower interconnections 40a and 40b may include a lower metal interconnection and a barrier metal layer pattern surrounding lower surfaces and sidewalls of the lower metal interconnection. The barrier metal layer pattern may be at least one of a tantalum nitride layer (TaN), a titanium nitride layer (TiN), a titanium layer, a tantalum layer, a tungsten nitride layer (WN), and a ruthenium layer (Ru). It may be a material film of any one of a copper film, an aluminum film, an aluminum-copper film, and a tungsten film.

Upper surfaces of the lower interconnections 40a and 40b may be covered with first and second buffer metals 42a and 42b, respectively. The first and second buffer conductive films 42a and 42b are preferably conductive films having a strong resistance to process gases, such as chlorine gas, for etching the metal film. For example, the buffer conductive layers 42a and 42b may be a tungsten film or a CoWP (Cobalt, Tungsten, Phosphorous) film.

The lower electrode 51a and the dielectric film pattern 52a are sequentially stacked on the predetermined region of the first buffer conductive film 42a. The lower electrode 51a may be a pure metal nitride film or a ternary metal nitride film containing aluminum or silicon. Specifically, the pure metal nitride layer may be a titanium nitride layer, a tantalum nitride layer, or a tungsten nitride layer, and the ternary metal nitride layer may be a tantalum silicon nitride layer (TaSiN) or a tantalum aluminum nitride layer (TaAlN). In addition, the lower electrode 51a may further include a noble metal layer stacked on the pure metal nitride film or the ternary metal nitride film. The precious metal film may be a ruthenium film, a platinum film or an iridium film. The noble metal film serves as an oxygen diffusion preventing film to prevent the first lower interconnection 40a from being oxidized in a subsequent process.

The dielectric layer pattern 52a may be formed of an aluminum oxide layer (AlO), a hafnium oxide layer (HfO), a tantalum oxide layer (TaO), a lanthanum oxide layer (LaO), an esteri layer (ST), a non-ESTI layer (BST), or a PZT layer. , A metal oxide film such as an SBT film, a zirconium oxide film (ZrO), or a high dielectric film such as a nitride film thereof.

An upper electrode 53a is stacked on a portion of the dielectric film pattern 52a. The upper electrode 53a may be a pure metal nitride film or a ternary metal nitride film containing aluminum or silicon, like the lower electrode 51a. In addition, the upper electrode 53a may further include a noble metal layer disposed under the pure metal nitride film or the ternary metal nitride film. The noble metal layer may be a ruthenium layer Ru, a platinum layer Pt, or an iridium layer Ir, and may improve interface characteristics between the dielectric layer pattern 52a and the upper electrode 53a.

A hard mask pattern 54a may be further stacked on the upper electrode 53a. The hard mask pattern 54a may be a material film having an etch selectivity with respect to the dielectric film pattern 52a and the lower electrode 51a. For example, the hard mask pattern 54a may be an insulating film such as silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (AlO), or aluminum oxynitride (AlON). When the upper electrode 53a is a conductive film having a high etching selectivity with respect to the dielectric layer pattern 52a and the lower electrode 51a, the hard mask pattern 54a may not be stacked.

Sidewalls of the upper electrode 53a and exposed edge upper surfaces of the dielectric film pattern 52a are covered with a spacer 55. In addition, the outer wall of the spacer 55 is self-aligned to the sidewalls of the dielectric film pattern 52a. That is, the spacer 55 is positioned on the exposed edge of the dielectric film pattern 52a. As a result, the width of the upper electrode 53a is smaller than the width of the dielectric film pattern 52a. The spacer 55 may be an insulating layer, such as a silicon nitride layer (SiN), a silicon oxynitride layer (SiON), an aluminum oxide layer (AlO), or an aluminum oxynitride layer (AlON). When the hard mask pattern 54a is stacked on the upper electrode 53a, the spacer 55 covers sidewalls of the hard mask pattern 54a together with sidewalls of the upper electrode 53a. Can be extended.

The entire surface of the semiconductor substrate including the spacer 55, the upper electrode 53a, and the hard mask pattern 54a is covered with a capping layer 60. The capping layer 60 may be a silicon nitride layer (SiN) or a double insulating layer of a silicon nitride layer (SiN) and an aluminum oxide layer (AlO).

The capping layer 60, the hard mask pattern 54a, and the spacer 55 may be formed by a capacitor in a hydrogen damage-dielectric layer in a hydrogen-containing process (eg, PECVD-SiN process). It also plays a role in preventing the reduction phenomenon).

A metal interlayer insulating film 70 is stacked on the capping film 60. The metal interlayer insulating film 70 is preferably a low dielectric film such as a silicon oxide film (SiO 2). In this case, the capping layer 60 prevents the copper atoms in the first and second lower interconnections 40a and 40b, that is, the copper interconnections from being diffused into the interlayer insulating layer 70. In addition, the interlayer dielectric layer 70 may be a planarized interlayer dielectric layer having a flat upper surface. A chemical mechanical polishing stoppage layer 80 may be further stacked on the interlayer dielectric layer 70. The chemical mechanical polishing stopper film 80 may be a silicon nitride film.

The upper electrode 53a may include a plurality of first via contact plugs 65a penetrating through the chemical mechanical polishing barrier layer 80, the interlayer dielectric layer 70, the capping layer 60, and the hard mask pattern 54a. Is electrically connected to the. In addition, the first buffer conductive layer 42a may be electrically connected to the second via contact plug 65b passing through the chemical mechanical polishing barrier layer 80, the metal interlayer insulating layer 70, and the capping layer 60. Can be. Similarly, the second buffer conductive layer 42b is formed on the third via contact plug 65c penetrating through the chemical mechanical polishing barrier layer 80, the interlayer dielectric layer 70, and the capping layer 60. Can be electrically connected. When the first and second buffer conductive layers 42a and 42b are not provided, the second and third via contact plugs 65b and 65c may respectively be the first and second lower interconnections 40a. , 40b) directly.

Preferably, the first via contact plugs 65a are at least two. This is to minimize the contact resistance between the upper electrode 53a and the first via contact plugs 65a. Each of the via contact plugs 65a, 65b, 65c may be a metal plug such as a copper plug, an aluminum plug, an aluminum-copper plug or a tungsten plug. In addition, each of the via contact plugs 65a, 65b, and 65c may further include a barrier metal film pattern surrounding sidewalls and a bottom surface of the metal plug.

First to third upper metal wires 90a, 90b, and 90c are provided on the chemical mechanical polishing stopper film 80. The first to third upper metal wires 90a, 90b, and 90c are disposed to cover the first to third via contact plugs 65a, 65b, and 65c, respectively. The first to third upper metal wires 90a, 90b, and 90c may be a material film of any one of a copper film, an aluminum film, an aluminum-copper film, and a tungsten film. In addition, each of the first to third upper metal wires 90a, 90b, and 90c may further include a barrier metal film pattern surrounding lower surfaces and sidewalls of the upper metal wires.

3A to 3F, methods of fabricating semiconductor devices having MI capacitors according to example embodiments will be described.

Referring to FIG. 3A, an interlayer insulating film 39 is formed on the semiconductor substrate 38. First and second lower interconnections 40a and 40b are formed in the interlayer insulating layer 39 using a damascene technique. The lower interconnections 40a and 40b may be formed of a metal film such as a copper film, an aluminum film, an aluminum copper film, or a tungsten film. In addition, the lower interconnections 40a and 40b may be formed to have lower barrier metal layers and metal layers sequentially stacked. The barrier metal film may be formed of at least one material film of a tantalum nitride film, a titanium nitride film, a titanium film, a tantalum film, a tungsten nitride film, and a ruthenium film. The lower electrode layer 51, the dielectric layer 52, and the upper electrode layer 53 are sequentially formed on the lower interconnections 40a and 40b and the interlayer insulating layer 39. Before the lower electrode layer 51 is formed, first and second buffer conductive layers 42a and 42b may be selectively formed on the first and second lower interconnections 40a and 40b, respectively. . Forming the buffer conductive layers 42a and 42b may include selectively forming a tungsten layer on the lower interconnections 40a and 40b using a selective CVD process. In contrast, forming the buffer conductive layers 42a and 42b may be performed by using an electroless plating method to selectively form a cobalt tungsten phosphorous (CoWP) layer on the lower interconnections 42a and 42b. It may include.

A hard mask layer 54 may be further formed on the upper electrode layer 53. The hard mask layer 53 may be formed of a material layer having an etch selectivity with respect to the dielectric layer 52 and the lower electrode layer 51. For example, the hard mask layer 54 may be formed of an insulating layer, such as a silicon nitride layer (SiN), a silicon oxynitride layer (SiON), an aluminum oxide layer (AlO), or an aluminum oxynitride layer (AlON). When the upper electrode film 53 is a conductive film having a high etching selectivity with respect to the dielectric film 52 and the lower electrode film 51, the formation of the hard mask film 54 may be omitted. .

Referring to FIG. 3B, the upper electrode layer 53 and the hard mask layer 54 are patterned to form an upper electrode 53a and a hard mask pattern 54a on a predetermined region of the lower interconnection 40a. .

Referring to FIG. 3C, spacers 55 are formed on sidewalls of the upper electrode 53a and the hard mask pattern 54a. The spacer 55 may be formed of a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film. When the process of forming the hard mask layer 54 is omitted in FIG. 3A, the spacer 55 is formed on sidewalls of the upper electrode 53a.

Referring to FIG. 3D, the dielectric layer 52 and the lower electrode layer 51 are etched using the hard mask pattern 54a and the spacer 55 as etch masks, thereby lowering the lower electrode 51a and the dielectric. The film pattern 52a is formed. In this case, an etch damage may be applied to the sidewall of the dielectric film pattern 52a. These etched sidewalls can act as a path for leakage current. However, in the present embodiment, the etched sidewalls of the dielectric film pattern 52a are formed to be spaced apart from the sidewall of the upper electrode 53a by the spacer 55 as shown in FIG. 3D. Accordingly, it is possible to prevent the direct leakage current path between the upper electrode 53a and the lower electrode 51a from being formed.

When the lower electrode 51a is formed, the chlorine group is etched until the end point is detected, and then the overetch is chlorine of metal-organic series. It is preferable to etch using chlorine etchant. Each of the dielectric film 52, the spacer 55, and the hard mask film 54 preferably proceeds with an etching gas containing fluorine or chlorine when etching.

Referring to FIG. 3E, a capping layer 60 is formed on the entire surface of the semiconductor substrate having the lower electrode 51a, the dielectric layer pattern 52a, and the spacer 55. The capping layer 60 may be formed of a silicon nitride layer (SiN) or a double insulating layer of a silicon nitride layer (SiN) and an aluminum oxide layer (AlO). The capping layer 60, the hard mask pattern 54a, and the spacer 55 may have a capacitor formed by hydrogen during a subsequent process using a process gas containing hydrogen (eg, a PECVD-SiN process). It acts as a hydrogen barrier that protects against hydrogen damage.

Referring to FIG. 3F, a metal interlayer insulating film 70 is formed on the capping film 60. The capping layer 60 serves as a barrier layer that prevents metal atoms, particularly copper atoms, from being diffused into the interlayer dielectric layer 70. A chemical mechanical polishing (CMP) blocking film 80 may be further formed on the interlayer insulating film 70. A plurality of first via contact plugs 65a penetrating through the chemical mechanical polishing barrier layer 80, the metal interlayer dielectric layer 70, the capping layer 60, and the hard mask pattern 54a on the upper electrode 53a. To form. In addition, a second via contact plug 65b may be formed on the first buffer conductive layer 42a through the chemical mechanical polishing barrier layer 80, the metal interlayer insulating layer 70, and the capping layer 60. Similarly, a third via contact plug 65c is formed on the second buffer conductive layer 42b through the chemical mechanical polishing barrier layer 80, the metal interlayer insulating layer 70, and the capping layer 60. . When the first and second buffer conductive layers 42a and 42b are not provided, the second and third via contact plugs 65b and 65c may respectively be the first and second lower interconnections 40a. , 40b). First to third upper metal wires 90a, 90b, and 90c are formed on the chemical mechanical polishing barrier layer 80. The first to third upper metal wires 90a, 90b, and 90c are formed to cover the first to third via contact plugs 65a, 65b, and 65c, respectively.

According to the present invention as described above, since the dielectric film is formed on the lower electrode film covering the lower wiring, it is possible to prevent the lower wiring from being oxidized even if a process gas containing oxygen is used during the formation of the dielectric film. In addition, since the etched sidewalls of the dielectric layer are formed to be spaced apart from the sidewalls of the upper electrode, leakage current characteristics between the upper electrode and the lower electrode can be significantly improved. In addition, a capping film is formed between the lower wirings and the interlayer insulating film. The capping layer may prevent diffusion of metal atoms, for example, copper atoms, in the lower interconnections into the interlayer insulating layer. Therefore, it is possible to prevent the deterioration of the characteristics of the interlayer insulating film.

1 and 2 are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device having an M capacitor.

3A through 3F are cross-sectional views illustrating semiconductor devices having MCM capacitors and fabricating methods thereof according to embodiments of the present invention.

Claims (14)

An interlayer insulating film formed on the semiconductor substrate; A lower wiring formed in the interlayer insulating film; A lower electrode and a dielectric layer pattern sequentially stacked on a predetermined region of the lower wiring; An upper electrode stacked on the dielectric layer pattern; A spacer covering sidewalls of the upper electrode and an edge of the dielectric layer pattern; And And a capping layer covering an entire surface of the semiconductor substrate having the spacer and the upper electrode. The method of claim 1, And a buffer conductive layer interposed between the lower wiring and the lower electrode and extending to cover the entire upper surface of the lower wiring. The method of claim 1, And a hard mask pattern interposed between the upper electrode and the capping layer, wherein the spacer covers sidewalls of the hard mask pattern together with sidewalls of the upper electrode. The method of claim 1, A metal interlayer insulating film stacked on the capping film; And And an upper wiring disposed on the interlayer insulating film and electrically connected to the upper electrode. The method of claim 4, wherein And the upper wiring is electrically connected to the upper electrode through a plurality of via contact plugs penetrating through the interlayer insulating layer and the capping layer. An interlayer insulating film is formed on the semiconductor substrate, Forming a lower wiring in the interlayer insulating film using a damascene technique; A lower electrode film, a dielectric film, and an upper electrode film are sequentially formed on the lower wiring and the interlayer insulating film; Patterning the upper electrode layer to form an upper electrode on a predetermined region of the lower wiring, Forming a spacer on sidewalls of the upper electrode, Etching the dielectric film and the lower electrode film using the upper electrode and the spacer as etching masks to form a lower electrode and a dielectric film pattern; And forming a capping film on the entire surface of the semiconductor substrate having the lower electrode and the dielectric film pattern. The method of claim 6, And forming a buffer conductive film selectively on the lower wiring before forming the lower electrode film. The method of claim 7, wherein The buffer conductive film selectively forms tungsten on the lower wiring by chemical vapor deposition (CVD), or CoWP (Cobalt, Tungsten, Phosphorous) on the lower wiring by electroless plating. Forming a semiconductor device, characterized in that formed. The method of claim 6, And forming a hard mask pattern interposed between the upper electrode and the capping layer, wherein the spacer is formed to cover sidewalls of the hard mask pattern together with sidewalls of the upper electrode. Manufacturing method. The method of claim 6, A metal interlayer insulating film is formed on the capping film; The method may further include forming an upper wiring on the interlayer insulating film. And the upper metal wiring is electrically connected to the upper electrode. The method of claim 10, And the upper metal wiring is electrically connected to the upper electrode through a plurality of via contact plugs penetrating through the interlayer insulating film and the capping film. The method of claim 6, The dielectric film may be formed of an aluminum oxide film, a hafnium oxide film, a tantalum oxide film, a lanthanum oxide film, an Estee film (ST), a BEST film (BST), a PZT film, an SBT film, a zirconium oxide film, or a nitride film thereof. A method of manufacturing a semiconductor device, characterized in that. The method of claim 6, And the capping film is formed of a silicon nitride film or a double insulating film of a silicon nitride film and an aluminum oxide film. The method of claim 6, The spacer is formed using a silicon nitride film, a silicon oxynitride film, an aluminum oxide film or an aluminum oxynitride film.