KR20050076527A - Interface apparatus using multi-input/output apparatus - Google Patents

Abstract

The present invention relates to a technology in which a device having a parallel or serial input / output device interfaces through multiple input / output devices. The present invention comprises a central processing unit (1A), I2C (1B), UART (1C) which is an external device having a different operation speed, data transmission width and data transmission method; Various types of device protocols 2A-2C for allowing the external devices 1A-1C to exchange data with each other; A register interface (3) which allows the device protocols (2A-2C) to be connected directly or via a FIFO (6); A register file section 4, which is a collection module of registers having a data transfer width of 8 bits; A FIFO control unit 5 which collects four 8-bit data and controls data transmission / reception with a 32-bit external device; A FIFO 6 for ensuring smooth data transmission and reception of the high speed device and the low speed device; A device protocol (7) for transmitting and receiving data between the FIFO control unit (5) and the memory (9); It operates at high speed at 120 MHz and has a data bus width of 32 bits, achieved by a memory 9 shared and used by several blocks.

Description

Interface device using multiple input / output devices {INTERFACE APPARATUS USING MULTI-INPUT / OUTPUT APPARATUS}

The present invention relates to a technology in which a device having a parallel or serial input / output device interfaces through multiple input / output devices, and particularly includes a register and a first-in first-out (FIFO) device when the operation speed and data transmission width between the devices are different. The present invention relates to an interface device using multiple input / output devices for smoothly interfacing with multiple input / output devices.

In general, when several types of devices interface with each other, each time a new device is added, each device must be provided with an interface circuit in order to transmit data to all existing devices.

With this background, it is possible to add peripheral devices in a simple manner, and there is a demand for a configuration that can compensate for differences in operation speed and data transmission width.

As described above, in the conventional data interface device, when several types of devices interface with each other, each device must be provided with an interface circuit in order to transmit data to all existing devices. Therefore, there was a problem in that hardware costs are added accordingly.

Accordingly, a first object of the present invention is to efficiently interface a circuit having several parallel and serial input / output devices.

A second object of the present invention is to interface more smoothly when interfacing data between devices having different data transmission bus widths.

A third object of the present invention is to interface more smoothly when interfacing data between devices having different operating clock frequencies.

A fourth object of the present invention is to use a FIFO structure to allow a high speed device to smoothly transmit data without falling into the standby mode when the low speed device and the high speed device communicate.

1 is a block diagram showing an embodiment of an interface device using multiple input / output devices according to the present invention. As shown in FIG. 1, a parallel input / output device having an 8-bit data bus width is operated in synchronization with a clock frequency of 24 MHz. A central processing unit 1A; A serial I / O device conforming to I2C communication protocol, comprising: I2C (1B) operating in 100-400 Kbps mode; A serial communication apparatus, comprising: a universal asynchronous receiver (UART) 1C operating at 9600 bps; As a block conforming to the transmission / reception protocol of each of the external devices 1A-1C, various types of device protocols that allow the register interface 3 and the external devices 1A-1C to exchange data with each other ( Device protocol) 2A-2C; A register interface (3) for allowing the various types of device protocols (2A-2C) to be connected directly or through a FIFO (6); A register file section 4, which is a collection module of registers having an 8-bit data transfer width; A FIFO control unit 5 which collects four 8-bit data and controls data transmission / reception with a 32-bit external device; Fist-In First-Out circuit is used to ensure smooth data transmission and reception of high speed devices and low speed devices, and is internally separated into address FIFO and data FIFO (FIFO: Fist-In First-Out). 6); A device protocol (7) for transmitting and receiving data between the FIFO control unit (5) and the memory (9); A register association section (8) corresponding to other block sections for viewing a value written in a register from each external device (1A-1C) and performing a specific operation or appropriately changing the values of the registers; A high speed operation at 120 MHz and a 32-bit data bus width, which are configured as a memory 9 shared and used by various blocks, will be described in detail with reference to FIG. 2 attached to the operation of the present invention. As follows.

An external device having a specific data bus width and operation speed and having a different data transmission method (serial / parallel transmission method), for example, the central processing unit 1A, I2C 1B and UART 1C are multiple input / output devices. Through the register file unit 4 and the FIFO 6 of 10 can be efficiently interfaced. First, the operation of each part of FIG.

First, the central processing unit 1A among the external devices is a parallel input and output device having an 8-bit input and an output, and operates in synchronization with a clock frequency of 24 MHz. In addition, the I2C (1B) is a serial input and output device conforming to the I2C communication protocol, and operates in the 100-400Kbps mode. In addition, the UART 1C is a serial communication device and operates at 9600 bps. The memory 9 operates at high speed in synchronization with a clock frequency of 120 MHz, has a data bus width of 32 bits, and is shared and used by several blocks.

Other external devices can be added at any time, and the number of bits of transmission data can be freely changed.

Each of the external devices 1A, 1B, and 1C is connected directly through the register interface 3 in the multiple input / output device 10 after the respective device protocols 2A, 2B, and 2C. Or through a FIFO (6), wherein the register interface (3) writes and reads data values of the external devices (1A), (1B), and (1C) to the register file section 4, which is a lower block. do.

The register file section 4 is a set of registers having an 8-bit data transfer width, and the data transfer width thereof can be changed according to a system.

The device protocols 2A-2C are blocks that conform to the transmission / reception protocols of the external devices 1A, 1B, and 1C, respectively, and the register interface 3 and its external devices 1A, 1B. , (1C) allows each other to send and receive data.

The 8-bit register value is not suitable for sending and receiving data with an external device having a data transfer width of 32 bits. In order to solve this problem, the FIFO control unit 5 collects four 8-bit data to control transmission and reception of data with a 32-bit external device. At this time, the number of data bits can be changed, and the FIFO control unit 5 collects data to be written or read, and performs control for reading and writing to a fast device at once.

The FIFO 6 is a first-in, first-out circuit used to ensure smooth data transmission and reception of the high speed device and the low speed device, which are internally separated into an address FIFO and a data FIFO.

The register association section 8 reads the values written in the register file section 4 from the external devices 1A, 1B, and 1C and performs a specific operation or appropriately changes the values of the registers. Perform.

The external devices 1A, 1B, and 1C, which are completely different from the input / output method, operation speed, data transmission width, and the like, are connected together through the multiple input / output device 10 and the memory 9 to give data to each other. Receive. To this end, each of the external devices 1A, 1B, and 1C transmits and receives data by writing and reading a specific value into an address register and a data register in the register file unit 4.

The fast operating memory 9 can be shared and used by several blocks. In this case, when the operating speed of the memory 9 is faster than that of other peripheral devices, a phenomenon in which the high speed memory 9 is monopolized by a slow device for a long time may occur. However, this can be prevented by using a multi-level FIFO 6 inside.

FIG. 2 shows a processing procedure in the case of writing data to the FIFO 6 through the register file section 4. Here, each register of the register file section 4 uses an 8-bit data bus. In addition, the memory 9 transmits and receives 32 bits of data at an address of 16 bits.

The operation sequence for writing data from the external device 1A, 1B, or 1C having a slow operation speed to the memory 9 having a high operation speed is as follows.

Any external device among the external devices 1A, 1B, and 1C attempts to access two address registers ADDR_HI_REG and ADDR_LO_REG that contain high-order byte information of the 16-bit address in the register file unit 4. The address of the memory 9 to be written is written.

Subsequently, the most significant 8 bits of data to be transferred are written into the data register DATA_REG. The first 8-bit data to be written first is moved to the left area of the data buffer 6B at the moment of receiving a control signal from the register interface 3 indicating that the data has been written. Subsequently, the second data written in the data register DATA_REG is moved to the middle area of the data buffer 6B. Subsequently, the third data written in the data register DATA_REG is moved to the right area of the data buffer 6B. Finally, fourth data is written to the data register DATA_REG.

When 32 bits of data are written in this way, the 27-bit data transferred to the data buffer 6B and the fourth 8-bit data recorded in the data register DATA_REG are simultaneously the first area FIFO of the data FIFO 6C. It is moved to the corresponding position in 0). At the same time, the addresses recorded in the address registers ADDR_HI_REG and ADDR_LO_REG are moved to the first area FIFO 0 of the address FIFO 6A.

If the FIFO 6 is not used, the values are not stored in the FIFO 6 but are transferred directly to the memory 9.

The values recorded in the address FIFO 6A and the data FIFO 6C are transferred to the memory 9 under the control of the FIFO control section 5.

By the way, when the third device is in use and the value cannot be written in the memory 9, the value is recorded in the FIFO 6 one after another. After that, when a value can be written in the memory 9, the values recorded in the FIFO 6 are transferred to the memory 9 at once.

The FIFO 6 used for writing when the external device having a slower operating speed among the external devices 1A, 1B, and 1C reads a value from the memory 9 having the faster operating speed. Is used for read this time.

In general, the FIFO 6 is often not used during the read operation of the memory 9. The following shows a process of reading a value from the memory 9 without going through the FIFO 6 as described above.

Of the 32-bit data corresponding to an address generated by any external device among the external devices 1A, 1B, and 1C, 31 to 24 bits are in the data register DATA_REG, and 23 to 0 bits are the data buffer 6B. Move on.

Each time a byte is read, the data stored in the data buffer 6B is moved to the data register DATA_REG in the order of 23 to 16 bits, 15 to 8 bits, and 7 to 0 bits so that the external device can read it.

For reference, the width of the address bus and data bus in the above description may be adjusted to interface with various types of external devices.

As described in detail above, when the devices having serial and parallel interfaces have different data transmission bus widths and operating frequencies, the present invention can efficiently interface with multiple input / output devices and memories.

In addition, since the FIFO structure is provided in the multi-input / output device, the data can be smoothly transmitted between the low speed device and the high speed device having different data transfer bus widths and operating speeds.

1 is a block diagram of an interface device using multiple input / output devices according to the present invention.

2 is a detailed block diagram of the FIFO in FIG.

*** Description of the symbols for the main parts of the drawings ***

1A: Central Processing Unit 1B: I2C

1C: UART 2A-2C, 7: Device Protocol

3: register interface 4: register file section

5: FIFO control unit 6: FIFO

7: Device Protocol 8: Register Related Section

9: memory

Claims (4)

A central processing unit (1A), I2C (1B), and UART (1C), which are external devices having different operating speeds, data transmission widths, and data transmission methods; Various types of device protocols 2A-2C for allowing the external devices 1A-1C to exchange data with each other; A register interface (3) which allows the device protocols (2A-2C) to be connected directly or via a FIFO (6); A register file section 4, which is a collection module of registers having a data transfer width of 8 bits; A FIFO control unit 5 which collects four 8-bit data and controls data transmission / reception with a 32-bit external device; A FIFO 6 for ensuring smooth data transmission and reception of the high speed device and the low speed device; A device protocol (7) for transmitting and receiving data between the FIFO control unit (5) and the memory (9); An interface device using multiple input / output devices, characterized by high-speed operation at 120 MHz and a data bus width of 32 bits, comprising memory (9) shared and used by multiple blocks. 2. The CPU 1A is a parallel input and output device having an 8-bit input and output, and operates in synchronization with a clock frequency of 24 MHz. The I2C (1B) is a serial input and output that conforms to the I2C communication protocol. The device operates in 100-400 Kbps mode, the UART (1C) is an interface device using a multiple input and output devices, characterized in that operating at 9600 bps as a serial communication device. 2. The register file unit (4) according to claim 1, further comprising: two address registers (ADDR_HI_REG) and (ADDR_LO_REG) for address transmission in units of 8 bits; Interface device using multiple input and output devices characterized by including a data register (DATA_REG) for data transmission in 8-bit units. 2. The apparatus according to claim 1, wherein the FIFO (6) comprises: an address FIFO (6A) for recording, on a first-in, first-out basis, 16-bit addresses transmitted simultaneously in the 8-bit separated form in the register file section 4; A multi-input / output device comprising: an address data buffer 6B and a data FIFO 6C for simultaneously writing, in a first-in-first-out manner, 32 bits of data transmitted four times by eight bits in the register file unit 4; Interface device used.