KR20050031626A - Apparatus and method for driving flat panel display - Google Patents

Abstract

A driving apparatus and a driving method of a flat panel display are provided to attenuate electromagnetic interference generated from a signal transmission process by using selectively a spread spectrum function of a flat display device according to presence of a spread spectrum function. A flat panel includes a cell matrix composed of cells, which are formed in each region defined by intersections between scan lines and data lines. A graphic card(148) generates image data, clock signals, and synchronous signals to display images onto the flat panel. A first spread spectrum circuit(144) modulates a frequency of a clock signal to a first clock signal. A transmission part synchronizes one signal of the clock signal and the first clock signal with the image data and the synchronous signals and transmits the synchronized signal through an interface line. A selection circuit outputs selectively the clock signal and the first clock signal according to a driving state of the first spread spectrum circuit(144). A second spread spectrum circuit(110) modulates the frequency of the clock signal outputted from the selection circuit to a second clock signal. A timing control part(108) generates a control signal for displaying an image signal onto the flat panel by using one of the first clock signal and the second clock signal.

Description

Driving apparatus and driving method of flat panel display device {APPARATUS AND METHOD FOR DRIVING FLAT PANEL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device and a method of a flat panel display, and more particularly, to a flat panel display that minimizes electromagnetic interference (EMI) and prevents screen noise by selectively using a spread spectrum function of the flat panel display. It relates to a drive device and a method of the.

Recently, various flat panel displays (hereinafter referred to as "FPDs") that can reduce weight and volume, which are disadvantages of cathode ray tubes, have been developed. The FPD includes a liquid crystal display, a field emission display, a plasma display panel, an electro-luminescence display, and the like.

The FPD generally consists of a flat panel in which cells are arranged in a matrix between two glass substrates, a printed circuit board module for driving the flat panel, and a case for protecting and integrating them. Since the liquid crystal display is not self-luminous, it requires a separate light source such as a backlight unit. Here, the printed circuit board module receives the red, green and blue image data and the synchronization signal from the outside, and supplies the image data, the scanning signal, and the timing control signals to the flat panel so that the computer, television image, It corresponds to a driving circuit for displaying other application images.

Referring to FIG. 1, a conventional FPD driving apparatus includes a flat panel 2 having a cell matrix, a scan driver 4 for driving scan lines of the flat panel 2, and data of the flat panel 2. A data driver 6 for driving the lines, a timing controller 8 for controlling the driving timing of the scan driver 4 and the data driver 6, and a printed circuit board 20 mounted with the timing controller 8; FPD (100) including; A drive system 40 including a graphics card 48 for generating an analog graphics signal, and a transmission interface section 42 for supplying the timing controller 8 of the FPD 100 from the graphics card 48; And an interface line 50 for signal transmission between the FPD 100 and the drive system 40.

The transmission interface unit 42 of the drive system 40 converts the analog graphic signal generated from the graphic card 48 to match the characteristics of the flat panel 2 and supplies it to the FPD 100 via the same. At this time, the transmission interface unit 42 is a large screen of the flat panel 2, and as the data processing speed increases as the resolution becomes higher, such as UXGA (1200 * 1600), QXGA (2048 * 1600), QSXGA (2560 * 2048), etc. DCLK (hereinafter referred to as "SDCLK") is frequency spread within a specific frequency range according to a spread spectrum method in order to reduce electromagnetic interference (hereinafter referred to as "EMI") in which harmonic components different from signals are generated. And converts the analog graphic signal generated from the graphics card 48 into the FPD 100 to match the characteristics of the flat panel 2 and supplies it to the FPD 100 through the interface line 50. .

To this end, the drive system 40 includes a first spread spectrum integrated circuit (“SS IC”) 44 for frequency spreading of the dot clock DCLK supplied from the graphics card 48. It is further provided. As shown in FIG. 2, the first SS IC 44 pulse-width modulates the frequency of the dot clock DCLK and outputs it to another phase SDCLK. Here, the first SS IC 44 is a commercially available integrated circuit that modulates a phase of a digital pulse signal by a phase locked loop. The first SS IC 44 widens the frequency band of the dot clock DCLK supplied from the graphics card 48 to the transmission interface unit 42 and distributes the frequencies so that energy is concentrated in a specific frequency band, thereby reducing the EMI reference value. It serves to prevent the phenomenon of excess.

The flat panel 2 of the FPD 10 has a cell matrix composed of cells formed at each region defined by the intersection of scan lines and data lines. The flat panel 2 may be any one of a liquid crystal panel, a plasma display panel, an electroluminescence panel, and a field emission display panel.

The scan driver 4 drives the scan lines of the flat panel 2 in response to the scan control signal SCS supplied from the timing controller 8.

The data driver 6 supplies the pixel data RGB supplied from the timing controller 8 to the data lines based on the data control signal DCS supplied from the timing controller 8.

On the printed circuit board 20, a Data Enable (hereinafter referred to as "DE") signal indicating a valid data section supplied in synchronization with the SDCLK from the transmission interface unit 44 of the drive system 40, horizontally. Receives a synchronization signal (hereinafter referred to as "Hsync"), a vertical synchronization signal (hereinafter referred to as "Vsync"), and a dot clock DCLK that determines the transmission timing of the pixel data RGB to the timing controller 8. A receiving interface unit 12 for supplying; A second SS IC 10 is mounted to prevent a phenomenon in which energy is concentrated in a specific frequency band and exceeds an EMI reference value by widening the frequency band of the dot clock DCLK supplied from the receiving interface unit 12 to distribute the frequencies. do.

As illustrated in FIG. 2, the second SS IC 10 pulse-width modulates the frequency of the dot clock DCLK supplied from the receiving interface unit 12 and outputs the pulses in another phase SDCLK. Here, the second SS IC 10 is a commercially available integrated circuit that modulates a phase of a digital pulse signal by a phase locked loop. The second SS IC 10 widens the frequency band of the dot clock DCLK input from the reception interface unit 12 to the timing controller 8 to distribute the frequency to supply the timing controller 8.

The timing controller 8 generates the data control signal DCS and the scan control signal SCS using the SDCLK supplied from the second SS IC 10. Accordingly, the frequencies of the control signals DCS and SCS generated by the timing controller 8 are not kept constant, but have a form of shaking within a specific frequency range along the SDCLK. EMI between the control signals is canceled to reduce the effect.

However, in the conventional drive and method of the flat panel display, the FPD is generated because the drive system 40 and the timing controller 8 generate various signals along the SDCLK from the first and second SS ICs 44 and 10, respectively. In some cases, driving timings between control signals for driving the 100 do not match. Accordingly, there is a problem that screen noise occurs on the flat panel 2.

Accordingly, an object of the present invention is to provide an apparatus and method for driving a flat panel display device, which minimizes electromagnetic interference (EMI) and prevents screen noise by selectively using a spread spectrum function of the flat panel display device. .

In order to achieve the above object, a driving apparatus of a flat panel display according to an exemplary embodiment of the present invention includes a flat panel including a cell matrix formed of cells formed at regions defined by intersections of scan lines and data lines, and a flat panel on the flat panel. A graphics card for generating image data and a clock signal and a synchronization signal for displaying an image, a first spread spectrum circuit for modulating a frequency of the clock signal into a first clock signal, and among the clock signal and the first clock signal A transmission unit for synchronizing the image data and the synchronization signals to any one signal and transmitting the same through an interface line, and a selection circuit for selectively outputting the clock signal and the first clock signal according to whether the first spread spectrum circuit is driven or not; Changing the frequency of the clock signal output from the selection circuit into a second clock signal; A control for displaying the video signal on the flat panel using any one of a second spread spectrum circuit, a first clock signal output from the selection circuit and a second clock signal output from the second spread spectrum circuit And a timing controller for generating and supplying signals.

In the driving apparatus, the interface lines may include an on / off signal line for transmitting an on / off signal corresponding to whether the first spread spectrum circuit is driven.

In the driving device, the on / off signal is connected to a first voltage source when the first spread spectrum circuit is driven, and becomes a first logic state. When the first spread spectrum circuit is not driven, the on / off signal is applied to a second voltage source. And a second logic state different from the first logic state.

In the driving apparatus, the selection circuit includes an input terminal to which one of the clock signal and the modulated clock signal are supplied, a first output terminal connected to an input terminal of the second spread spectrum circuit, and the second spread spectrum circuit. And a control terminal for selectively switching the clock signal supplied to the input terminal to the first and second output terminals in accordance with the on / off signal. It features.

In the driving device, when the on / off signal of the first logic state is supplied to its control terminal, the selection circuit switches the modulated clock signal to the second output terminal, and the second control terminal to the second control terminal. The clock signal is switched to the first output terminal when a logic on / off signal is supplied.

In the driving device, the timing controller is configured to supply the image signals to the data lines using any one of a first clock signal output from the selection circuit and a second clock signal output from the second spread spectrum circuit. And generating and supplying data control signals for controlling the driving of the data driver and scan control signals for controlling the driving of the scan driver for supplying the scanning signals to the scan lines.

In the driving apparatus, the selection circuit and the second spread spectrum circuit are integrated in the timing controller.

A method of driving a flat panel display device according to an embodiment of the present invention includes a first step of providing a flat panel including a cell matrix formed of cells formed at regions defined by intersections of scan lines and data lines, and an image on the flat panel. A second step of generating image data, a clock signal, and a synchronization signal for displaying a; a third step of modulating a frequency of the clock signal into a first clock signal; and one of the clock signal and the first clock signal A fourth step of synchronizing the image data and the synchronization signal to the signal of the signal and transmitting the same through the interface lines, and a fifth step of selectively outputting the clock signal and the first clock signal according to whether the clock signal is modulated; A sixth step of modulating a frequency of the clock signal selected and supplied from the fifth step into a second clock signal; And a seventh step of generating and supplying control signals for displaying the video signal on the flat panel using any one of a first clock signal and a second clock signal.

The method may further include transmitting an on / off signal corresponding to the presence or absence of the modulation of the clock signal through an on / off signal line among the interface lines.

In the driving method, the transmitting of the on / off signal may include transmitting an on / off signal in a first logic state when the clock signal is modulated into the first clock signal, and the clock signal is the first clock signal. When not modulated, the on / off signal of the second logic state different from the first logic state is transmitted.

In the driving method, the step 5 supplies the first clock signal to the seventh step in response to the on / off signal of the first logic state and the clock in response to the on / off signal of the second logic state. The signal is supplied to the sixth step.

In the driving method, the seventh step may generate data control signals for controlling driving of a data driver for supplying the image signal to the data lines by using any one of the first and second clock signals. And generating scan control signals for controlling the driving of the scan driver for supplying the scanning signals to the scan lines.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 6.

Referring to FIG. 3, a driving device of a flat panel display (hereinafter referred to as “FPD”) according to an exemplary embodiment of the present invention spreads the frequency of the input clock signal DCLK from the graphics card 148. Spread spectrum according to a driving state of a first spread spectrum integrated circuit (hereinafter referred to as "SS IC") 144 that generates a first dot clock signal DCLK1. SS ") and a drive system 140 for generating an on / off signal SSop and converting an analog graphic signal from the graphics card 148 into digital pixel data, and an input supplied from the drive system 140. The frequency of the clock signal DCLK is diffused to generate the second dot clock signal DCLK2 and the first dot clock signal DCLK1 and the second in response to the SS on / off signal SSop from the driving system 140. The clock signals DCLK1 and DCLK2 of one of the dot clock signals DCLK2 may be FPD 200 for generating control signals for displaying digital pixel data from the drive system 140 on the flat panel 102 and transmitting and driving signals between the FPD 200 and the drive system 140. And an interface line 150 for transmitting the SS on / off signal SSop from the system 140 to the FPD 200.

The driving system 140 spreads the frequencies of the graphics card 148 generating the analog graphics signal and the input clock signal DCLK input from the graphics card 148 to generate the first dot clock signal DCLK1. The analog graphics signal from the graphics card 148 is converted into digital pixel data RGB in accordance with the first SS IC 144 and the first dot clock signal DCLK1 from the first SS IC 144. The transmission interface unit 142 transmits the pixel data RGB, various synchronization signals DE, Vsync, Hsync, DCLK, and SS on / off signal SSop.

The transmission interface unit 142 of the driving system 140 converts the analog graphic signal generated from the graphics card 148 to match the characteristics of the flat panel 102 and supplies it to the FPD 200 via the flat panel 102. At this time, the transmission interface unit 142 is a large screen of the flat panel 102, and as the data processing speed increases as the resolution becomes higher, such as UXGA (1200 * 1600), QXGA (2048 * 1600), QSXGA (2560 * 2048), etc. In order to reduce electromagnetic interference (hereinafter, referred to as "EMI") in which harmonic components different from the signal are generated, the first dot clock signal DCLK1 frequency-spread within a specific frequency range according to the SS scheme is used. The analog graphic signal generated from the graphics card 48 is converted to match the characteristics of the flat panel 102 and supplied to the FPD 2200 through the interface line 150.

Accordingly, the first SS IC 144 pulse-width modulates the frequency of the input clock signal DCLK from the graphics card 148 into the first dot clock signal DCLK1 having a different phase to transmit the transmission interface unit 142. To supply. Here, the first SS IC 144 is a commercially available integrated circuit that modulates a phase of a digital pulse signal by a phase locked loop. The first SS IC 144 widens the frequency band of the input clock signal DCLK supplied from the graphics card 148 to the transmission interface unit 142 and distributes the frequency, thereby concentrating energy in a specific frequency band, thereby reducing the EMI reference value. It serves to prevent the phenomenon exceeding.

The interface line 150 is connected between the transmission interface unit 142 and the FPD 200, as shown in FIG. 4, so that the pixel data RGB and various signals DE, Vsync, Hsync, DCLK, SSop, GND, VDD) and the like are transmitted to the FPD 200. To this end, the interface line 150 includes a plurality of RGB transmission lines (RGB), DE transmission lines, Vsync lines, Hsync lines, DCLK lines, a plurality of GND lines, VDD lines and a plurality of dummy lines. . At this time, one of the input clock signal DCLK from the graphics card 148 and the first dot clock signal DCLK1 output from the first SS IC 144 is transmitted to the DCLK line.

In addition, any one of a plurality of GND lines and dummy lines may be used as the SSop transmission line 152 for transmitting the SS on / off signal SSop generated by the driving system 140 to the FPD 200. .

The SSop transmission line 152 is supplied with a logic signal of any one of a high state and a low state by a system engineer according to the driving state of the first SS IC 144. That is, when the first SS IC 144 is installed in the driving system 140 to perform the EMI reduction function, the SSop transmission line is supplied to the SSop transmission line 152, for example, a logic signal in a low state. 152 is connected to the ground voltage source GND. Accordingly, the SSop transmission line 152 always supplies a logic signal in a low state to the FPD 200. On the other hand, when the first SS IC 144 is installed in the driving system 140 and does not perform the EMI reduction function, the SSop is supplied to the SSop transmission line 152 so as to supply a logic signal of, for example, a high state. The transmission line 152 is connected to the voltage source VDD. Accordingly, the SSop transmission line 152 always supplies a logic signal of a high state to the FPD 200.

Accordingly, when the logic state on the SSop transmission line 152 is LOW, the pixel data RGB transmitted from the driving system 140 to the FPD 200 and various synchronization signals DE, Vsync, Hsync, DCLK or DCLK1 are transmitted by the first SS IC 144 according to the SS scheme, while the logical state on the SSop transmission line 152 is high to transmit to the FPD 200 from the drive system 140. The pixel data RGB and various synchronization signals DE, Vsync, Hsync, DCLK or DCLK1 are transmitted by a general transmission method.

The FPD 200 includes a flat panel 102 having a cell matrix, a scan driver 104 for driving scan lines of the flat panel 102, and a data driver for driving data lines of the flat panel 102. 106 and a reception interface unit 112 for receiving pixel data RGB and various signals DE, Vsync, Hsync, DCLK, SSop, GND, and VDD transmitted from the driving system 140 through the interface line 150. ), A second SS IC 110 generating a second dot clock signal DCLK2 by spreading a frequency of the input clock signal DCLK supplied from the receiving interface unit 112, and the second SS IC 110. Generates a scan control signal SCS and a data control signal DCS for controlling the driving timing of the scan driver 104 and the data driver 106 according to the first and second dot clock signals DCLK1 and DCLK2 from On / off signal SSop from timing control unit 108 and receiving interface unit 144 In response, the flat panel display device 200 including an SS function selector 154 for supplying an input clock signal DCLK from the receiving interface unit 144 to any one of an input terminal and an output terminal of the second SS IC 110. ). Here, the reception interface unit 112, the second SS IC 110, the timing controller 108, and the SS function selection unit 154 are mounted on the printed circuit board 120.

The flat panel 102 of the FPD 200 has a cell matrix composed of cells formed at each region defined by the intersection of scan lines and data lines. The flat panel 102 may be any one of a liquid crystal panel, a plasma display panel, an electroluminescence panel, and a field emission display panel.

The scan driver 104 drives the scan lines of the flat panel 102 in response to the scan control signal SCS supplied from the timing controller 108.

The data driver 106 supplies the pixel data RGB supplied from the timing controller 108 to the data lines based on the data control signal DCS supplied from the timing controller 108.

The reception interface unit 112 receives pixel data RGB and various signals DE, Vsync, Hsync, DCLK or DCLK1, SSop, GND, and VDD transmitted from the driving system 140 through the interface line 150. It supplies to the timing control part 108. At this time, the SS on / off signal SSop and the input clock signal DCLK or the first dot clock signal DCLK1 received by the reception interface unit 112 are supplied to the SS function selection unit 154.

As shown in FIG. 5, the SS function selector 154 includes a control terminal to which the SS on / off signal SSop is supplied, an input terminal to which the clock signals DCLK and DCLK1 are supplied from the reception interface unit 112, and And a first output terminal connected to the input terminal of the second SS IC 110 and a second output terminal connected to the output terminal of the second SS IC 110.

The SS function selector 154 switches the clock signals DCLK and DCLK1 input through the input terminal to either the first output terminal or the second output terminal according to the SS on / off signal SSop. Specifically, in the case of the SS on / off signal SSop in the low state LOW, the first dot clock signal DCLK1 subjected to SS processing by the first SS IC 144 of the driving system 140 is the SS function selection unit. The second output terminal 154 is switched to the timing controller 108 through an output terminal of the second SS IC 110. Here, the SS on / off signal SSop in the low state LOW is various signals transmitted from the driving system 140 to the FPD 200 by various SS signals of the first SS IC 144. The first dot clock signal DCLK1 is transmitted from the driving system 140 to the FPD 200 because it is a signal for notifying the FPD 200. Accordingly, the SS function selector 154 prevents the first dot clock signal DCLK1 from being double-spreaded by the second SS IC 110 and is poor in image quality due to asynchronous driving timing due to the dual SS function. In order to prevent the error, the first dot clock signal DCLK1 is bypassed to the output terminal of the second SS IC 110.

On the other hand, when the SS on / off signal SSop of the high state HIGH is not SS processed by the first SS IC 144 of the driving system 140, the input clock signal DCLK by the general signal transmission method is Switched to the first output terminal of the SS function selection unit 154 is supplied to the input terminal of the second SS IC (110). In this case, the SS on / off signal SSop of the high state HIGH may not be installed on the driving system 140, or the first SS IC 144 may be driven. It is a signal notifying the FPD 200 that the various signals are transmitted by the general signal transmission method. Thus, the input clock signal DCLK generated by the graphics card 148 is transmitted from the driving system 140 to the FPD 200 as it is. Accordingly, the SS function selector 154 transmits the input clock signal DCLK through its first output terminal to the second SS IC 110 to reduce EMI generated between signal transmissions in the FPD 200. It is supplied to the input terminal of. Accordingly, the second SS IC 110 pulse-width modulates the frequency of the input clock signal DCLK from the receiving interface unit 112 to the second dot clock signal DCLK2 having a different phase to the timing controller 108. Supply. Here, the second SS IC 110 is a commercially available integrated circuit that modulates the phase of the digital pulse signal by a phase locked loop. The second SS IC 110 widens the frequency band of the input clock signal DCLK supplied to the receiving interface unit 112 to distribute the frequency, thereby preventing energy from being concentrated in a specific frequency band and exceeding an EMI threshold. It plays a role.

The timing controller 108 controls the data control signal DCS and the scan control signal SCS by using any one of the first and second dot clock signals DCLK1 and DCLK2 supplied from the second SS IC 110. Will be created. As such, the data control signal DCS generated in synchronization with any one of the first and second dot clock signals DCLK1 and DCLK2 is supplied to the data driver 106, and the scan control signal SCS is applied to the scan driver ( 104). Accordingly, the frequency of the control signals DCS and SCS generated by the timing controller 108 is not kept constant, but a specific frequency range according to any one of the first and second dot clock signals DCLK1 and DCLK2. It has a form of shaking in the inside, and as a result it is possible to obtain the effect of canceling and reducing the EMI between the control signals by the shaking frequency.

As described above, the FPD driving apparatus and method according to an embodiment of the present invention generates clock signals using any one of the first SS IC 144 of the driving system and the second SS IC 110 of the FPD 200. As a result, EMI generated during signal transmission can be canceled and driving timing margin can be increased.

On the other hand, referring to Figure 6, the driving device of the FPD according to another embodiment of the present invention has the same configuration as the driving device of the FPD according to the embodiment of the present invention shown in Figure 3, only the second SS IC (110) ) And the SS function selection unit 154 are integrated into the timing control unit 108 and embedded therein. Accordingly, the FPD driving apparatus according to another embodiment of the present invention can reduce the size of the printed circuit board 120 and increase the signal transmission efficiency.

As described above, the driving apparatus and method of the flat panel display device according to the embodiment of the present invention is an electron generated during the signal transmission by selectively using the spread spectrum function of the flat panel display device in accordance with the presence or absence of the spread spectrum function in the drive system Miracle interference can be canceled and the margin of driving timing between the drive system and the flat panel display can be increased. As a result, the driving apparatus and method of the flat panel display device according to the embodiment of the present invention can improve the display quality by preventing noise generated on the display screen of the flat panel due to the timing between the drive system and the flat panel display device. .

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram illustrating a driving apparatus of a flat panel display device according to the related art.

FIG. 2 is a waveform diagram showing frequency modulation of the spread spectrum integrated circuit shown in FIG.

3 is a block diagram illustrating a driving apparatus of a flat panel display device according to an exemplary embodiment of the present invention.

4 shows the interface lines shown in FIG. 3;

FIG. 5 is a circuit diagram illustrating a spread spectrum function selection unit shown in FIG. 3. FIG.

6 is a block diagram illustrating a driving device of a flat panel display device according to another exemplary embodiment.

<Description of Symbols for Main Parts of Drawings>

2, 102: flat panel 4, 104: scan driver

6, 106: data driver 8, 108: timing controller

10, 44, 110, 144: spread spectrum IC 12, 112: receiving interface unit

20, 120: printed circuit board 40, 140: drive system

42, 142: transmission interface unit 48, 148: graphics card

50, 150: interface lines 100, 200: flat panel display

154 spread spectrum function selection unit

Claims (12)

A flat panel including a cell matrix composed of cells formed at each region defined by the intersection of scan lines and data lines; A graphics card for generating image data, clock signals, and synchronization signals for displaying an image on the flat panel; A first spread spectrum circuit for modulating a frequency of the clock signal into a first clock signal; A transmitter configured to synchronize the image data and the synchronization signal to any one of the clock signal and the first clock signal and transmit the same through the interface lines; A selection circuit for selectively outputting the clock signal and the first clock signal according to whether the first spread spectrum circuit is driven; A second spread spectrum circuit for modulating a frequency of the clock signal output from the selection circuit into a second clock signal; A timing controller for generating and supplying control signals for displaying the video signal on the flat panel using any one of a first clock signal output from the selection circuit and a second clock signal output from the second spread spectrum circuit. A driving apparatus of the flat panel display device characterized in that it comprises a. The method of claim 1, And the on / off signal line for transmitting an on / off signal corresponding to whether the first spread spectrum circuit is driven or not is included in the interface lines. The method of claim 2, The on / off signal is, When the first spread spectrum circuit is driven, it is connected to a first voltage source and enters a first logic state, And when the first spread spectrum circuit is not driven, is connected to a second voltage source so as to be in a second logic state different from the first logic state. The method of claim 3, wherein The selection circuit, An input terminal to which any one of the clock signal and the modulated clock signal is supplied; A first output terminal connected to an input terminal of the second spread spectrum circuit, A second output terminal connected to an output terminal of the second spread spectrum circuit, And a control terminal for selectively switching the clock signal supplied to the input terminal to the first and second output terminals according to the on / off signal. The method of claim 4, wherein The selection circuit, When the on / off signal of the first logic state is supplied to its control terminal, the modulated clock signal is switched to the second output terminal, And a clock signal is switched to the first output terminal when the on / off signal of the second logic state is supplied to its control terminal. The method of claim 1, The timing controller, For controlling driving of a data driver for supplying the image signals to the data lines using any one of a first clock signal output from the selection circuit and a second clock signal output from the second spread spectrum circuit. And generating and supplying data control signals and scan control signals for controlling driving of a scan driver for supplying scanning signals to the scan lines. The method of claim 1, And the selection circuit and the second spread spectrum circuit are integrated in the timing controller. A first step of providing a flat panel including a cell matrix composed of cells formed at each region defined by the intersection of scan lines and data lines; A second step of generating image data, clock signals, and synchronization signals for displaying an image on the flat panel; Modulating a frequency of the clock signal into a first clock signal; A fourth step of synchronizing the image data and the synchronization signal to any one of the clock signal and the first clock signal and transmitting them through interface lines; A fifth step of selectively outputting the clock signal and the first clock signal according to whether the clock signal is modulated; A sixth step of modulating a frequency of the clock signal selected and supplied from the fifth step into a second clock signal; And a seventh step of generating and supplying control signals for displaying the image signal on the flat panel using one of the first clock signal and the second clock signal. . The method of claim 8, And transmitting an on / off signal corresponding to the presence or absence of the modulation of the clock signal through an on / off signal line among the interface lines. The method of claim 9, Transmitting the on / off signal, Transmits an on / off signal of a first logic state when the clock signal is modulated with the first clock signal, And transmitting the on / off signal of a second logic state different from the first logic state when the clock signal is not modulated by the first clock signal. The method of claim 10, The five steps, Supplying the first clock signal to the seventh step in response to an on / off signal of the first logic state, And supplying the clock signal to the sixth step in response to the on / off signal of the second logic state. The method of claim 8, The seventh step, One of the first and second clock signals is used to generate data control signals for controlling driving of a data driver for supplying the image signal to the data lines, and supply a scanning signal to the scan lines. And generating scan control signals for controlling driving of the scan driver.