KR20040063429A - Apparatus and method for measuring the skew of signals - Google Patents

Abstract

PURPOSE: A skew measurement unit and its method are provided to analyze the characteristics of a semiconductor device determined by skew by measuring the skew between internal signals of the semiconductor device. CONSTITUTION: According to the skew measurement unit(100), an amplifier(40) comprises the first input port, the second input port and an output port, and converts skew existing between the first signal inputted to the first input port and the second input signal inputted to the second input port into a voltage, and outputs the amplified voltage through the output port. An analog-digital converter(50) is connected to the output port of the amplifier, and receives a reference voltage(Vref) and the voltage inputted through the output port of the amplifier, and converts the voltage inputted through the output port of the amplifier into N bit parallel data, and outputs the N bit parallel data. And an N-bit register(60) converts the N bit parallel data into serial data, and outputs the serial data in response to a control signal.

Description

Apparatus and method for measuring the skew of signals}

The present invention relates to a skew measuring apparatus and a skew measuring method, and more particularly, to an apparatus and a method capable of measuring a skew generated between signals inside a memory device in a wafer or package state.

In general, a simulation used to determine characteristics of a semiconductor device predicts skew between internal signals of the semiconductor device, and thus, in an environment affected by actual PVT, skew between internal signals of the semiconductor device may be reduced. There is no way to know.

Therefore, in identifying the important characteristics of the semiconductor device, due to the difference between the measured value of the output signal (s) of the semiconductor device and the result obtained through the simulation, there is a problem that the characteristics of the semiconductor device cannot be accurately understood. have.

Accordingly, a technical object of the present invention is to provide an apparatus and method capable of directly analyzing the skew between internal signals of a semiconductor device and directly analyzing the characteristics of the semiconductor device determined by the skew.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 shows a block diagram of a skew measuring apparatus according to the present invention.

FIG. 2 shows a circuit diagram of the amplifier shown in FIG. 1.

FIG. 3 shows a circuit diagram of the OP amplifier shown in FIG. 2.

4 shows a circuit diagram of the analog-to-digital converter shown in FIG. 1.

FIG. 5 shows a circuit diagram of the comparator shown in FIG. 4.

6 shows a timing diagram of a skew measuring apparatus according to the present invention.

7 is a flowchart illustrating a method of correcting skew according to the present invention.

8 is a flowchart illustrating a method of measuring skew in accordance with the present invention.

The skew measuring apparatus according to the present invention includes a first input terminal, a second input terminal, and an output terminal, and includes a predetermined skew between the first signal input to the first input terminal and the second signal input to the second input terminal. An amplifier converting the voltage and outputting the voltage amplified through the output terminal; Connected to an output terminal of the amplifier, receiving a reference voltage and a voltage input through an output terminal of the amplifier, converting a voltage input through the output terminal of the amplifier into N-bit parallel data, and outputting the N-bit parallel data Analog-to-digital converters; And an N-bit register for converting the N-bit parallel data into serial data and outputting the serial data in response to a control signal.

The amplifier receives a first node 250, the first signal S1, and the inverted second signal S2, and includes a first negative AND gate 243 that is negative AND, and the first negative AND. A pull-up circuit 247 that pulls up the first node 250 to a power supply voltage VDD in response to an output signal Sout of a gate, and the first node 250 in response to a reset signal RESET. ) Is a pull-down circuit 251 that pulls down to ground voltage VSS, an output signal of the first negative AND gate, and an inverted reset signal, and a second negative AND gate that performs an AND logic. 255, connected between the second node 269 and the first node 250, in response to the output signal T1 of the second negative AND gate 255, the first node and the second node. A first transistor 267 connected to receive an output signal of the second negative AND gate and an output signal of the second negative AND gate delayed for a predetermined time; A negative capacitor gate connected to the negative logic gate 265, the first node CS connected to the second node 269 and the ground voltage, a first input terminal (+), a second input terminal (−), and an output terminal 274. An amplifier 273 for comparing the voltage VA input to the first input terminal with a reference voltage Vref, and outputting the comparison result through the output terminal 274, and a first input terminal of the amplifier. And a second capacitor CH connected between an output terminal of the amplifier and a first input terminal of the amplifier and the second node, the first node in response to an output signal of the negative OR gate 265. And a second transistor 271 connecting the second node.

The analog-to-digital converter compares a plurality of resistors connected in series to distribute the reference voltage, the output signal of the amplifier and the voltage of the corresponding first stage of each of the plurality of resistors, and the comparison result It has a plurality of comparators for outputting each.

The skew measuring apparatus according to the present invention receives two selection circuits for selecting one of an internal signal and an external signal in response to a corresponding selection signal, and receives output signals of the two selection circuits, and outputs the output signals. Generating a pulse having a width corresponding to a skew difference existing therebetween, generating and amplifying a voltage corresponding to the width of the pulse and receiving an amplifier, a reference voltage and an output signal of the amplifier, An analog-to-digital converter for converting the output signal to N-bit parallel data, and an N-bit register for converting the N-bit parallel data to serial data and outputting the serial data in response to a control signal. The skew difference existing between the output signals can be adjusted.

The skew measuring apparatus capable of measuring skew between internal signals according to the present invention outputs a first external signal when the skew measuring apparatus is corrected, and outputs a first internal signal when measuring the skew between the internal signals. A second selection circuit for outputting a second external signal when the skew measuring device is calibrated, and a second internal signal when the skew between the internal signals is measured; Receiving an output signal and an output signal of the second selection circuit, generating a pulse having a width corresponding to a skew present between the output signal of the first selection circuit and the output signal of the second selection circuit; An amplifier for generating and amplifying a voltage corresponding to the width of the pulse, an analog for receiving a reference voltage and an output signal of the amplifier, and converting the output signal of the amplifier into N-bit parallel data A digital converter and an N-bit register for converting the N-bit parallel data into serial data and outputting the serial data in response to a control signal.

The skew measuring method according to the present invention converts a predetermined skew between a first signal input to a first input terminal and a second signal input to a second input terminal into a voltage, and outputs the amplified voltage through the output terminal. Receiving a reference voltage and a voltage input through the output terminal, converting the voltage input through the output terminal into N-bit parallel data, outputting the N-bit parallel data, and serializing the N-bit parallel data Converting to data and outputting the serial data in response to a control signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 shows a block diagram of a skew measuring apparatus according to the present invention. Referring to FIG. 1, a skew measuring apparatus 100 implemented as a semiconductor chip includes a selection signal generating circuit 10, two selection circuits 20 and 30, an amplifier 40, and an analog-to-digital converter. a digital converter (ADC) 50 and an N-bit register 60;

The selection signal generation circuit 10 may be implemented as an AND gate 11. The AND gate 11 receives a calibration enable signal CAL_En and a test signal TestMode, ANDs the CAL_En and TestMode, and selects the AND product SEL first. Output to the circuit 20 and the second selection circuit 30.

When the skew measuring device 100 is calibrated (e.g., when measuring the skew generated between the two external signals using at least two external signals to prepare a skew-to-digital output value table), The enable signal CAL_En and the test signal TestMode are activated (e.g., logic high), and when the skew measurement device 100 measures the skew generated between internal signals of the semiconductor device after calibrating the skew measuring device 100, the test signal TestMode Remains active and the correction enable signal CAL_En is deactivated (e.g., logic low).

The first selection circuit 20 selectively selects one signal S1 among the first external signal Ext_1 and the first internal signal Int_1 in response to the output signal SEL of the AND gate 11. )

That is, the first selection circuit 20 outputs the first external signal Ext_1 when correcting the skew measuring apparatus 100 and outputs the first internal signal Int_1 when measuring the skew between the internal signals. .

The second selection circuit 30 transfers one signal S2 from the second external signal Ext_2 and the second internal signal Int_2 to the amplifier 40 in response to the output signal SEL of the AND gate 11. Optionally output

That is, the second selection circuit 30 outputs the second external signal Ext_2 when the correction skew measuring apparatus 100 is corrected, and outputs the second internal signal Int_2 when the skew between the internal signals is measured. do.

The amplifier 40 receives the output signal S1 of the first selection circuit 20 and the output signal S2 of the second selection circuit 30, and has a width corresponding to the skew difference between them (S1, S2). A pulse having a width) is generated, the pulse is amplified, and the amplification result Vout is output. Here, the output signal S1 of the first selection circuit 20 and the output signal S2 of the second selection circuit 30 have a predetermined controllable skew.

The analog-to-digital converter 50 receives the reference voltage Vref and the output signal Vout of the amplifier 40, and converts the output signal Vout of the amplifier 40 into N-bit parallel data D <N-1: 0>).

The N-bit register 60 converts the N-bit parallel data D <N-1: 0> into serial data and outputs serial data Dout in response to the control signal LOAD. The output serial data Dout may be measured through a predetermined measuring device.

FIG. 2 shows a circuit diagram of the amplifier shown in FIG. 1. Referring to FIG. 2, the amplifier 40 includes a plurality of logic gates 241, 243, 249 and 255, a plurality of MOS transistors 245, 247, 251, 253, 267 and 271, and a pulse generator 257. , Two capacitors C _S , C _H and an OP amplifier 273.

The inverter 241 inverts the output signal S2 of the second selection circuit 30, and the NAND gate 243 converts the output signal S1 of the first selection circuit 20 and the output signal of the inverter 241. And negatively multiply them, and output the negative AND product Sout to the gate and NAND gate 255 of the PMOS transistor 247.

The node 250 is connected to the power supply voltage VDD through the PMOS transistors 245 and 247 connected in series, and the gate of the PMOS transistor 245 is connected to the first bias voltage VB1. The first bias voltage VB1 preferably has a level of the ground voltage VSS. In this case, the PMOS transistor 245 is always turned on.

The node 250 is connected to the ground voltage VSS through the NMOS transistors 251 and 253 connected in series. The reset signal RESET is input to the gate of the NMOS transistor 251 and the input terminal of the inverter 249, and the second bias voltage VB2 is input to the gate of the NMOS transistor 253. The second bias voltage VB2 preferably has a level of the power supply voltage VDD. In this case, the NMOS transistor 253 is always kept on.

The reset signal RESET is a signal obtained by performing a logic operation on the correction enable signal Cal_En and the delayed correction enable signal Cal_En through a plurality of inverters. Referring to FIG. 6, the reset signal RESET is a pulse having a predetermined width.

The inverter 249 inverts the reset signal RESET, and the NAND gate 255 receives the output signal Sout of the NAND gate 243 and the output signal of the inverter 249, negates AND of these, and negates logic. The product T1 is output to the gate of the pulse generator 257 and the NMOS transistor 267.

The pulse generator 257 has a plurality of inverters 259, 261, 263 and a NOR gate 265. Each of the plurality of inverters 259, 261, 263 is connected in series with each other to form a delay chain. The NOR gate 265 receives the output signal T1 of the NAND gate 255 and the output signal of the inverter 263, performs a negative logic sum on them, and turns the result of the negative logic sum T2 into the gate of the NMOS transistor 271. Output

NMOS transistor 267 is connected between node 250 and node 269, and NMOS transistor 271 is connected between node 269 and node 272.

Capacitor CS is connected between node 269 and ground voltage VSS, and capacitor C _H is connected between node 272 and output terminal 274 of amplifier 273. The amplifier 273 receives the reference voltage Vref and the voltage VA of the node 272, amplifies the difference between them (Vref and VA), and outputs an amplification result Vout.

FIG. 3 shows a circuit diagram of the OP amplifier shown in FIG. 2. Referring to FIG. 3, the amplifier 273 includes a plurality of MOS transistors 2731, 2735, 2739, and 2741 and a current source 2745.

The PMOS transistor 2731 is connected between the power supply voltage VDD and the node 2731, and the PMOS transistor 2735 is connected between the power supply voltage VDD and the node 2735 and the PMOS transistors 2731 and 2735 are connected. Each gate of is connected between nodes 2735. PMOS transistors 2731 and 2735 constitute a current mirror.

The NMOS transistor 2739 is connected between the node 2731 and the node 2743, and the input voltage VA is input to the gate of the NMOS transistor 2739. The NMOS transistor 2741 is connected between the node 2737 and the node 2743, and the reference voltage Vref is input to the gate of the NMOS transistor 2741. The voltage Vout of the node 2739 becomes the output voltage of the amplifier 273. Current source 2745 is connected between node 2743 and ground voltage VSS.

The amplifier 273 amplifies the difference between the voltages VA and Vref input to the gates of the NMOS transistors 2739 and 2741, and outputs an amplification result Vout through the node 2737.

4 shows a circuit diagram of the analog-to-digital converter shown in FIG. 1. Referring to FIG. 4, the analog-to-digital converter 50 includes a plurality of resistors R1, R2, R (n-1) and Rn and a plurality of comparators 351, 353, 355, and 357 connected in series. It is provided.

Each of the comparators 351, 353, 355, and 357 is a first signal corresponding to the output signal Vout of the charge pump and the amplifier 40 and the plurality of resistors R1, R2, R (n-1), and Rn, respectively. The voltages VR1, VR2, VR (n-1) and VRn of the stages are compared, and the comparison results D0, D1, D (N-2) and D (N-1) are output.

Resistor R1 is connected between power supply voltage VDD and node 361, resistor R2 is connected between node 361 and node 363, and resistor Rn is connected to node 365 and node. 367 is connected. By voltage distribution, the voltages of the nodes 361, 363, 365, and 367 are VR1, VR2, VR (n-1), and VRn, respectively.

For example, the comparator 351 receives and compares the output signal Vout of the charge pump and the amplifier 40 input to the negative input terminal and the voltage VR1 of the node 361 input to the positive input terminal and compares the voltage. The comparison result D0 is output, and the comparator 357 outputs the charge signal inputted to the negative input terminal and the output signal Vout of the amplifier 40 and the voltage VRn of the node 367 inputted to the positive input terminal. ) Is received and compared, and the comparison result D (N-1) is output.

FIG. 5 shows a circuit diagram of the comparator shown in FIG. 4. 4 and 5, only the comparator 351 is shown in FIG. 5, but the structures of the remaining comparators 353, 355, and 357, which are not shown, may be easily understood by those skilled in the art with reference to FIGS. 4 and 5. have.

The PMOS transistor 3511 is connected between the power supply voltage VDD and the node 3515, the PMOS transistor 3513 is connected between the power supply voltage VDD and the node 3519, and the gate of the PMOS transistor 3511 is It is connected to a node 3519, and a gate of the PMOS transistor 3513 is connected between the nodes 3515. Input terminals of the inverters 3517 and 3521 are connected to the nodes 3515 and 3519. The output signal Do of the inverter 3351 is an output signal of the comparator 351.

The NMOS transistor 3525 is connected between the node 3515 and the node 3519, and the inverted test signal TestModeB is input to the gate of the NMOS transistor 3525.

NMOS transistor 3525 is connected between node 3515 and ground voltage VSS, and NMOS transistor 3529 is connected between node 3529 and ground voltage VSS. The output signal Vout of the charge pump and the amplifier 40 is input to the gate of the NMOS transistor 3525 through the NMOS transistor 3523 corresponding to the test signal TestMode, and the voltage VR1 of the node 361 is It is input to the gate of the NMOS transistor 3529 through the NMOS transistor 3531 in response to the test signal TestMode.

6 shows a timing diagram of a skew measuring apparatus according to the present invention. The operation of the skew measuring apparatus according to the present invention will be described with reference to FIGS. 1 to 6 as follows.

First, the skew measuring apparatus 100 needs to be corrected in order to cancel the variation of the measured value of the skew between internal signals according to the PVT change.

When the skew measuring apparatus 100 is corrected, the test signal TestMode and the correction enable signal CAL_En are activated. Accordingly, the first selection circuit 20 outputs the first external signal Ext_1 as the output signal S1 in response to the output signal of the selection signal generation circuit 10, and the second selection circuit 30 generates the selection signal. The second external signal Ext_1 is output as the output signal S2 in response to the output signal of the circuit 10.

Referring to FIG. 6, the NAND gate 243 may include a pulse having a width corresponding to a skew difference between an output signal S1 of the first selection circuit 20 and an output signal S2 of the second selection circuit 30. Sout) is generated and output to the gate and the NAND gate 255 of the PMOS transistor 247.

Therefore, since the PMOS transistor 247 and the NMOS transistor 267 are turned on for a time corresponding to the width of the pulse Sout, the capacitor C _S is charged by ΔV for a time corresponding to the width of the pulse Sout. .

The NMOS transistor 271 is turned on in response to the output signal T2 of the pulse generator 257 after a predetermined time results after the NMOS transistor 267 is turned off. Therefore, the voltage Vin of the node 250 is input to the positive input terminal of the amplifier 273 by the output signal T1 of the NAND gate 255 and the output signal T2 of the pulse generator 257. The amplifier 273 receives the voltage VA of the node 272 input to the positive input terminal and the reference voltage Vref input to the negative input terminal, and outputs a voltage Vout represented by Equation 1 below. do.

Vout ∝ (C _S / C _H ) × ΔV

Referring to FIG. 4, the analog-to-digital converter 50 converts the output voltage Vout of the amplifier 273 into N-bit parallel digital codes D <N-1: 0>. That is, the analog-to-digital converter 50 outputs each of the voltages VR1, VR2M VR (n-1), VRn) and the amplifier 273 which voltage-divides the reference voltage Vref into N resistors connected in series. The voltages Vout are compared, respectively, and N-bit parallel digital codes D0, D1, D (N-2), and D (N-1) corresponding to the comparison result are output.

The N-bit register 60 receives the N-bit parallel digital code D <N-1: 0> output from the analog-to-digital converter 50 and converts it into serial data Dout, and the control signal LOAD. In response, the serial data Dout is output.

When the serial data Dout is read by repeatedly performing the above-described measurement method while changing the skew of the first external signal Ext_1 and the second external signal Ext_2, a skew-to-digital value table is created.

After the skew-to-digital value table is created, when the semiconductor device is operated and the correction enable signal TestMode is deactivated, the first selection circuit 20 responds to the first signal in response to the output signal of the selection signal generation circuit 10. The internal signal Int_1 is output as the output signal S1, and the second selection circuit 30 sets the second internal signal Int_2 as the output signal S2 in response to the output signal of the selection signal generation circuit 10. Output

Through the above-described process, the serial data Dout output from the N-bit register 60 is read out, and the digital data corresponding to the serial data Dout read from the already prepared skew-to-digital value table is compared and read. The skew corresponding to the serial data Dout can be measured.

7 is a flowchart illustrating a method of correcting skew according to the present invention. 1 to 7, a skew-to-digital value table must first be prepared to measure skew between internal signals of a semiconductor device.

First, when the correction starts (710), the selection signal generation circuit 10 receives the activated selection signal in response to the activated test signal TestMode and the activated correction enable signal CAL_En. And outputs to the second selection circuit 30 (720).

The first selection circuit 20 and the second selection circuit 30 output the first external signal Ext_1 and the second external signal Ext_2 as output signals S1 and S2, respectively, in response to the activated selection signal. .

In this case, the skew T between the output signal S1 of the first selection circuit 20 and the output signal of the second selection circuit 30 is 0 ns (730).

In step 740, the serial data Dout output from the N-bit register 60 is read to create a skew-to-digital value table (740), and the output signal S1 and the second selection circuit of the first selection circuit 20 are generated. It is determined whether the skew T between the output signals of 30 is the maximum T _MAX (750). If the skew T is not the maximum T _MAX , the skew T between the output signal S1 of the first selection circuit 20 and the output signal of the second selection circuit 30 is increased (T =). T + ΔT)). Steps 740 to 760 are repeatedly performed until the skew T becomes the maximum T _MAX .

When the skew T becomes the maximum T _MAX , a skew-to-digital value table is created (770) and the calibration is terminated (780).

8 is a flowchart illustrating a method of measuring skew in accordance with the present invention. 1 through 8, when skew measurement between internal signals is started (810), the selection signal generation circuit 10 responds to the activated test signal TestMode and the deactivated correction enable signal CAL_En. The deactivated selection signal is output to the first selection circuit 20 and the second selection circuit 30 (820).

The first selection circuit 20 and the second selection circuit 30 output the first internal signal Int_1 and the second internal signal Int_2 as output signals S1 and S2, respectively, in response to the inactive selection signal. .

The charge pump and amplifier 40 amplifies the skew present between the first internal signal Int_1 and the second internal signal Int_2 with the voltage Vout, and the ADC 50 converts the reference voltage Vref and the charge pump. And in response to the output signal Vout of the amplifier 40, the output signal Vout of the charge pump and the amplifier 40 is converted into N-bit parallel data D <N-1: 0>, and the N-bit register ( 60 converts the N-bit parallel data D <N-1: 0> into serial data Dout and outputs serial data Dout.

The measured serial data Dout is read (830), the skew corresponding to the measured serial data (Dout) from the skew-to-digital value table is measured (840), and the skew measurement procedure is terminated (850).

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, a skew measuring apparatus capable of measuring skew between internal signals according to the present invention directly measures skew between internal signals of a semiconductor device to directly analyze characteristics of the semiconductor device determined by the skew. It can work.

As described above, a skew measuring apparatus capable of measuring skew between internal signals according to the present invention can directly measure skew generated between internal signals of a semiconductor device in a wafer or package state, thereby operating characteristics of the memory device. It is effective to grasp exactly.

Claims (9)

In the skew measuring device, A first input terminal, a second input terminal, and an output terminal, converting a predetermined skew between a first signal input to the first input terminal and a second signal input to the second input terminal into a voltage, and converting the output terminal to a voltage. An amplifier for outputting the voltage amplified through; Connected to an output terminal of the amplifier, receiving a reference voltage and a voltage input through an output terminal of the amplifier, converting a voltage input through the output terminal of the amplifier into N-bit parallel data, and outputting the N-bit parallel data Analog-to-digital converters; And And an N-bit register for converting the N-bit parallel data into serial data and outputting the serial data in response to a control signal. The method of claim 1, wherein the amplifier, A first node; A first negative AND gate that receives the first signal and the inverted second signal and performs an AND logic; A pull-up circuit configured to pull-up the first node to a power supply voltage in response to an output signal of the first negative AND gate; A pull-down circuit for pulling down the first node to a ground voltage in response to a reset signal; A second negative AND gate receiving the negative NOR AND output signal of the first negative AND gate and the inverted reset signal; A first transistor connected between a second node and the first node, and connected to the first node and the second node in response to an output signal of the second negative AND gate; A negative OR gate which receives the output signal of the second negative AND gate and the output signal of the second negative AND gate delayed by a predetermined time and negates and ORs; A first capacitor connected between the second node and the ground voltage; An amplifier having a first input terminal, a second input terminal, and an output terminal, comparing the voltage input to the first input terminal with a reference voltage, and outputting the comparison result through the output terminal; A second capacitor connected between the first input terminal of the amplifier and the output terminal of the amplifier; And And a second transistor connected between the first input terminal of the amplifier and the second node, the second transistor connecting the first node and the second node in response to an output signal of the negative logic sum gate. Device. The method of claim 1, wherein the analog-to-digital converter, A plurality of resistors connected in series to distribute the reference voltage; And And a plurality of comparators for comparing the output signal of the amplifier and the voltage of the corresponding first stage of each of the plurality of resistors and outputting the comparison result. In the skew measuring device, Two selection circuits for selecting one of an internal signal and an external signal in response to a corresponding selection signal; An amplifier receiving the output signals of the two selection circuits, generating a pulse having a width corresponding to a skew difference existing between the output signals, and generating and amplifying a voltage corresponding to the width of the pulse ; An analog-to-digital converter that receives a reference voltage and an output signal of the amplifier and converts the output signal of the amplifier into N-bit parallel data; And And an N-bit register for converting the N-bit parallel data into serial data and outputting the serial data in response to a control signal. 6. The skew measuring apparatus according to claim 4, wherein a skew difference existing between the output signals can be adjusted. The method of claim 4, wherein the analog-to-digital converter, A plurality of resistors connected in series to distribute the reference voltage; And And a plurality of comparators for comparing the output signal of the amplifier and the voltage of the corresponding first stage of each of the plurality of resistors and outputting the comparison result. The skew measuring apparatus of claim 4, wherein the selection signal is activated when the skew measuring apparatus is corrected. In the skew measuring apparatus capable of measuring the skew between the internal signals, A first selection circuit outputting a first external signal when the skew measuring device is corrected, and a first internal signal when the skew between the internal signals is measured; A second selection circuit outputting a second external signal when the skew measuring device is corrected, and a second internal signal when the skew between the internal signals is measured; A width corresponding to a skew between the output signal of the first selection circuit and the output signal of the second selection circuit, the signal being present between the output signal of the first selection circuit and the output signal of the second selection circuit; An amplifier for generating a pulse having a voltage and generating and amplifying a voltage corresponding to the width of the pulse; An analog-to-digital converter that receives a reference voltage and an output signal of the amplifier and converts the output signal of the amplifier into N-bit parallel data; And And an N-bit register for converting the N-bit parallel data into serial data and outputting the serial data in response to a control signal. In the skew measurement method, Converting a predetermined skew between a first signal input to a first input terminal and a second signal input to a second input terminal into a voltage, and outputting the amplified voltage through an output terminal; Receiving a reference voltage and a voltage input through the output terminal, converting the voltage input through the output terminal into N-bit parallel data, and outputting the N-bit parallel data; And And converting the N-bit parallel data into serial data and outputting the serial data in response to a control signal.