KR20040057394A - Deskewing buffer and it's method for combiner of cdma receiver - Google Patents

Abstract

PURPOSE: A deskewing buffer of a combiner in a CDMA receiver is provided to combine data stored in the buffer with data outputted from a selection switch, and to reduce the number of deskewing buffers that compensate for time delay of each path to one, thereby reducing hardware burden. CONSTITUTION: A plurality of fingers(11-1N) output I/Q channel data by setting multiple paths every carrier after receiving data inputted through an antenna, demodulate the obtained multiple paths, and output. A data selection switch(40) selects data outputted from one of the fingers(11-1N) according to a time delay sequence of the multiple paths among the I/Q channel data, and outputs the selected data. A combiner(50) reads the data selected by the data selection switch(40) and data of other path whose timing is adjusted to the selected data from a deskewing buffer(60), adds the read data, and stores the added data in the deskewing buffer(60).

Description

DESKEWING BUFFER AND IT'S METHOD FOR COMBINER OF CDMA RECEIVER}

The present invention relates to a dequeuing buffer of a combiner of a code division multiple access receiver and a method of operating the same, and in particular, to improve a method of implementing a dequeuing buffer required by the number of passes to be combined, one dequeuing buffer regardless of the paths to be combined. The present invention relates to a dequeuing buffer of a combiner of a code division multiple access receiver and a method of operating the same.

Code division multiple access receivers combine signals received through multiple paths in order to increase reception sensitivity. This is because combining multiple multipath signals improves reception performance than using one path signal.

However, since the received signals of each path have different time delays, to combine the received signals of the multipaths, the output of this dequeuing buffer is combined using a dequeuing buffer that compensates for the time delay and allows the signal to be processed at the same time. do.

FIG. 1 is a block diagram showing the structure of a front end of a combiner in a conventional code division multiple access receiver. As shown in FIG. 1, a plurality of paths for demodulating and demodulating multiple paths in a signal received through an antenna and outputting I / Q channel data are shown in FIG. Fingers 11-1N; A plurality of deskew buffers 21-2N for compensating and storing time delays of the I / Q channel data; Composed of a combiner 30 for combining the data stored in the deskew buffer as described with reference to the coupling timing diagram shown in FIG.

A code division multiple access receiver puts a dequeuing buffer to combine signals with different time delays, and reads and combines the data stored in the dequeuing buffer at a certain time.

The size of the dequeuing buffer must be able to guarantee the difference between the point of reading from the combiner and the point of writing to the dequeuing buffer, which is defined as the maximum possible time difference of the multipath, so a large value is welcome, but due to the transmission latency and hardware overhead It can not be decided unconditionally.

However, in the prior art as described above, since the dequeuing buffer must be set separately for each path, there is a problem in that the size of the buffer is increased, resulting in an inefficient implementation method in hardware.

Accordingly, the present invention has been made in view of the above problems, and includes a dequeuing buffer of a combiner of a code division multiple access receiver capable of reducing the number of dequeuing buffers by performing channel data combining operations in front of the dequeuing buffer; The purpose is to provide a method of operation.

1 is a block diagram showing the configuration of a front end of a combiner in a conventional code division multiple access receiver.

FIG. 2 is a timing diagram of processing a signal at the same time by compensating for a time delay along a path of data stored in the deskew buffer of the combiner of FIG.

3 is a block diagram showing a configuration of a deskew buffer of a combiner of a code division multiple access receiver according to the present invention;

4 is an operation flowchart showing a method of operating a dequeuing buffer of a combiner of a code division multiple access receiver according to the present invention, and a timing diagram of data along a path illustrated to explain the same.

** Description of the symbols for the main parts of the drawings **

40: data selection switch 50: combiner

60: deskew buffer

The present invention for achieving the above object, the finger receiving the data received from the antenna to set the multi-path to output the channel data; A data selection switch for selectively outputting channel data of the finger; A buffer for storing an output signal of the data selection switch; And a combiner for combining the data stored in the buffer and the data output from the selection switch.

In addition, setting and outputting a multi-path for the received data; Selectively switching the output data; Storing the switched data; And combining the stored data with the switched data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram showing the configuration of a dequeuing buffer of a combiner of a code division multiple access receiver according to the present invention. As shown in FIG. A plurality of fingers 11 to 1N for outputting data; A data selection switch 40 for selecting and outputting data output from one finger according to the time delay order of the multipath among the I / Q channel data; The combiner 50 reads the data selected by the data selection switch 40 and the data of another path whose timing matches the selected data from the dequeuing buffer 60 and adds them to the dequeuing buffer 60. .

For convenience of explanation, assume that the join operation is performed by simple addition. The actual combining operation is multiplied with weights for each path, but the present invention is not related to combining, so the following description will be simplified.

The plurality of fingers 11 to 1N output I / Q channel data by demodulating a multipath for each carrier in a signal received through an antenna as in the related art.

The dequeuing buffer 60 is located in front of the combiner. Instead there are two buffer outputs, one corresponding to a conventional combiner output and the other to be data to be combined into the data output.

The data selection switch 40 operates N + 1 times faster than the finger to process the finger output data and read the buffer data. The data output from one finger is selected and output from the data output from the plurality of fingers 11-1N according to the time delay order of the multipath.

The selected data is input to the combiner 50 and added to the data of another path whose timing coincides with the data, and is input again to the dequeuing buffer 60. This process continues for one data cycle.

Thereafter, when data is read from the dequeuing buffer 60, the data of the corresponding address is cleared. This prevents the combined operation described above (ie, a kind of accumulation operation) from malfunctioning.

FIG. 4 is a flowchart illustrating an operation method of a dequeuing buffer of a combiner of a code division multiple access receiver according to the present invention, and a timing diagram of data along a path illustrated to explain the same. Referring to FIG. a) describes that in the case of three paths, road path B, which indicates the order in which data is received, is received first, A is received by one chip, and path C is received one chip later than path A.

FIG. 4B is an operation flowchart. As shown in FIG. 4B, the first output of the first quarter time slot of the chip period adds the finger output corresponding to the path A and the data of the dequeuing buffer corresponding to the address address 1. Storing in memory (S11); Adding a finger output corresponding to path B and data of a dequeuing buffer corresponding to address address 2 in a second quarter time slot of a chip period and storing the data in a second memory; Adding the finger output corresponding to the path C and the data of the dequeuing buffer corresponding to the address address 0 in the third quarter time slot of the chip period and storing the data in the zero memory (S13); Reading the data of the dequeuing buffer corresponding to address address 3 in the fourth quarter time slot of the chip period and inserting 0 into the third memory corresponding thereto (S14) and repeatedly performing this step every chip period (S15). S26), the following description is made with reference to the data timing diagram shown in FIG.

Suppose there are three paths through which incoming signals come in differently.

Because there are three paths, the dequeuing buffer requires four address spaces, three of which refer to memory that stores the signals received from each path, and the other refers to memory that reads data stored in the dequeuing buffer from the outside. Point. This is because the cycle of each path is 4 chips.

In order to process the signal received in path A, the combiner adds the finger output corresponding to path A and the data of the dequeuing buffer corresponding to address address 1 and stores it in the first memory in the first quarter time slot of the chip period. (S11).

Thereafter, the combiner stores the data of the finger output and the dequeuing buffer for the paths B and C by varying the address address as described above in the second and third quarter time slots of the chip period (S12 and S13).

In the fourth quarter time slot of the chip period, the data of the dequeuing buffer corresponding to address address 3 is externally read and assigned to 0 to be cleared (S14).

In the next chip period, data of A2, B3, and C1 is received, so that data of A2 and the second memory are added, data of B3 and the third memory are added, and data of C1 and the first memory are added. Then, the data of the zeroth memory is read (S15 to S18).

In this manner, the operation is repeatedly performed (S19 to S26).

Here, the cumulative relationship of the data of each path stored in the memory according to the address is shown as a table as follows.

Chip 1 Chip 2 Chip 3 Chip 4 0th memory B0 + A0 + C0 0 B0 B0 + A0 First memory B1 + A1 B1 + A1 + C1 0 B1 Second memory B2 B2 + A2 B2 + A2 + C2 0 Third memory 0 B3 B3 + A3 B3 + A3 + C3

As shown in the table above, when the finger outputs are sequentially selected in the path of the data selection switch, the combiner selects a memory corresponding to the finger outputs from the dequeuing buffer and adds two data to accumulate in the memory.

When all data of each path is accumulated, the data is read from the memory and cleared to zero.

As described in detail above, the present invention has the effect of reducing the hardware burden by reducing the number of dequeuing buffers to compensate the time delay of each path to one.

Claims (2)

A finger for receiving the data received from the antenna and setting the multipath to output channel data; A data selection switch for selectively outputting channel data of the finger; A buffer for storing an output signal of the data selection switch; And a combiner for combining the data stored in the buffer and the data output from the selector switch. Setting and outputting a multipath for the received data; Selectively switching the output data; Storing the switched data; And combining the stored data with the switched data.