KR20040034807A - Method for improving data read and write speed - Google Patents

Abstract

PURPOSE: A method for improving a data read/write speed is provided to reduce delay of data read/write by using an address decoder and a burst cycle between devices that a microprocessor and a data address are fixed by a specified address. CONSTITUTION: The specified address of the device is extended to a predetermined address area by using the address decoder(304). The microprocessor(300) views the specified address like continuous serial addresses by using the microprocessor and the burst cycle between devices. Thus, the specified address is accessed fast. The device that the data address is fixed by the specified address is a data storage such as an FIFO(First Input First Output)(302), an SRAM, a DRAM, or a PCMCIA(Personal Computer Memory Card International Association) card.

Description

Method for improving data read and write speed}

The present invention relates to the processing of data on a board equipped with a microprocessor, and more particularly, to a method of improving data read and write speeds using an address decoder between a microprocessor and a device having a data address fixed to a specific address.

Typically, when data reading and writing is required between the MPC8XX microprocessor and a device such as a First In First Out (FIFO) located at a fixed address, the MPC8XX microprocessor accesses the device by a Chip Select (CS) signal. When reading data continuously or writing data continuously from the device, there is a time delay of about 20 to 22 clocks from one data to the next. This time delay degrades data read and write performance as a whole, which is not efficient when fast data reads and writes between the MPC8XX microprocessor and the device are required.

On the other hand, for a burst transfer support external bus control method using a memory device such as a synchronous dynamic random access memory (SDRAM) rather than a method of directly reading and writing data between the MPC8XX microprocessor and the device, Korean Patent Registration No. 1999-0035394 A burst transmission support external bus controller and method using an MP 860 and an SDA (hereinafter referred to as cited invention) are disclosed. The cited invention relates to the structure of an external bus controller that supports variable length burst transfer of up to 16 bytes that MPC860 can support using the MPC860 microprocessor and SDRAM, and to the MPC860 User Programmable Machine (UPM). Various processor boards that use the system provide maximum transfer bandwidth to the external bus by controlling the SDRAM with bursts on external buses such as PCI and PCMCIA.

Hereinafter, the problems of the prior art will be described with reference to the drawings.

1 is a general data read timing diagram between a conventional MPC8XX microprocessor and a device such as a FIFO in which a data address is fixed to a specific address. When the MPC8XX microprocessor continuously reads a certain amount of data from a 16-bit FIFO with a fixed data address, the time delay between every CS signal from the 50-MHz operating clock to the microprocessor's FIFO is approximately 21 clocks. In other words, multiplying 1 / 50MHz by 21 clocks reduces the overall data read performance to about 420ns, which is not efficient when fast data reads and writes are required. On the other hand, high-speed access may be possible using burst cycles for successive series of addresses.

SUMMARY OF THE INVENTION The present invention provides a method of improving data read and write speeds that can reduce time delays in reading and writing data by using an address decoder and a burst cycle between a microprocessor and a device whose data address is fixed to a specific address. To provide.

1 is a data read timing diagram for explaining a time delay according to the prior art.

2 is a diagram for explaining a board configuration with an MPC8XX microprocessor;

3 is a block diagram of an address decoder for improving data read and write speeds according to an embodiment of the present invention.

4 illustrates an example of assembly source code that supports burst cycles among instructions supported by the MPC8XX microprocessor.

5 is a view for explaining the operation of the device to the assembly source code shown in FIG.

6 is a data read timing diagram according to the inventors' method for improving data read and write speed.

In order to achieve the above object, the method for improving data read and write speed according to the present invention is a method for improving data read and write speed between a microprocessor and a device whose data address is fixed to a specific address. It is desirable to extend the specific address to a certain address area and to make the microprocessor appear to be a continuous series of addresses by using a burst cycle between the microprocessor and the device so that the specific address can be accessed at high speed.

The present invention relates to a device having a data address fixed to a specific address, such as a microprocessor and a FIFO, or a personal computer memory card international association (PCMCIA) card having a data input / output unit for interworking with a host system. The present invention proposes an apparatus and method for efficiently reading and writing data by using burst cycles between microprocessors and these devices in various microprocessor boards. That is, an address decoder circuit is added to a data address of a device in which the data address on the memory-map of the microprocessor board is fixed to a specific address, and the specific address is rapidly accessed using the microprocessor's burst cycle. Make it possible. This address decoder circuit allows one particular address to be accessed to appear to the microprocessor as a contiguous series of addresses, thereby enabling high-speed data reading and writing. Examples of devices in which data addresses of the present invention are fixed to specific addresses include FIFO, SRAM and DRAM, I / O type PCMCIA cards, and the like. Or MPC860.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It is not.

2 is a view for explaining a board configuration equipped with an MPC8XX microprocessor. The MPC8XX microprocessor has been widely applied to various applications in accordance with the trend of accommodating various applications and improving the performance of the microprocessor. The board includes an MPC8XX microprocessor 200 connected to Ethernet and serial ports using Serial Communication Control (SCC), Serial Management Control (SMC), SRAM 202 used as main memory, SDRAM 204, flash ROM 206 for booting function, buffer and controller 208 for matching with PCMCIA interface, PCMCIA Host Bus Adapter (HBA) module 210, data input / output function with external device And a FIFO 212 in charge of the back, a clock unit 214 for providing an operation clock, a power supply unit 216 for supplying operation power, and the like.

3 is a block diagram of an address decoder for improving data read and write speeds according to an embodiment of the present invention.

On the microprocessor board memory map equipped with the MPC8XX microprocessor 300 and the FIFO 302 located at a fixed data address, the address decoder 304 modifies the address area of the FIFO up to 1024 bits (32 bits x 32 registers). ), And read and write to all addresses in the area. For example, if the address of the FIFO is 0x20000000h on the board memory map, 0x20000000h to 0x20000100h is allocated as the address of the FIFO, and the addresses 0x20000000h to 0x20000100h are assigned to the position 0x20000000h, which is actually the data address of the FIFO by the address decoder 304. Is mapped.

4 illustrates an example of assembly source code supporting burst cycles among instructions supported by the MPC8XX microprocessor according to an embodiment of the present invention. Among the assembly instructions of the MPC8XX microprocessor, the load multiple word (lmw) and stmw (store multiple word) instructions that support burst cycles are used to read data in 32-bit (2 word) size units from FIFOs or FIFOs. It is configured to be able to write data to such devices. Reads 32 bits at a time from r3 into burst cycles using 32-bit registers r8 to r31, stores these data in 24 registers from r8 to r31, and then stores these data into r4 32 bits at a time in burst cycles. It will transmit data. This configuration reduces the time lag between device CSs, allowing for more efficient data transfer.

FIG. 5 is a diagram for describing an operation of a device with respect to the assembly source code illustrated in FIG. 4. Read data in burst cycles using the lmw command from the first device 500 having a certain size of data stored therein, and store the data in a certain number of registers 504 obtained, and then store these data in the burst cycles using the stmw command. Write data to the second device 502 to send.

6 is a timing diagram of data read by the method of improving data read and write speed of the present invention. By extending the data address of the FIFO with fixed data address by a certain area, it operates in burst cycles when continuously reading data of a certain size from the 16-bit FIFO, thereby reducing the time delay between CS signals of about 1 to 21 clocks. Decreases by two to three clocks. As a result, when reading and writing data of a certain size between the MPC8XX microprocessor and the device, the overall processing speed can be improved. On the other hand, the degree of data read and write performance improvement depends on the number of registers used.

As described above, the method for improving data read and write speed according to the present invention uses a address decoder between a microprocessor and a device whose data address is fixed to a specific address, and assigns a specific address to a contiguous series of addresses for the microprocessor. By making it visible, it is possible to improve the performance of data read and write processing speed by reducing the time delay between CS signals.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.

Claims (3)

A method of improving data read and write speed between a microprocessor and a device having a data address fixed to a specific address, By using an address decoder, a specific address of the device is extended and secured to a predetermined address area, and by using a burst cycle between the microprocessor and the device, the specific address is shown to the microprocessor as a continuous series of addresses. A method for improving data read and write speed, comprising accessing an address at high speed. The method of claim 1, wherein the device having the data address fixed to a specific address is a data storage device such as a FIFO, an SRAM, a DRAM, or a PCMCIA card. The address decoder of claim 1, wherein the address decoder reads data 32 bits at a time in burst cycles and stores the data in a plurality of 32-bit registers so that a specific address appears to the microprocessor as a series of addresses. To improve data read and write speeds.