KR20040003124A - Delay control circuit controlling the delay of the clock signal outputting from clock buffer in semiconductor memory device - Google Patents

Abstract

PURPOSE: A delay control circuit controlling delay of an output signal being output to an output port of a clock buffer in a semiconductor memory device is provided to give a positive delay and also a negative delay, by referring to a reference signal related with an output port signal. CONSTITUTION: According to the delay control circuit(300) controlling a delay of an output signal being output from an output port of a clock buffer, the first delay circuit(310) is connected to the output port and generates the first delay in the output signal in response to a delay control signal and a number of control signals. A logic circuit(320) outputs a logic signal in response to the delay control signal and the control signals. And the second delay circuit(330) is connected to the output port and generates the second delay in the output signal in response to the logic signal. The first delay circuit is enabled in response to the logic signal of the delay control signal.

Description

Delay control circuit controlling the delay of the clock signal outputting from clock buffer in semiconductor memory device}

The present invention relates to a semiconductor memory device, and more particularly, to a delay control circuit for adjusting a delay amount of an output signal of a clock buffer in a semiconductor memory device.

The semiconductor memory device includes a delayed locked loop (DLL) for synchronizing an inputted external clock signal with an internal clock signal. The clock signal synchronized by this delay synchronization loop is input to a predetermined circuit through which a clock signal is required through a predetermined clock buffer.

The clock buffer amplifies the attenuated signal by placing the clock signal in a necessary part of a path through which the signal is transmitted in order to overcome the attenuation of the signal that is generated through various processes.

FIG. 1 is a diagram schematically illustrating a receiving circuit (circuits 1 to 3) that receives a data clock buffer 100 and buffered clocks CLK1, CLK2, and CLK3 in a semiconductor memory device. The clock buffer 100 includes predetermined buffers 101, 102, 103, 104, and the clock signal CLK_IN input to the clock buffer 100 includes a clock buffer 100 and a predetermined local buffer; Received at circuit 1 through circuit 3 via 110.

Here, in order to ensure correct operation of the semiconductor memory device, the clocks CLK1, CLK2, and CLK3 input to the circuits 1 to 3 must be synchronized. When designing a real semiconductor memory, these clocks are designed to be synchronized.However, when manufacturing a real chip, actual signals are not synchronized due to changes in process, voltage, and temperature (PVT). ps will be different.

After the chip is fabricated, a delay control circuit is used to solve this problem. 2 is a circuit diagram illustrating a delay control circuit 200 controlling a delay amount of a conventional clock buffer output signal.

The delay control circuit 200 of FIG. 2 controls the delay of the output terminal N2 signal of the clock buffer 20, and the delay control circuit 200 includes a plurality of transistors TR21, TR22, TR23, TR24, and a delay element ( C21, C22). The delay elements C21 and C22 use capacitors having a predetermined capacitance.

Referring to FIG. 2, the operation of the conventional delay control circuit 200 will be described below. The delay amount is adjusted by the amount of capacitance that the output terminal N2 sees, depending on whether the signals at the output terminal N2 of the clock buffer 20 are on / off of terminals A, B, C, and D. That is, the delay amount is adjusted by changing a time constant value, which is a measure of the delay amount in the signal.

For example, when both A and B terminals are on, the transistors TR21 and TR22 are both activated so that the output terminal N2 faces the capacitor C21 and the signal is delayed by that amount.

When the terminal A is in an off state, the transistor TR21 does not operate. In this case, the output terminal N2 looks at the small equivalent capacitance of the gate-drain of the transistor TR21. All will have less delay than if they were on.

Similarly, the C and D terminals can be described in the same way, and when A, B, C, and D are all on, the output terminal N2 looks at both capacitors C21 and C22, and they Since they are connected in parallel, they have a delay corresponding to the equivalent capacitance, C21 + C22.

As described above, the conventional delay control circuit 200 shown in FIG. 2 can adjust the delay amount by adjusting terminals A, B, C, and D. However, the conventional delay control circuit 200 can give a positive delay for delaying the signal of the output terminal N2, but cannot provide a negative delay for leading the signal. There was this.

Accordingly, the present invention provides a delay control circuit for controlling a delay amount of an output signal of a clock buffer, in which a negative delay as well as a positive delay is based on a predetermined reference signal associated with an output terminal N2 signal. To provide a delay control circuit that can be given.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

FIG. 1 is a schematic diagram illustrating a reception circuit for receiving a data clock buffer and a buffered clock in a semiconductor memory device.

2 is a circuit diagram illustrating a delay control circuit for controlling a delay amount of a conventional clock buffer output signal.

3 is an embodiment showing a delay control circuit according to the present invention.

4 is a table showing a positive delay amount and a negative delay amount according to combinations of respective control signals in the delay control circuit according to the present invention.

5 is a graph illustrating a simulation result according to a combination of each control signal in the delay control circuit according to the present invention.

One aspect of the present invention for achieving the above technical problem relates to a delay control circuit for controlling the delay of the output signal output to the output terminal of the clock buffer. A delay control circuit according to the present invention includes: a first delay circuit connected to the output terminal and generating a first delay amount in the output signal in response to a predetermined delay control signal and a plurality of control signals; A logic circuit outputting a predetermined logic signal in response to the delay control signal and a plurality of control signals; And a second delay circuit connected to the output terminal and generating a second delay amount in the output signal in response to the logic signal, wherein the first delay circuit is activated in response to a logic signal of the delay control signal. It is characterized by.

Preferably, the first delay circuit includes a switching circuit for receiving the delay control signal to determine whether the first delay circuit operation; A first delay control circuit connected in series with the switching circuit and adjusting the first delay amount in response to the plurality of control signals; And a first delay element connected in series with the first delay control circuit.

Also preferably, the logic circuit may include: a first logic element configured to receive the delay control signal and the first control signal and output a first logic state; And a second logic element configured to receive the delay control signal and the second control signal and output a second logic state, wherein the first logic element and the second logic element are NAND gates.

Also preferably, the second delay circuit may include: a second delay control circuit configured to adjust the second delay amount in response to the first logic state and the second logic state; And a second delay element connected in series with the second delay control circuit.

Another aspect of the present invention for achieving the above technical problem relates to a delay control circuit for controlling a delay of a signal transmitted through a signal transmission line. A delay control circuit according to the present invention is connected to the signal transmission line in response to a first control signal, the first delay circuit for delaying a signal transmitted through the signal transmission line for a predetermined time; and, in response to the second control signal A second delay circuit connected to the signal transmission line and delaying a signal transmitted through the signal transmission line for a predetermined time, wherein a delay amount of a signal transmitted through the signal transmission line is controlled by the first control signal and the second control; It is characterized by the combination of the signal.

Preferably, each of the first delay circuit and the second delay circuit is a capacitor having a predetermined capacitance.

Another aspect of the present invention for solving the technical problem relates to a delay control circuit. A delay control circuit according to the present invention includes a signal transmission line for transmitting a signal; A first delay circuit connected between the first node and a ground power source; A second delay circuit connected between a second node and the ground power source; And a switching circuit for connecting the signal transmission line with the first node and / or the second node in response to a control signal, wherein a delay amount of a signal transmitted through the signal transmission line is determined by the first delay circuit; And / or controlled by the second delay circuit.

Another aspect of the present invention for solving the technical problem relates to a delay control circuit. A delay control circuit according to the present invention includes a signal transmission line for transmitting a signal; A first delay circuit connected between the first node and a ground power source; A second delay circuit connected between a second node and the ground power source; First and second transistors connected in series between the first node and the signal transmission line; And third to fifth transistors connected in series between the second node and the signal transmission line, wherein the first transistor is configured to gate a first gating signal and the fourth transistor to gate the third transistor. And a second gating signal, wherein the second transistor is gated by a combination of the first gating signal and the third gating signal for gating the fifth transistor.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is an embodiment showing a delay control circuit 300 for controlling a positive delay amount and a negative delay amount according to the present invention. The delay control circuit 300 according to FIG. 3 includes a first delay circuit 310, a logic circuit 320, and a second delay circuit 330.

The first delay circuit 310 is connected to the output terminal N3 of the clock buffer 30, the first delay circuit 310 is the switching circuit 311, the first delay control circuit 312 and the first delay element ( C32).

The switching circuit 311 determines whether the first delay circuit 310 operates in response to the delay control signal CONT. In FIG. 3, the switching circuit 311 is implemented with an NMOS transistor TR33 having a delay control signal CONT as a gate input. The first delay control circuit 312 adjusts the first delay amount in response to the plurality of control signals A and B, and is implemented with transistors TR34 and TR35 connected in series in FIG. 3.

The first delay element C32 is connected in series with the first delay control circuit 312, and may be implemented as a capacitor having a predetermined capacitance in FIG. 3. The first delay amount that can be adjusted by the first delay control circuit 312 depends on the magnitude of the capacitance viewed from the output terminal N3 of the clock buffer 30.

The logic circuit 320 includes a first logic element 321 and a second logic element 322. The first logic element 321 and the second logic element 322 may be implemented with a NAND gate. The first logic element 321 receives the delay control signal CONT and the control signal A to receive the first logic signal X having a predetermined logic state (eg, logic 'high' or logic 'low'). The second logic element 322 receives the delay control signal CONT and the control signal B and outputs a second logic signal Y having a predetermined logic state.

The second delay circuit 330 is connected to the output terminal N3 of the clock buffer 30 and generates a second delay amount in response to the first logic signal X and the second logic signal Y. An adjusting circuit 331 and a second delay element C31 are provided.

The second delay control circuit 331 may be implemented with a plurality of series connected transistors TR31 and TR32, and the second delay device C31 may be implemented with a capacitor having a predetermined capacitance.

Referring to Figure 3 describes the operation of the delay control circuit 300 according to the present invention. First, when the delay control signal CONT is logic 'low', the transistor TR33 is activated so that the switching circuit 311 is connected, and the first logic signal X and the second output signal of the logic circuit 320 are the first. The logic state of the logic signal Y becomes logic 'high' regardless of the logic states of the control signals A and B, thereby activating the transistors TR31 and TR32. In this case, the output terminal N3 of the clock buffer 30 faces the second delay element C32.

When the delay control signal CONT and the control signals A and B are both logic 'low' as the reference signal, the logic state of each of the control signals A and B is adjusted to adjust the reference signal for a predetermined time. You can control the amount of delay to delay. That is, when the delay control signal CONT is logic 'low', it corresponds to a case where the delay control signal CONT has a positive delay with respect to the reference signal.

Next, when the delay control signal CONT is logic 'high', the transistor TR33 is inactivated, and thus the switching circuit 311 is disconnected, so that the first delay circuit 310 does not operate. In addition, since the delay control signal CONT is a logic 'high', the first logic signal X and the second logic signal, which are output signals of the logic circuit 320, in accordance with the logic states of the control signals A and B. The logic state of the logic signal Y is determined to determine whether to activate the transistors TR31 and TR32 of the second delay circuit 330.

That is, in this case, when the control signal A is logic 'low' and the control signal B is logic 'high', the first logic signal X, which is an output signal of the logic circuit 320, is logic 'high'. And the second logic signal Y, which is an output signal of the logic circuit 320, becomes a logic 'low'. Thus, transistor TR31 is activated and transistor TR32 is deactivated. At this time, the capacitance seen from the output terminal N3 of the clock buffer 30 becomes the gate-drain capacitance of the transistor TR32, and thus has a negative delay amount that advances the reference signal by a predetermined time.

In addition, when the control signal A is logic 'high', the output signal X of the logic circuit 320 becomes logic 'low' regardless of the logic state of the control signal B, so that the transistor TR31 is inactivated. do. In this case, therefore, the capacitance seen from the output terminal N3 of the clock buffer 30 becomes the gate-drain capacitance of the transistor TR31, and thus a negative delay amount of a predetermined time is also given to the reference signal.

The positive delay amount and the negative delay amount with respect to the reference signal may be adjusted by the sizes of the delay elements C31 and C32 and the transistors TR31, TR32, TR34, and TR35.

That is, according to the present invention, a negative delay amount as well as a positive delay amount can be given to the reference signal corresponding to the output signal of the clock buffer 30 corresponding to the logic state of the delay control signal CONT.

In the embodiment of the present invention shown in Fig. 3, for each component that is activated in response to a logic signal, whether it is activated to logic 'high' or to logic 'low' described in the embodiment of Fig. 3 is seen. It does not act as a constraint on the invention. In other words, each component can be implemented to be activated in a different logic state than shown in the embodiment of the present invention.

4 is a table showing a positive delay amount and a negative delay amount according to combinations of respective control signals in the delay control circuit according to the present invention. In FIG. 4, the delay amount is shown in response to the logic state of the delay control signal CONT and the control signals A and B. In FIG. Herein, a case in which the delay control signal CONT and the control signals A and B are logic 'low' is referred to as a reference signal without delay, and a signal having a positive / negative delay amount is shown as a reference signal.

5 is a graph illustrating a simulation result according to a combination of each control signal in the delay control circuit according to the present invention. FIG. 5 graphically illustrates the delay of the signal in response to the results shown in the table of FIG. 4.

Referring to the table of FIG. 4, a and b of FIG. 5 are cases where the delay control signal CONT has a positive delay amount when the delay control signal CONT is logic 'low', and c and d of FIG. The case where the delay control signal CONT is logic 'high' has a negative delay compared to the reference signal.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the delay control circuit according to the present invention uses a delay control signal CONT to provide a delay control circuit that enables a positive delay and a negative delay to the output signal of the clock buffer, thereby outputting from the clock buffer. The clock signals can be synchronized.

Claims (12)

In the delay control circuit for controlling the delay of the output signal output from the output terminal of the clock buffer, A first delay circuit connected to the output terminal and generating a first delay amount in the output signal in response to a predetermined delay control signal and a plurality of control signals; A logic circuit outputting a predetermined logic signal in response to the delay control signal and a plurality of control signals; And, A second delay circuit connected to the output terminal and generating a second delay amount in the output signal in response to the logic signal, And the first delay circuit is activated in response to a logic signal of the delay control signal. The method of claim 1, wherein the first delay circuit A switching circuit configured to receive the delay control signal and determine whether to operate the first delay circuit; A first delay control circuit connected in series with the switching circuit and adjusting the first delay amount in response to the plurality of control signals; And, And a first delay element connected in series with the first delay control circuit. The method of claim 2, wherein the first delay element A delay control circuit, characterized in that the capacitor having a predetermined capacitance. The method of claim 1, wherein the first delay circuit And a delay control circuit activated when the logic state of the delay control signal is logic 'low'. The logic circuit of claim 1, wherein the logic circuit A first logic element receiving the delay control signal and the first control signal and outputting a first logic state; And, A second logic element configured to receive the delay control signal and the second control signal and output a second logic state; And the first logic element and the second logic element are NAND gates. The method of claim 1, wherein the second delay circuit A second delay control circuit for adjusting the second delay amount in response to the first logic state and the second logic state; And, And a second delay element connected in series with the second delay control circuit. The method of claim 6, wherein the second delay element A delay control circuit, characterized in that the capacitor having a predetermined capacitance. A delay control circuit for controlling a delay of a signal transmitted through a signal transmission line, A first delay circuit connected to the signal transmission line in response to a first control signal, for delaying a signal transmitted through the signal transmission line for a predetermined time; And A second delay circuit connected to the signal transmission line in response to a second control signal, for delaying a signal transmitted through the signal transmission line for a predetermined time; And a delay amount of a signal transmitted through the signal transmission line is adjusted by a combination of the first control signal and the second control signal. The method of claim 8, And each of the first delay circuit and the second delay circuit is a capacitor having a predetermined capacitance. A signal transmission line for transmitting a signal; A first delay circuit connected between the first node and a ground power source; A second delay circuit connected between a second node and the ground power source; And And a switching circuit for connecting the signal transmission line with the first node and / or the second node in response to a control signal. And a delay amount of a signal transmitted through the signal transmission line is controlled by the first delay circuit and / or the second delay circuit. The method of claim 10, And each of the first delay circuit and the second delay circuit is a capacitor having a predetermined capacitance. A signal transmission line for transmitting a signal; A first delay circuit connected between the first node and a ground power source; A second delay circuit connected between a second node and the ground power source; First and second transistors connected in series between the first node and the signal transmission line; And And third through fifth transistors connected in series between the second node and the signal transmission line, The first transistor is gated by a combination of a first gating signal for gating the third transistor and a second gating signal for gating the fourth transistor, And the second transistor is gated by a combination of the first gating signal and a third gating signal for gating the fifth transistor.