KR20030094431A - Apparatus for storing mpeg hd video pc-based - Google Patents

Abstract

PURPOSE: A PC based apparatus for storing MPEG(Moving Picture Experts Group) HD(High Definition) video is provided to simplify a PCI card compressing video signals, safely transmit compressed data to a personal computer in real time, and prevent loss of data generated in a process of transmitting data to peripheral devices. CONSTITUTION: A compressor(110) compresses inputted video signals according to an MPEG standard. A PCI(Peripheral Component Interconnect) interface unit(120) transmits the compressed MPEG video signals through a PCI bus, and generates PCI DMA(Direct Memory Access) interrupt. A DMA buffer unit(210) includes a plurality of buffers storing the video signals inputted through the PCI bus from the PCI interface unit. A control unit(220) reads the video data stored in the DMA buffer unit for transmitting the read video data to a peripheral device(300) based on the PCI DMA interrupt of a video compressing PCI card(100). The control unit calculates fullness degrees of the buffers and controls a compression rate of the video compressing PCI card based on the calculated fullness degrees of the buffers.

Description

PC based MPEG HD video storage device {APPARATUS FOR STORING MPEG HD VIDEO PC-BASED}

The present invention relates to a low-cost PC-based MPEG high-definition (HD) video storage device, and in particular, to simplify the PCI card for compressing a video signal based on MPEG2 I picture by utilizing the signal processing function of a low-cost PC, compressed data (streaming output data) PC-based MPEG HD video storage device that allows secure real-time transmission to the PC and also controls the compression rate according to the buffer's fullness.

In general, digital HDTV has about 6 times higher quality video information than conventional SDTV class. After creating such high quality information, new requirements arise in the process of storing and transmitting this vast information. In the case of storage media, it is necessary to use a general-purpose disk that is easier to access randomly than the tape method. In addition, efforts are underway to enable access via computer networks. Many of these studies are underway with the standardization of digital content archive systems.

On the other hand, if you look briefly about the existing high-definition image storage device, there are analog and digital methods of the conventional high-definition image storage device, all of these methods are using a tape method, the network is difficult and random access, and also, The network of data is difficult.

Recently, the disk-based method is based on a PC and is configured to use a parallel disk processing technology in an uncompressed method. Such a system requires a large number of disks to store high-definition information. Because it is structurally unstable that cannot be delivered to the storage unit stably, it shows unstable operation due to the OS and environment of the actual PC. Accordingly, in the PC-based video storage device, a compression technique is required for more stable transmission.

On the other hand, briefly looking at the development of high-definition video storage device, incorporating image compression technology in the process of storing and transmitting high-definition video information can increase the efficiency of the storage capacity, and the speed of the signal processing unit when processing the compressed signal may be low Advantageous over uncompressed. In addition, a compression method that can be easily thought of as a compression type disk storage device can be configured by using an MPEG transport stream interface card such as DVB-ASI in a broadcast compression device and a PC. It is not practical due to the disadvantage of poor performance due to its disadvantageous structure and high price.

For this reason, the requirements of a low-cost compression recorder are as follows: Compression to be combined with non-broadcast storage, first to consider editing, secondly to minimize picture quality loss, and thirdly to Consideration should be given to ensuring quality of service (QoS) until storage. The compression scheme that satisfies these requirements is MPEG-II, and a variable compression ratio control scheme (VBR) can be adopted to avoid storage loss.

Conventional techniques for storing high-definition video on disk can be divided into two types, one method using parallel storage to receive high-speed, high-capacity video data in real time, and the other method using independent HD video compression. It is a method using the equipment and the interface card, which will be described in detail below.

1 is a configuration diagram of a conventional PC-based uncompressed HD video storage device. Referring to FIG. 1, a conventional PC-based uncompressed HD video storage device includes a streaming interface PCI card 11 and a parallel data storage device 12. The streaming interface PCI card 11 includes a streaming interface unit 11a for receiving an HD video signal and a PCI interface unit 11b for allowing data to be transferred to a PC on a PCI bus. In addition, the parallel data storage device 12 includes a plurality of storage devices in parallel.

This parallel structure can increase the data storage capacity and improve the storage speed. In the case of HD video, the parallel data magnetic field device is essential because the storage speed of the storage device must be very high because the high speed data must be processed. .

However, such a conventional device has a problem that a simple price increase factor due to the number of storage devices in parallel data storage devices and a price increase due to the need for a complex disk parallel operation unit by paralleling the storage device, and also, HD The lack of video compression technology makes it difficult to store large amounts of data on storage media of the same capacity, and no matter how storage devices are placed in parallel, PCI card output signals pass through the system bus of the PC to the storage devices. Therefore, the PC system bus is shared by many resources, so the occupancy of the bus resources available to transfer data from the PCI card to the storage device varies, and data loss may occur depending on the changed state. Currently, this type of equipment depends on the OS and the computer. Therefore, there is a problem that causes anxiety.

2 is a configuration diagram of another conventional PC-based compressed HD video storage device. Referring to FIG. 2, another conventional PC-based compressed HD video storage device uses a HD video compression device. And a streaming interface PCI card 22 and a peripheral device 23. The HD video compression unit 21 is a compressor 21a for compressing based on DCT, VLC, and motion estimation technology according to MPEG standards. The compressor 21a stores the data generated by the compressed data and buffers it so that it can be read out at a constant speed, and the fullness of the VBV unit 21b is read to read the compressed state of the compressor 21a. And a rate control unit 21c for controlling the compression rate. The streaming interface PCI card 22 includes a streaming interface unit 22a for receiving a compressed HD video signal, and a PCI interface unit 22b for transferring the data to a PC via the PCI bus. The peripheral device 23 may include a storage device or a network device or a PC I / O device.

Unlike the prior art described with reference to FIG. 1, the conventional technology receives the slower data because the streaming interface unit receives the compressed video, thereby transmitting data from the PCI card generated in the prior art shown in FIG. Attempts have been made to solve the stability problem of the city.

However, although the data rate from the PCI interface card to the PC is reduced, the speed at which the peripheral device receives the data is also reduced, so this method also has no problem of stably delivering data to the peripheral device.

The present invention not only satisfies the requirements of digital data, disk storage method, and computer network mentioned above, but also compresses in consideration of editing occurring while applying compression technology, minimizes image quality loss, and guarantees QoS (quality of service) to storage. We propose a digital high-definition image storage device having a method.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to simplify a PCI card that compresses a video signal based on MPEG2 I picture by utilizing a signal processing function of a low-cost PC, and compresses data (streaming output data). It is to provide PC-based MPEG HD video storage device that can safely transmit real time to PC and control compression rate according to buffer fullness.

In addition, another object of the present invention is to provide a PC-based MPEG HD video storage device that can prevent data loss caused in the process of data transmission to a peripheral device such as a network or storage device.

1 is a block diagram of a conventional PC-based uncompressed HD video storage device.

2 is a block diagram of another conventional PC-based compressed HD video storage device.

3 is a block diagram of a PC-based MPEG HD video storage device according to the present invention.

4 is a configuration diagram illustrating a PCI interface and a DMA buffer of FIG. 3.

5 is a configuration diagram of the control unit of FIG. 3.

FIG. 6 is a diagram illustrating performance analysis of various buses and I / O channels of FIG. 3.

Explanation of symbols on the main parts of the drawings

100: video compression PCI card 110: compressor

120: PCI interface unit 121: PCI bridge chip

122: PCI master chip 200: computer (PC)

210: DMA buffer unit 220: control unit

221: data transmission unit 222: DMA message management unit

223: buffer fullness calculation unit 224: compression ratio calculation unit

400: peripheral device

In order to achieve the above object of the present invention, the present invention provides a compressor for compressing the input video signal according to the MPEG standard, and transmits the compressed MPEG video signal by the compressor via the PCI bus, and generates a PCI DMA interrupt A video compression PCI card including a PCI interface unit; A DMA buffer unit including a plurality of buffers for storing a video signal input in a DMA manner from a PCI interface unit of the video compression PCI card through a PCI bus, and based on a PCI DMA interrupt from the video compression PCI card. And a computer including a control unit that reads video data stored in a DMA buffer unit and transmits the data to a peripheral device, calculates the buffer's fullness in this process, and controls the compression rate of the video compression PCI card based on the calculation. It provides a PC-based MPEG HD video storage device.

Hereinafter, the configuration and operation of the PC-based MPEG HD video storage device according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings referred to in the present invention, components having substantially the same configuration and function will use the same reference numerals.

The PC-based MPEG HD video storage device of the present invention includes a video compression PCI card (100), a computer (200) and peripheral politics (300).

3 is a block diagram of a PC-based MPEG HD video storage device according to the present invention. Referring to FIG. 3, the video compression PCI card 100 includes a compressor 110 for compressing an input video signal according to MPEG standards. And a PCI interface unit 120 for transmitting the compressed MPEG video signal by the compressor 110 through the PCI bus and generating a PCI DMA interrupt. The compressor 110 compresses an input video signal using only MPEG2 I pictures based on DCT, VLC, and quantization techniques according to the MPEG2 standard.

In addition, the computer 200 includes a DMA buffer unit 210 including a plurality of buffers for storing a video signal input in a DMA manner from the PCI interface unit 120 of the video compression PCI card 100 through the PCI bus. And, based on the PCI DMA interrupt from the video compression PCI card 100, the video data stored in the DMA buffer unit 210 is read and transmitted to the peripheral device, and during this process, the buffer fullness is calculated and And a control unit 300 for controlling the compression rate of the video compression PCI card 100 based on the above.

4 is a configuration diagram of a PCI interface and a DMA buffer of FIG. 3. Referring to FIG. 4, the PCI interface 120 transmits an input MPEG video signal, and a DMA interrupt is generated through the PCI bus. The PCI bridge chip 121 and the PCI master chip 122 for receiving the MPEG video signal from the PCI bridge chip 121 and transmits to the DMA buffer unit 210.

The DMA buffer unit 210 includes a plurality of buffers allocated to a partial area of the main memory of the PC, and the plurality of buffers are configured as ring buffers that perform writing and reading of data while circulating in a ring structure. In addition, the DMA buffer unit 210 operates in a scatter gather mode to efficiently process irregular data output of the compressor 110, and buffers the system bus speed of the PC and the access speed of peripheral devices. To pass data.

FIG. 5 is a block diagram of the controller of FIG. 3. Referring to FIG. 5, the controller 220 receives a data movement permission signal, reads data from the DMA buffer 210, and transmits the data to a peripheral device. When the DMA interrupter is input by the data moving unit 221 and the PCI bridge chip 121 of the PCI interface unit 120, which provides a signal indicating a reading position of the current buffer, the interrupt occurrence frequency is stored. And a DMA message management unit 222 providing a signal indicating a writing position of a current buffer in which data transmitted from the PCI interface unit 120 is transmitted in a DMA manner, and based on a reading position and a writing position signal of the DMA buffer. If one or more buffers among the plurality of buffers of the DMA buffer unit 210 are full, a data movement permission signal is provided to the data movement unit 221, and based on this, the buffer fullness information is provided. A compression ratio is calculated based on the buffer fullness calculator 223 and the buffer fullness information by the buffer fullness calculator 223, and a compression rate control signal including the compression ratio is provided to the compressor 110. It includes a compression ratio calculation unit 224.

The controller 220 controls the compression ratio based on a state in which data is accumulated in the DMA buffer 210 when data is not transmitted to the peripheral device, and interrupts the DMA from the PCI bridge chip 121. Recognizing that data transfer is completed to one DMA buffer unit 210 by the DMA method according to the signal, and controlling the compression rate of the compressor based on this, and the data transfer time from the DMA buffer unit 210 to the peripheral device Determine and control the transmission.

FIG. 6 is a diagram illustrating performance analysis of various buses and I / O channels of FIG. 3.

Operation of the preferred embodiment of the present invention configured as described above will be described in detail below based on the accompanying drawings.

First, the operation of the PC-based MPEG HD video storage device according to the present invention will be described with reference to FIG. 3.

The HD video storage device of the present invention includes a video compression PCI card 100 and a computer (PC). The compressor 110 of the video compression PCI card 100 compresses an input video signal according to MPEG standards. Provided to the PCI interface unit 120, the PCI interface unit 120 transmits the compressed MPEG video signal by the compressor 110 through the PCI bus, and generates a PCI DMA interrupt. The compressor 110 compresses an input video signal using only MPEG2 I pictures based on DCT, VLC, and motion estimation techniques according to the MPEG2 standard.

Thereafter, the DMA buffer unit 210 of the computer (PC) includes a plurality of buffers and receives a plurality of video signals input in a DMA manner from the PCI interface unit 120 of the video compression PCI card 100 through the PCI bus. Store in a buffer. Here, the plurality of buffers are allocated to a part of the main memory of the PC, and the plurality of buffers of the DMA buffer unit 210 perform ringing and writing of data in a ring structure as a ring buffer. . The DMA buffer 210 operates in a scatter gather mode to efficiently process irregular data output of the compressor 110 and buffers the system bus speed of the PC and the access speed of the peripheral device. To pass data.

The control unit 300 of the computer PC reads the video data stored in the DMA buffer 210 based on the PCI DMA interrupt from the video compression PCI card 100 and transmits the video data to the peripheral device. After calculating the fullness of the buffer to control the compression ratio of the video compression PCI card 100 based on this.

The streaming interface unit has a buffer that accepts data in a synchronous method (such as DVB-SSI, DVB-SPI, etc.) or asynchronous method (DVB-ASI) that enters the PCI card and allows the PCI interface to read it. In addition, since the DMA buffer part uses a part of the main memory (hundreds of Mbytes to several Gbytes) of the PC, there is an advantage in that the PCI card can be made inexpensively.

In addition, the control unit 300 may be generally composed of a DSP or a micro process, which allows the compression rate control by the program of the PC to simplify the PCI card and reduce the overall cost. And, unlike the rate control, which allows data to be read from the VBV unit at a simple constant rate, the control unit uses the data rate to accumulate in the DMA buffer if the data is not passed in the process of passing the data to the peripheral device. This function ensures that data is reliably compressed and stored up to peripheral devices.

Referring to FIG. 4, the PCI interface unit 120 will be described in more detail. The PCI bridge chip 121 of the PCI interface unit 120 transmits an input MPEG video signal, and at this time, the DMA through the PCI bus. An interrupt occurs, and the PCI master chip 122 of the PCI interface unit 120 receives the MPEG video signal from the PCI bridge chip 121 and transmits the MPEG video signal to the DMA buffer unit 210.

The DMA buffer unit includes a plurality of buffers in the main memory of the PC. Preferably, the DMA buffer unit includes three or more buffers. For example, the DMA buffer includes three first, second and third buffers. When data is stored in the negative first buffer, data is stored in the second buffer and data is stored in the third buffer. If there are n buffers, the data is stored in the last n buffer. After that, it is a ring buffer structured to store data in the first buffer.

PCI interface method uses DMA method to transfer a lot of data at high speed by efficiently utilizing the PCI bus, and DMA method also has block mode and scatter gather mode. Because it occurs irregularly, it is effective to use the scatter gather mode. In addition, in the PCI bridge, a DMA interrupt occurs to the PCI bus, and this interrupt signal allows the PC to know that data transfer is completed in one DMA buffer by the DMA method, thereby allowing some control. Using this signal, the control unit controls the compression rate and determines whether to transfer data from the DMA buffer unit to the peripheral device.

The configuration of the DMA buffer portion as a ring buffer is divided so that it is difficult to simultaneously write and read the DMA buffer portion and does not conflict with each other. The purpose of configuring three or more ring buffers is to determine the fullness of the buffer by leaving one or more spares in addition to the read and write buffers. Having multiple buffers allows for precise control of compression ratio. The size of the DMA buffer should be such that the performance of the PC's system bus and peripherals changes instantaneously and buffers it to deliver data at the average bus or peripheral access speed. In addition, if the buffer is large, the frequency of interruption will occur frequently. If the frequency of interrupts is high, the compression rate control decision must be made frequently, so precise compression rate control can be performed.

Referring to FIG. 5, the control unit 220 will be described in detail. The data moving unit 221 of the control unit 220 receives a data movement permission signal and reads data from the DMA buffer unit 210 to a peripheral device. In this case, a signal indicating the reading position of the current buffer reading data is provided. The DMA message manager 222 of the controller 220 stores the interrupt occurrence frequency when the DMA interrupt is input from the PCI bridge chip 121 of the PCI interface 120. Provides a signal indicating where to write the current buffer, which is writing data transferred from the DMA system.

The buffer fullness calculator 223 of the controller 220 permits data movement when one or more buffers among the plurality of buffers of the DMA buffer 210 are full based on the read position and the write position signal of the DMA buffer. The signal is provided to the data moving unit 221, and the fullness information of the buffer is provided to the compression rate calculator 224 based on the signal. The compression rate calculator 224 calculates a compression rate based on the buffer fullness information by the buffer fullness calculator 223, and provides a compression rate control signal including the compression rate to the compressor 110. .

The controller 220 controls the compression ratio based on a state in which data is accumulated in the DMA buffer unit 210 when data is not transmitted to the peripheral device.

The control unit 220 recognizes that data transmission is completed to one DMA buffer unit 210 by the DMA method according to the DMA interrupt signal from the PCI bridge chip 121, and controls the compression ratio of the compressor based on this. In addition, the DMA buffer 210 determines the time of data transmission from the peripheral device to control the transmission.

FIG. 6 is a diagram illustrating performance analysis of various buses and I / O channels of FIG. 3. FIG. 6 is a diagram illustrating performance analysis of various buses and I / O channels applied to the present invention.

-HD-SDI video input data rate: 1.2 Gbps

PCI Local Bus: Approx.2.1 Gbps (66 MHz, 32 bit)

PCI bus: 4.2 Gbps (66 MHz, 64 bit)

PC system bus: 17 Gbps (133 MHz, 128 bit)

IDE bus: (several Mbyte / sec ~ tens Mbyte / sec)

Network: (few Mbyte / sec to several tens of Mbyte / sec)

In FIG. 6, the flow of data is moved in the form of a compressor, a PCI bridge, a PCI master, a DMA buffer unit, and a storage device (IDE bus master, => HDD). In this case, as shown in FIG. The slowest flow In the middle, the PC system bus, PCI bus, and local bus are bus structures that use several parts simultaneously, so there is no guarantee that the data flow rate calculated above can be used sufficiently, but the bandwidth is relatively wider than other parts.

According to the present invention as described above, by utilizing a signal processing function of a low-cost PC to simplify the PCI card for compressing the video signal based on the MPEG2 I picture, and to transmit the compressed data (streaming output data) to the PC safely in real time In addition, by controlling the compression rate according to the fullness of the buffer, there is an effect that can prevent the data loss caused during the data transmission process to the peripheral device, such as network or storage device.

The above description is only a description of specific embodiments of the present invention, and the present invention is not limited to these specific embodiments, and various changes and modifications of the configuration are possible from the above-described specific embodiments of the present invention. It will be apparent to those skilled in the art to which the present invention pertains.

Claims (13)

Compressor 110 for compressing the input video signal according to the MPEG standard, and PCI interface unit 120 for transmitting the compressed MPEG video signal by the compressor 110 through the PCI bus, and generates a PCI DMA interrupt A video compression PCI card 100 including; A DMA buffer unit 210 including a plurality of buffers for storing a video signal input in a DMA manner from the PCI interface unit 120 of the video compression PCI card 100 through the PCI bus, and the video compression PCI card ( Based on the PCI DMA interrupt from the 100, the video data stored in the DMA buffer unit 210 is read and transmitted to the peripheral device. In this process, the fullness of the buffer is calculated and then the video compression PCI card ( PC-based MPEG HD video storage device characterized in that it comprises a computer (200) including a control unit (300) for controlling the compression rate of the 100. The method of claim 1, wherein the PCI interface unit 120 A PCI bridge chip 121 that transmits an input MPEG video signal and generates DMA interrupts through the PCI bus; And a PCI master chip (122) for receiving the MPEG video signal from the PCI bridge chip (121) and transmitting the MPEG video signal to the DMA buffer (210). The method of claim 1, wherein the DMA buffer unit 210 PC-based MPEG HD video storage device comprising a plurality of buffers allocated to a portion of the main memory of the PC. The method of claim 3, wherein the DMA buffer unit 210 PC-based MPEG HD video storage device, characterized in that to operate in a scatter gather mode to efficiently process the irregular data output of the compressor (110). The method of claim 1, wherein the control unit 220 In response to the DMA interrupt signal from the PCI bridge chip 212, it is recognized that the data transfer is completed to one DMA buffer unit 210 by the DMA method, and based on the control of the compression rate of the compressor, the DMA buffer unit PC-based MPEG HD video storage device, characterized in that for determining the data transfer time to the peripheral device at 210. The method of claim 1, wherein the control unit 220 A data moving unit 221 which receives a data movement permission signal and reads data from the DMA buffer unit 210 and transmits the data to a peripheral device, and provides a signal indicating a reading position of a current buffer reading data; When the DMA interrupter is input by the PCI bridge chip 121 of the PCI interface unit 120, the interrupt occurrence frequency is stored, and a position of writing a current buffer that writes data transmitted from the PCI interface unit 120 in the DMA manner. A DMA message manager 222 for providing a signal informing of the failure; The data movement permission signal is provided to the data movement unit 221 when one or more buffers among the plurality of buffers of the DMA buffer unit 210 are full based on the read position and the write position signal of the DMA buffer. A buffer fullness calculator 223 for providing fullness information of the buffer; And a compression rate calculation unit 224 that calculates a compression rate based on the buffer fullness information by the buffer fullness calculation unit 223 and provides a compression rate control signal including the compression rate to the compressor 110. PC based MPEG HD video storage. Compressor 110 for compressing the input video signal to the MPEG2 I picture only according to the MPEG standard, and transmits the compressed MPEG video signal by the compressor 110 through the PCI bus, and generates a PCI DMA interrupt A video compression PCI card 100 including a PCI interface unit 120; And a plurality of buffers for storing video signals input in a DMA manner from the PCI interface unit 120 of the video compression PCI card 100 through a PCI bus, and the plurality of buffers have a ring structure for writing and reading data. Peripheral device that reads the video data stored in the DMA buffer unit 210 based on the DMA buffer unit 210 implemented as a ring buffer to perform a circular loop and the PCI DMA interrupt from the video compression PCI card 100. And a computer (200) including a control unit (300) for controlling the compression rate of the video compression PCI card (100) based on the calculation of the fullness of the buffer in this process. Based MPEG HD Video Storage. The method of claim 7, wherein the PCI interface unit 120 is A PCI bridge chip 121 that transmits an input MPEG video signal and generates DMA interrupts through the PCI bus; And a PCI master chip (122) for receiving the MPEG video signal from the PCI bridge chip (121) and transmitting the MPEG video signal to the DMA buffer unit (210). The method of claim 7, wherein the DMA buffer unit 210 PC-based MPEG HD video storage device comprising a plurality of buffers allocated to a portion of the main memory of the PC. The method of claim 9, wherein the DMA buffer unit 210 PC-based MPEG HD video storage device, characterized in that to operate in a scatter gather mode to efficiently process the irregular data output of the compressor (110). The method of claim 7, wherein the control unit 220 In response to the DMA interrupt signal from the PCI bridge chip 121, it recognizes that data transfer is completed to one DMA buffer unit 210 by the DMA method, and controls the compression ratio of the compressor based on the DMA buffer unit. PC-based MPEG HD video storage device, characterized in that for determining the data transfer time to the peripheral device at 210. The method of claim 7, wherein the control unit 220 A data moving unit 221 which receives a data movement permission signal and reads data from the DMA buffer unit 210 and transmits the data to a peripheral device, and provides a signal indicating a reading position of a current buffer reading data; When the DMA interrupter is input by the PCI bridge chip 121 of the PCI interface unit 120, the interrupt occurrence frequency is stored, and a position of writing a current buffer that writes data transmitted from the PCI interface unit 120 in the DMA manner. A DMA message manager 222 for providing a signal informing of the failure; The data movement permission signal is provided to the data movement unit 221 when one or more buffers among the plurality of buffers of the DMA buffer unit 210 are full based on the read position and the write position signal of the DMA buffer. A buffer fullness calculator 223 for providing fullness information of the buffer; And a compression rate calculation unit 224 that calculates a compression rate based on the buffer fullness information by the buffer fullness calculation unit 223 and provides a compression rate control signal including the compression rate to the compressor 110. PC based MPEG HD video storage. Compressor 110 for compressing the input video signal to the MPEG2 I picture only according to the MPEG standard, and transmits the compressed MPEG video signal by the compressor 110 through the PCI bus, and generates a PCI DMA interrupt And a PCI interface unit 120, wherein the PCI interface unit 120 transmits an input MPEG video signal, and at this time, a PCI bridge chip 121 in which a DMA interrupt occurs through the PCI bus, and the PCI bridge A video compression PCI card 100 including a PCI master chip 122 for receiving an MPEG video signal from a chip 121 and transmitting the MPEG video signal to the DMA buffer 210; And a plurality of buffers for storing a video signal input in a DMA manner from the PCI interface unit 120 of the video compression PCI card 100 through a PCI bus, wherein the plurality of buffers are part of the main memory of the PC. A plurality of buffers allocated to the DMA buffer unit 210 implemented as a ring buffer which performs a write and read of data while circulating in a ring structure; A data moving unit 221 receiving a data movement permission signal and reading data from the DMA buffer unit 210 and transmitting the data to a peripheral device, wherein a data moving unit 221 provides a signal indicating a reading position of a current buffer reading data; When the DMA interrupter is input by the PCI bridge chip 121 of the PCI interface unit 120, the interrupt occurrence frequency is stored, and the writing position of the current buffer that writes data transmitted from the PCI interface unit 120 in the DMA manner is written. A DMA message management unit 222 which provides an informing signal and a data movement permission signal when one or more buffers of the plurality of buffers of the DMA buffer unit 210 are full based on a read position and a write position signal of the DMA buffer. Is provided to the data moving unit 221 and based on the buffer fullness calculator 223 and the buffer fullness calculator 223 for providing buffer fullness information. And a control unit (300) including a compression rate calculation unit (224) for calculating a compression rate based on the fur fullness information and providing a compression rate control signal including the compression rate to the compressor (110). Based MPEG HD Video Storage.