KR20030091425A - Apparatus of wireless data communication - Google Patents

Abstract

PURPOSE: A wireless data communication device is provided to prevent wiretapping by encoding data when transmitting the data from a host CPU to a wireless interface unit. CONSTITUTION: A wireless interface unit(200) is composed between a host CPU(11) and a wireless signal processing unit(16) for converting a data format and performing a real-time process necessary for the wireless signal processing unit(16). An encoding block is composed between the host CPU(11) and the wireless interface unit(200). The encoding block encodes data when the data are transmitted from the host CPU(11) to the wireless interface unit(200) so that the data are not decoded without exchanging a normal key in the outside.

Description

Wireless data communication device {APPARATUS OF WIRELESS DATA COMMUNICATION}

The present invention relates to a wireless data communication device, and more particularly, to a wireless data communication device serving as a bridge to connect two or more Ethernet networks.

1 is a block diagram showing a wireless data communication device for connecting a general Ethernet network, Figure 2 is a detailed block diagram showing a wireless data communication device of the prior art.

As shown, the wireless data communication device according to the prior art serves as a bridge connecting two or more Ethernet networks, including the memory 10, 14, the host CPU 11, the Ethernet MAC 12, Ethernet connection section 13, wireless LAN MAC (15), and wireless signal processing section (16).

The memory 10 stores data to be transmitted and received (TX / RX) wirelessly with Ethernet. The host CPU 11 bridges data coming into the Ethernet and wirelessly, and is in charge of a wireless protocol. The Ethernet MAC 12 is in charge of the Ethernet protocol. The Ethernet connection 13 is a part that is physically connected to the Ethernet. The WLAN MAC 15 and the wireless signal processor 16 are physically wirelessly connected.

However, the conventional communication apparatus configured as described above has a complicated structure such as a wireless LAN MAC, which leads to a decrease in productivity, an increase in cost, a decrease in data communication speed, and eavesdropping.

Accordingly, the present invention is to solve the above-mentioned conventional problems, in the wireless data communication device that serves as a bridge to connect two or more Ethernet networks, by simplifying the structure to improve productivity and reduce costs, An object of the present invention is to provide a wireless data communication device that improves communication speed and prevents eavesdropping.

1 is a block diagram illustrating a wireless data communication device connecting a general Ethernet network.

2 is a detailed block diagram showing a wireless data communication apparatus of the prior art.

3 is a block diagram showing a wireless data communication apparatus according to the present invention.

4 is a detailed block diagram illustrating a wireless I / F (interface) unit of FIG. 3;

5 is a block diagram showing a wireless data communication device with an encryption function according to the present invention.

6 and 7 are block diagrams illustrating a wireless data communication device having a repeater function according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: memory 11: host CPU

12: Ethernet MAC 13: Ethernet connection

16, 400: wireless signal processing unit 200, 500: wireless I / F unit

201: transmission length register 202: reception length register

203: transmit buffer register 204: receive buffer register

205: transmit shift register 206: receive shift register

207: transmission counter 208: reception counter

209, 214: comparator 210, 215: CRC32 shift register

211: transmit interrupt generator 212: wireless header decoder

213: transmit / receive power enable controller 300: encryption block

A wireless data communication apparatus according to the present invention for achieving the above object, a memory for storing data to be transmitted and received wirelessly with Ethernet, a host CPU bridging data coming into the Ethernet and wireless, and responsible for the wireless protocol, Ethernet A communication device comprising an Ethernet MAC in charge of a protocol, an Ethernet connection part physically connected to Ethernet, and a wireless signal processing part physically connected wirelessly, converts a data format between the host CPU and the wireless signal processing part. Characterized in that it further comprises a wireless I / F (interface) for real-time processing required by the wireless signal processing unit.

The wireless I / F unit includes: a transmission length register connected to the host CPU and transmitting wireless data by a value stored in the register; A transmit buffer register coupled to the host CPU and storing data to be transmitted; A transmission shift register for converting data in the transmission buffer register, which is parallel data, into serial data for wireless transmission; A transmission counter coupled to the transmission shift register to count up data transmitted; A comparator for comparing the data length stored in the transmission length register with the transmission counter and transmitting an output signal when the transmission is the same, indicating that the transmission is completed; A transmission interrupt generator which receives a signal indicating that the transmission is completed from the comparator and informs the host CPU; A transmission means comprising a CRC32 shift register for feeding back the output data of the transmission shift register and calculating the CRC32 to add to the CRC32 field of data in order to see the integrity of the data when transmitting, and connected to the host CPU. A reception length register for receiving radio data by a value stored in a register, wherein a length field stored in a header of the radio data is copied; A reception shift register for converting serially received serial data into parallel data; A receive buffer register for storing data received by the receive shift register and coupled to the host CPU; A wireless header decoder coupled to the receive buffer register and analyzing the header of data upon receipt to notify the host CPU when the data is on it and copying a length field in the header to the receive length register; A reception counter for counting up data received by the reception shift register; A comparator for comparing the data length stored in the reception length register with the reception counter when receiving the same and outputting an output signal to indicate completion of reception; Receiving means comprising a CRC32 shift register for calculating CRC32 to add to the CRC32 field of data to see defects of data received by the receiving shift register, and transmitting / receiving for operating the receiving means when receiving a transmitting means when transmitting. And a power enable controller.

The apparatus further includes an encryption block for encrypting data between the host CPU and the wireless I / F unit, and encrypts the data when the host CPU passes from the host CPU to the wireless I / F unit. It is impossible to decrypt the data without exchange.

The apparatus may further include a wireless signal processor that is physically wirelessly connected to another Ethernet network, and another wireless I / F unit that converts a data format between the host CPU and the wireless signal processor and performs real time processing required by the wireless signal processor. Thus, if the distance between Ethernet networks is too far, it operates as a repeater structure in the middle.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a wireless data communication apparatus according to the present invention.

As shown, the present invention is a conventional communication apparatus comprising a memory 10, a host CPU 11, an Ethernet MAC 12, an Ethernet connection portion 13, and a radio signal processor 16, A wireless I / F unit 200 is further provided between the host CPU 11 and the wireless signal processor 16. The wireless I / F unit 200 converts the data format between the host CPU 11 and the wireless signal processor 16 and performs real time processing required by the wireless signal processor 16.

FIG. 4 is a detailed block diagram showing the wireless I / F unit of FIG. 3. As shown, the transmission means includes a transmission length register 201, a transmission buffer register 203, a transmission shift register 205, and a transmission counter 207. FIG. ), A comparator 209, a transmission interrupt generator 211, and a CRC32 shift register 210. The reception means includes a reception length register 202, a reception shift register 206, a reception buffer register 204, and a radio. The header decoder 212, the reception counter 208, the comparator 214, and the CRC32 shift register 215 are provided, and the transmission / reception power enable controller 213 which operates the reception means when receiving a transmission means at the time of transmission, respectively. ) Is included.

The transmit length register 201 is connected to the host CPU 11 and transmits wireless data by the value stored in the register, and the transmit buffer register 203 is connected to the host CPU 11 and transmits data to be transmitted. keep it.

The transmission shift register 205 converts data in the transmission buffer register 203 which is parallel data into serial data for wireless transmission, and the transmission counter 207 is connected to the transmission shift register 205 and transmitted data. To count up.

The comparator 209 compares the data length stored in the transmission length register 201 with the transmission counter 207 when transmitting, and outputs an output signal to indicate that the transmission is completed.

The transmission interrupt generator 211 receives a signal indicating that the transmission is completed from the comparator 209 and notifies the host CPU 11, and the CRC32 shift register 210 feeds back output data of the transmission shift register 205. In order to see data defects when transmitting, CRC32 is calculated and added to the CRC32 field of the data.

Meanwhile, in the above, the reception length register 202 is connected to the host CPU 11 and receives radio data by the value stored in the register, and the length field stored in the header of the radio data is copied.

A receive shift register 206 converts serially received serial data into parallel data, and a receive buffer register 204 stores data received by the receive shift register 206 and is connected to the host CPU 11. .

The wireless header decoder 212 is connected to the reception buffer register 204 and analyzes the header of the data when receiving and informs the host CPU 11 when the data is on it, and indicates the length field in the header to the reception length register. Copy to (202).

The reception counter 208 counts up the data received by the reception shift register 206, and the comparator 214 compares the data length stored in the reception length register 202 with the reception counter 208 when receiving. If it is the same, an output signal is sent to indicate that reception is complete.

The CRC32 shift register 215 calculates and adds the CRC32 to the CRC32 field of the data in order to see defects of the data received by the reception shift register 206.

5 is a block diagram illustrating a wireless data communication device to which an encryption function is added according to the present invention.

As shown, the present invention provides a memory 10, a host CPU 11, an Ethernet MAC 12, an Ethernet connection unit 13, a wireless signal processor 16, a wireless I / F unit 200 In the communication device consisting of a), the encryption block 300 is further provided between the host CPU 11 and the wireless I / F unit 200. The encryption block 300 encrypts data between the host CPU 11 and the wireless I / F unit 200.

6 and 7 are block diagrams illustrating a wireless data communication apparatus to which a repeater function is added according to the present invention.

As shown, the present invention converts the data format between the wireless signal processor 400 and the host CPU 11 and the wireless signal processor 400 that is physically wirelessly connected to another Ethernet network, the wireless signal In addition, the processor 400 further includes another wireless I / F unit 500 for real-time processing required by the processor 400 to operate in a repeater structure in the middle when the distance between Ethernet networks is too long.

Referring to the operation of the present invention configured as described above is as follows.

The communication device of the present invention serves as a bridge connecting two or more Ethernet networks (where communication devices A and B have the same structure).

First, when data is transmitted from the Ethernet network A to the Ethernet network B, the Ethernet connection unit 13 of the communication device A receives and processes the data in the Ethernet MAC 12 and hands it over to the host CPU 11. The host CPU 11 stores the data in the memory 10 and passes the data to the wireless signal processing unit 16 through the wireless I / F unit 200 to transmit the data wirelessly.

Then, the radio signal processor 16 of the communication device B receives the radio signal and passes it to the radio I / F unit 200. The radio I / F unit 200 analyzes this and passes it to the host CPU 11. Judge. Once the data passed to the host CPU 11 is stored in the memory 10, the data is transferred to the Ethernet network B through the Ethernet MAC (12) and transferred to the Ethernet network B. At this time, data transmission between the communication device A and the communication device B is performed by the protocol of the present invention.

Referring to FIG. 4, the operation of the wireless I / F unit 200 will be described in more detail. First, when transmitting data, the transmission length register 201 is connected to the host CPU 11 and is connected to the register. The wireless data is transmitted by the stored value, and the transmission buffer register 203 is connected to the host CPU 11 and stores data to be transmitted. The transmission shift register 205 converts data in the transmission buffer register 203 which is parallel data into serial data for wireless transmission, and the transmission counter 207 is connected to the transmission shift register 205 and transmitted data. To count up. Thereafter, when the comparator 209 transmits and compares the data length stored in the transmission length register 201 with the transmission counter 207, the comparator 209 sends an output signal to indicate that the transmission is completed, and the transmission interrupt generator 211 Receives a signal from the comparator 209 indicating that the transmission is complete, and informs the host CPU 11, CRC32 shift register 210 feeds back the output data of the transmission shift register 205, when the data is defective To see this, calculate CRC32 and add it to the CRC32 field of the data.

On the other hand, when receiving data, the reception length register 202 is connected to the host CPU 11 and receives radio data by the value stored in the register, and the length field stored in the header of the radio data is copied. A receive shift register 206 converts serially received serial data into parallel data, and a receive buffer register 204 stores data received by the receive shift register 206 and is connected to the host CPU 11. . Thereafter, the wireless header decoder 212 is connected to the reception buffer register 204 and analyzes the header of the data when receiving and notifies the host CPU 11 when the data comes to itself, and receives the length field in the header. Copy to length register 202. The reception counter 208 counts up the data received by the reception shift register 206, and the comparator 214 compares the data length stored in the reception length register 202 with the reception counter 208 when receiving. In this case, the output signal is sent to indicate that the reception is completed, and the CRC32 shift register 215 calculates the CRC32 and adds the CRC32 to the CRC32 field of the data to see the defect of the data received by the reception shift register 206.

Therefore, when the present communication device is used, when the same modulation method is used at the same frequency than the existing device, a transmission capacity of about 80% or more can be obtained. The reason is the overhead reduction due to the simplification of the protocol.

In addition, as shown in FIG. 5, when an encryption block 300 is added, data is encrypted when data is transferred from the host CPU 11 to the wireless I / F unit 200, so that a normal key exchange is performed outside the apparatus. Without it, the data cannot be decrypted. Therefore, the conventional security problem is solved.

6 and 7, when the distance between Ethernet networks is too far, the repeater structure may be operated in the middle.

That is, as shown in FIG. 7, when wireless data is received through the wireless signal processing unit A 16, the wireless data is transferred to the wireless I / F unit A 200. The wireless I / F unit 200 analyzes this data and determines whether to pass it to the host CPU 11. The data once passed to the host CPU 11 is stored in the volatile memory 10. The host CPU 11 analyzes this data to determine whether to transfer data over Ethernet or wirelessly. In order to transmit data through Ethernet, the data is transmitted to the Ethernet MAC 12 and the data is transmitted to the Ethernet through the Ethernet connection 13. To transmit data wirelessly, the data is transferred to the wireless I / F unit B 500 and the data is wirelessly transmitted through the wireless signal processor B 400. On the other hand, when receiving the wireless data through the wireless signal processor B (400) may be reversed from the above case.

Therefore, as shown in FIG. 6, if the distance between the Ethernet network A and the Ethernet network C is too far, it is possible to easily solve the distance problem by using the repeater structure communication device in the middle. It is possible to connect to networks A and C.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described embodiments without departing from the spirit of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and such modifications are intended to fall within the scope of the appended claims.

As described above, according to the wireless data communication device according to the present invention, in the wireless data communication device serving as a bridge to connect two or more Ethernet networks, the structure is simplified to improve productivity and reduce costs, Data communication speed is improved due to the overhead reduction due to the simplification, and data is encrypted when the data is transferred from the host CPU to the wireless I / F part, so that the data cannot be decrypted without the normal key exchange outside the device. There are various effects to prevent.

Claims (4)

A memory 10 for storing data to be transmitted and received wirelessly with Ethernet, a host CPU 11 for bridging data coming into the Ethernet and wireless, and responsible for a wireless protocol, an Ethernet MAC 12 for an Ethernet protocol, In the communication device consisting of an Ethernet connection 13 which is physically connected to Ethernet, and a wireless signal processor 16 which is physically wirelessly connected, It further comprises a wireless I / F unit 200 for converting the data format between the host CPU 11 and the radio signal processor 16, and performs the real-time processing required by the radio signal processor 16. Wireless data communication device. According to claim 1, wherein the wireless I / F unit 200 A transmission length register 201 connected to the host CPU 11 and transmitting wireless data by a value stored in this register; A transmission buffer register (203) connected to the host CPU (11) and storing data to be transmitted; A transmission shift register 205 for converting data in the transmission buffer register 203 which is parallel data into serial data for wireless transmission; A transmission counter (207) coupled to the transmission shift register (205) for counting up transmitted data; A comparator 209 for comparing the data length stored in the transmission length register 201 with the transmission counter 207 when transmitting and outputting an output signal to indicate that the transmission is completed; A transmission interrupt generator 211 which receives a signal indicating that the transmission is completed from the comparator 209 and informs the host CPU 11; Transmission means configured to feed back the output data of the transmission shift register (205) and calculate a CRC32 to add to the CRC32 field of data in order to see the defect of the data when transmitting; A reception length register (202) connected to the host CPU (11) to receive wireless data by a value stored in this register, and copying a length field stored in a header of the wireless data; A reception shift register 206 for converting serially received serial data into parallel data; A receive buffer register (204) for storing data received by the receive shift register (206) and coupled to the host CPU (11); A radio connected to the reception buffer register 204 and analyzing the header of the data when receiving and informing the host CPU 11 when the data came to itself, and copying a length field in the header to the receiving length register 202. Header decoder 212; A reception counter (208) for counting up data received by the reception shift register (206); A comparator (214) indicating that the reception is completed by sending an output signal if the data length stored in the reception length register (202) and the reception counter (208) are equal when received; Receiving means composed of a CRC32 shift register (215) for calculating a CRC32 and adding it to a CRC32 field of data in order to view defects of data received by the reception shift register (206); And And a transmit / receive power enable controller (213) for operating the receiving means when receiving the transmitting means when transmitting. The method of claim 1, Further comprising an encryption block 300 for encrypting data between the host CPU 11 and the wireless I / F unit 200, the data from the host CPU 11 to the wireless I / F unit 200 A wireless data communication device, characterized in that the data is encrypted so that it cannot be decrypted without a normal key exchange outside the device. The method of claim 1, It converts the data format between the wireless signal processor 400 and the host CPU 11 and the wireless signal processor 400 that are physically wirelessly connected to another Ethernet network, and performs the real time processing required by the wireless signal processor 400. Further comprising another wireless I / F unit 500, the wireless data communication device, characterized in that to operate in a repeater structure in the middle when the distance between the Ethernet network is too far.