KR20030087835A - Dram using aligned soi double gate transistor and process thereof - Google Patents

Abstract

PURPOSE: A DRAM(Dynamic Random Access Memory) using a self aligned SOI(Silicon-On-Insulator) double gate transistor and a method for manufacturing the same are provided to be capable of solving the problems such as DIBL(Drain Induced Barrier Lowering) phenomenon, the increase of channel resistance, the increase of gate resistance, and junction leakage current. CONSTITUTION: After forming a double gate at the upper portion of a substrate, a cell is formed by forming a source/drain for CMOS(Complementary Metal Oxide Semiconductor) at the peripheral region of the double gate. Then, a direct contact and a buried contact(161) of the cell, are formed at the resultant structure. A metal contact is formed on the direct and buried contact.

Description

DRAM using magnetic array S.O.I double gate transistor and method of manufacturing the same {DRAM USING ALIGNED SOI DOUBLE GATE TRANSISTOR AND PROCESS THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor fabrication and relates to integrated circuits having design rules of sub 100 nm. In particular, the present invention is for manufacturing a DRAM to form a self aligned double gate using a silicon on insulator wafer (SOI wafer), and source / drain (SEG) using a selective epitaxial growth (SEG) and a method of manufacturing the same.

Conventional planar type transistors reduce drain lengths (DIBLs) due to high integration as channel lengths are reduced to less than 100 nm, increased channel resistance, increased gate resistance, and junction leakage. Problems such as junction leakage current have occurred and the limit has been reached. Therefore, in order to solve this problem, a double gate type transistor in which a gate passes up and down with a channel in between is being developed.

These development efforts have been reported continuously, Device Scaling Limits of Si MOSFETs and Their Application Dependencies p259, Proceedings of IEEE, vol. 89, no. 3 , 2001) ", the bottom and top gates are not self-aligning and require additional space to open the seed Si, which prevents integration. Hon-Sup Philip Wong's "Novel Device Options for Sub-100nm CMOS IEDM Short Course, 1999" shows that the bottom and top gates are self-aligned, The gate region is formed by wet etch, which is not suitable for use in the nano-scale integration process.The difference in oxidation rate and selective epitaxy of JH Lee Super Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy (IEDM, p71, 1999) "discloses the concept of double gate formation, but is limited to unit cells. Will be.

SUMMARY In order to solve the problems of the conventional planar MOS transistor, the present invention provides a semiconductor DRAM and a method of manufacturing the same, which solve DIBL, channel resistance, gate resistance, junction leakage current.

Another object of the present invention is to provide a method for manufacturing a DRAM that can be applied without changing a mask for manufacturing a conventional DRAM.

It is still another object of the present invention to provide a DRAM manufacturing method capable of omitting a well formation process, which is a characteristic of an SOI process, and thus omitting a photo and ion implantation process.

In order to achieve the above object, the present invention provides a DRAM manufacturing process using a self-aligned SOI double gate transistor, wherein the semiconductor DRAM comprises: forming a double gate on a substrate; Forming a source / drain for CMOS in a peripheral area on the substrate on which the double gate is formed; Forming a direct contact (DC) and a buried contact (BC) of the cell; Forming a metal contact, wherein the forming a double gate on the substrate comprises buried oxide, SOI wafer, bottom gate oxide, poly-Si, WSi and CVD oxide on top of the bulk Si. Stacking sequentially; Forming a thermal oxide film on a support handle wafer, bonding it to the top of the SOI wafer, and removing the bulk Si and buried oxide film; Photographic and etching steps defining the active area; Sequentially depositing a gate oxide film, poly-Si, WSi, and SiN layers with a top gate material on the back side of the support handle wafer; Etching side surfaces of the stacked top gate, channel and bottom gate, and then oxidizing gate material and channel; Growing an SEG with seed of the oxidized exposed channel sidewalls, and then depositing a CVD oxide film under the SEG, and performing etch-back, wherein the double gate formed substrate is formed. In the process of forming a source / drain for the CMOS in the peripheral region, a SiN spacer is deposited on the double gate-formed DRAM, the SiN is etched to open only the peripheral NMOS region, and then ions are implanted. Making a step; Seeding the exposed SEG layer for secondary SEG growth, thereafter implanting an ion implant, and then depositing a CVD oxide film; Forming a peripheral PMOS region in the same manner as the opening, implantation, secondary SEG, ion implantation, and CVD oxide deposition steps, including direct contact (DC) and investment contact (BC) Forming a buried contact comprises: etching a SiN spacer and a CVD oxide film formed in the peripheral CMOS source / drain formation process to open a self-aligned contact (SAC); Performing ion implantation for contact plugs in said open area; Depositing poly-Si and performing etch-back or CMP, wherein forming a metal contact comprises separating a portion to be contact for the gate; Top and bottom gates of a double gate are simultaneously connected to a metal, and a source / drain of an active region is also connected together.

1 is a thin film stack structure for forming a CVD oxide deposited DRAM according to an embodiment of the present invention.

FIG. 2 is a thin film stacked structure diagram of a DRAM having a single crystal Si layer exposed after being attached to an upper surface of the wafer of FIG. 1 according to an exemplary embodiment of the present invention. FIG.

3A is a thin film stack structure diagram of a DRAM on the side of a gate line illustrating the formation of a top gate stack in accordance with one preferred embodiment of the present invention.

3B is a thin film stack structure diagram of a DRAM on the side of an active region illustrating the formation of a top gate stack in accordance with one preferred embodiment of the present invention.

4 is a comparative planar structure diagram of an active region used in a conventional DRAM manufacturing process and an active region of a DRAM according to a preferred embodiment of the present invention.

5 is a thin film stack structure of a DRAM after a photo and dry etching process according to an embodiment of the present invention.

FIG. 6 is a thin film stacked structure diagram of a DRAM in which wet etching is performed according to an exemplary embodiment of the present invention. FIG.

7 is a planar structure diagram of a DRAM after growing an SEG with the sidewalls of the channel as a seed according to a preferred embodiment of the present invention.

8 is a cross-sectional view taken along the line AA ′ of FIG. 7;

9 is a thin film laminated structure diagram of a DRAM having CVD oxide film deposition according to an embodiment of the present invention.

FIG. 10 is a thin film stack structured structure of a post-etched DRAM according to an exemplary embodiment of the present invention. FIG.

FIG. 11 is a thin film stack structure diagram of a DRAM on which a SiN layer is grown according to an exemplary embodiment of the present invention. FIG.

12 is a thin film stack structure diagram of a DRAM having SEG grown according to an embodiment of the present invention.

FIG. 13 is a thin film stack structure diagram of a DRAM including a connection metal having a wide window according to a preferred embodiment of the present invention. FIG.

FIG. 14 is a thin film stack structure diagram of a DRAM showing opening of self-aligned contacts to form DC and BC of a cell in accordance with a preferred embodiment of the present invention. FIG.

15 is a cross-sectional view taken along the line A-A 'of FIG.

16 is a thin film stack structure of a DRAM of the completed form according to an embodiment of the present invention.

Fig. 17 is a thin film lamination structure diagram of a DRAM in which a conventional gate contact portion is connected.

FIG. 18 is a thin film stacked structure diagram of a DRAM in which a contact is formed in accordance with a preferred embodiment of the present invention. FIG.

19 is a thin film stacked structure diagram of a DRAM having a conventional gate line formed therein;

20 is a thin film stack structure of DRAM in which only the top gate is anisotropically etched so that the top gate and the bottom gate are in contact simultaneously.

<Description of Major Symbols in Drawing>

101: bulk Si (blk Si) 102: buried oxide

103: SOI

104: bottom gate oxide

105: poly-Si 106: WSi

107 CVD oxide film 201 support handle wafer

301: SiN302: Top Gate Material WSi

303: Top gate material poly-Si304: Top gate oxide

701: primary SEG901: deposited CVD oxide film

111: deposited SiN spacer 121: secondary SEG

131: contact metal 181: metal contact

161: Poly-Si deposited for DC and BC formation of cells

Hereinafter, described in detail with reference to the accompanying drawings of the present invention. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used for the same components, even if displayed on different drawings. In addition, the detailed description is omitted if it is determined that the gist of the present invention may be unnecessarily obscured.

1 is a structural diagram illustrating a process of thin film stacking for DRAM formation according to an exemplary embodiment of the present invention, in which a buried oxide 102 is formed on a bulk silicon 101 and an SOI wafer ( A bottom gate oxide 104 is sequentially formed on the 103 by an oxidation process. Preferably, a bottom gate material is then deposited with doped poly-Si (poly-Si) 105 and WSi 106, and a CVD oxide film 107 is deposited thereon, and the film is deposited with CMP ( Chemical Mechanical Polishing) to favor bonding. The thickness of the bottom gate oxide film is 2-8 nm and particularly preferably 5 nm, the thickness of the poly-Si is preferably 30-150 nm and particularly preferably 50 nm, and the thickness of the WSi is preferably Is 50-150 nm and particularly preferably 70 nm, and the CVD oxide film is preferably deposited to a thickness of 10-1,000 nm, more preferably to a thickness of 300 nm.

Then, as shown in FIG. 2, a thermal oxide film is formed on the mechanical support handle wafer 201 and adhered to the upper portion of the wafer of FIG. Appropriate bonding machinery is used to prevent voids from forming. The bottom of the original SOI wafer is removed using a lapping apparatus to wrap the original SOI wafer substrate until the substrate remains properly over the oxide film. Thereafter, the wet etching agent is used to remove the remaining substrate Si and the buried oxide film (referring to the oxide film portion 102 of the SOI wafer) to reveal a single crystal Si layer. Preferably the single crystal Si layer is 5-25 nm, more preferably 10 nm.

Then, as shown in FIG. 3A, a gate oxide film 304 for a top gate is formed by an oxidation process, and sequentially doped poly-Si 303 and WSi 302 which are top gate materials are deposited. SiN layer 301 is deposited. Alternatively, a SiGe layer doped with N + and P +, respectively, may be used as the gate material. Thereafter, the deposited substrate etches all sides of the top gate, the channel, and the bottom gate by a photolithography and a dry etching process as shown in FIG. 3B. 3, the active region is formed by performing a general photo process and an etching process defining the active region. The thickness of the oxide is preferably 1-8 nm, particularly preferably 5 nm. The thickness of the doped poly-Si is preferably 30-100 nm and particularly preferably 50 nm. The thickness of the WSi is preferably 50-150 nm, particularly preferably 70 nm. The thickness of the SiN layer is preferably 30-250 nm, particularly preferably 100 nm.

Figure 4 shows a comparison planar structure showing the active region used in the conventional DRAM manufacturing process and the active region of the present invention, the dotted line is a conventional active region of the elliptical form, the active region according to the present invention is more length portion You can see that it shrinks faster as it goes to the edge of the center width. The reason for this structure is to widen the process window so that adjacent active cells are not shorted in subsequent source / drain definition SEGs. This purpose can be achieved by making the width of the active region of the DC portion in direct contact (DC) larger than the width of the active region of the BC region in BC (Buried Contact), so that the primary grown SEG is They do not touch each other, but at the DC site, DC proceeds to meet each other. FIG. 5 illustrates a planar structure diagram of a thin film stack after etching is performed in the process of FIG. 3.

Thereafter, when the gate material and the channel are oxidized by the oxidation process as shown in FIG. 6, the oxidation rate of the gate material increases. By using this, wet etching is performed only to remove the oxide layer of the less grown channel Si region. When the exposed sidewall of the channel is used as a seed, when the SEG (primary SEG) 701 is grown, it grows as shown in FIG. 8, and FIG. 8 is also a cross-sectional view taken along line A-A 'of FIG. 7. In the conventional DRAM, the areas where direct contact (DC) is formed are grown to the extent that the active regions become wider and stick together, and the areas where buried contact (BC) are formed are far apart from each other and are not shorted to each other. . For example, a 100 nm design rule DRAM can grow to about 70 nm. However, further growth is also possible if the process is adjusted to have a preference according to the crystallographic direction. Thereafter, as illustrated in FIG. 9, a CVD oxide film 901 deposition process is performed to fill an empty space under the SEG, and an etch-back process is performed as shown in FIG. 10.

Thereafter, a process of completing the source / drain for NMOS and PMOS in the peripheral region is performed. As shown in FIG. 11, the SiN layer is deposited, and only the region around the NMOS is opened by SiN dry etching, followed by implantation of As + ions. Then, as shown in FIG. 12, the exposed SEG layer is seeded to add SEG (secondary SEG) growth again to extend the landing area at the subsequent metal contact and again to ion implantation. Thereby doping the extended SEG region. Then, by depositing the CVD oxide, subsequent contact metals can be formed with wide windows, as shown in FIG.

The surrounding PMOS region can then also be formed by the same method, namely through opening, ion implantation, secondary SEG, ion implantation, and final CVD oxide deposition.

Alternatively, the ion implantation may be performed by opening both the NMOS and the PMOS without growing the ion before performing the second SEG, growing the SEG at once, and then opening the ion again.

As another method, only source / drain ion implantation may be performed by respectively opening the NMOS and the PMOS without performing secondary SEG growth, and may be connected to each other at the time of contact etching.

In another method, a dummy gate may be formed to surround the contact pad portion, and then poly-Si may be left by poly-Si etching or CMP.

After the source / drain formation process of the surrounding CMOS, as shown in FIG. 15, a self-aligned contact (SAC) is opened to form DC and BC of the cell. 15 is a cross-sectional view taken along the line A-A 'of FIG. Then, as shown in FIG. 16, the SiN and CVD oxide films deposited for the surrounding CMOS process are removed by dry etching, and after the SAC is opened, ion implantation for the contact plug is performed, and then poly-Si is deposited. -Perform etching or CMP. However, by growing to SEG instead of poly-Si, the subsequent post-etch process can be omitted.

The metal contact process then proceeds. Due to the characteristics of the DRAM, the source and drain contacts for the gate and the active region are simultaneously formed. At this time, the top gate and the bottom gate of the double gate should be connected to the metal at the same time. This can be achieved by forming a structure in which portions to be contacted for the gate are separated as shown in FIGS. 17 and 18. That is, when the parts connected to each other are separated by the conventional method as in the circled portion of FIG. 17, the contact 181 is formed as shown in FIG. At the same time, the source / drain portions of the active region can be connected in the same process.

19 and 20 illustrate another method in which the top gate and the bottom gate are simultaneously connected by one contact. As shown in FIGS. 19 and 20, the gate line is formed as in a conventional DRAM and a suitable step, for example, a gate When the gate contact is opened after the spacer is etched, and only the top gate is anisotropically etched, the top gate and the bottom gate may be simultaneously connected by one contact in the original contact etching process.

The semiconductor DRAM using the semiconductor SSDG MOSFET manufactured by the above method has two transistors in one cell, that is, one bit line has two bit lines so that the semiconductor DRAM can be implemented in the same arrangement as a conventional planar MOS transistor. The active layer is partially defined by the gate in such a way as to charge the word line.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the top gate and the bottom gate according to the embodiment of the present invention are connected by one contact at the same time, thereby solving the problems of DIBL, channel resistance, gate resistance, and junction leakage current of the conventional MOS transistor. It is effective. In addition, a process of forming a well may be omitted, and thus a photo and ion implantation process may be omitted. In addition, it can be applied without changing the mask for the existing DRAM manufacturing.

Claims (17)

In a manufacturing process of a DRAM using a self-aligned SOI double gate transistor (SELF ALIGNED SOI DOUBLE GATE TRANSISTOR), Forming a double gate on the substrate; Forming a cell by forming a source / drain for CMOS in a peripheral region on the substrate on which the double gate is formed; Forming direct contact (DC) and buried contact (BC) of the cell; Forming a metal contact on the direct contact and the buried contact of the cell. The method of claim 1, wherein the double gate, Sequentially depositing a buried oxide film, an SOI wafer, a bottom gate oxide film, a poly-Si, WSi, and a CVD oxide film on top of the bulk Si; Forming a thermal oxide film on a support handle wafer, bonding it to the top of the SOI wafer, and removing the bulk Si and buried oxide film; Photographic and etching steps defining the active area; Sequentially depositing a gate oxide film, poly-Si, WSi, and SiN layers with a top gate material on the back side of the support handle wafer; Etching side surfaces of the stacked top gate, channel and bottom gate, and then oxidizing gate material and channel; Growing an SEG with seed of the oxidized exposed channel sidewall, and then depositing a CVD oxide film under the SEG, and performing etch-back. Manufacturing method. The process of claim 1, wherein the source / drain for the CMOS in the peripheral region is formed. Depositing a SiN spacer on the DRAM having the double gate, etching SiN to open only a peripheral NMOS region, and implanting ions therein; Seeding the exposed SEG layer for secondary SEG growth, thereafter implanting an ion implant, and then depositing a CVD oxide film; Forming a peripheral PMOS region in the same manner as the opening, ion implantation, secondary SEG, ion implantation, and CVD oxide deposition. The method of claim 1, wherein the process of forming a direct contact (DC) and a buried contact (BC) of the cell includes: Etching the SiN spacer and the CVD oxide film formed in the peripheral CMOS source / drain formation process to open a self-aligned contact (SAC); Performing ion implantation for contact plugs in said open area; Depositing poly-Si and performing etch-back or CMP. The method of claim 1, wherein the forming of the metal contact comprises: Separating the part to be contacted for the gate; And a top of the double gate and a bottom gate are simultaneously connected to the metal, and a source / drain of the active region is also connected together. The method of manufacturing a semiconductor DRAM according to any one of claims 1 to 5, wherein a SiGe layer doped with N + and P +, respectively, is used as the top gate material. The method according to any one of claims 1 to 5, wherein when the active region is formed, the width of the active region of the DC portion in direct contact (DC) is greater than that of the BC region in buried contact (BC). A method for manufacturing a semiconductor DRAM, characterized by widening a window of the process. The method according to any one of claims 1 to 5, wherein the growing of the SEG by seeding the exposed sidewalls of the channel is performed so that the first-grown SEGs do not touch each other at the BC to BC site, and at DC to DC. The portion proceeds to meet each other. The process of claim 1 or 2, wherein the step of forming a source / drain for CNMOS in the peripheral region is performed without ion implantation before performing secondary SEG. Opening both NMOS and PMOS to grow secondary SEGs at once; And then reopening each to perform ion implantation. The process according to any one of claims 1 to 5, wherein the process for forming a source / drain for CMOS in the peripheral region does not perform secondary SEG growth, Performing only source / drain ion implantation open to the NMOS and PMOS, respectively; And then connecting them to each other at the time of contact etching. The process according to any one of claims 1 to 5, wherein the process for forming a source / drain for NMOS and PMOS in the peripheral region, Forming a dummy gate to surround the contact pad portion; And then leaving the poly-Si by post-etching or CMP to leave the poly-Si. The process of claim 1, wherein the forming of the metal contact is performed. A method of manufacturing a semiconductor DRAM after etching a gate spacer, in which only the top gate portion is etched in advance so as to simultaneously connect the bottom gate and the top gate, so that they are all connected in a subsequent main contact process. The thickness of the bottom gate oxide film is 2-8 nm, the thickness of the poly-Si doped on the bottom gate oxide film is 30-150 nm, and the poly-S. The thickness of the WSi deposited on top of the semiconductor DRAM manufacturing method, characterized in that 50-150nm. The method of manufacturing a semiconductor DRAM according to any one of claims 1 to 5, wherein the single crystal Si layer formed by removing the substrate Si and the buried oxide film is 5 to 25 nm. The thickness of the top gate gate oxide film is 1-8 nm, and the thickness of the poly-Si deposited on top of the top gate gate oxide film is 30-100 nm. A semiconductor DRAM manufacturing method. The semiconductor DRAM manufacturing method according to any one of claims 1 to 5, wherein the thickness of the SiN layer deposited on the top gate gate oxide film is 30 to 250 nm. Double gates formed on top and bottom of the SOI wafer; A source / drain region for CMOS formed in a peripheral region of the substrate on which the double gate is formed; Direct contact and investment contact formed by etching a portion of the source / drain region for CMOS to open a self-aligned contact, and performing ion implantation for a contact plug in the open area; A DRAM using a self-aligned SOI double gate transistor including a metal contact formed such that the top and bottom gates of the double gate are simultaneously connected and the source / drain of the active region is connected together.