KR20030078541A - Arithmetic unit for processing guard bits simply in DSP and guard bits processing method in the Arithmetic unit - Google Patents

Abstract

PURPOSE: A device for simply operating a guard bit on a DSP(Digital Signal Processor) and a method for processing the guard bit on the same are provided to reduce cost by reducing a circuit for processing the guard bit of an operator and reducing the number of the used devices. CONSTITUTION: The operator(20) outputs an addition result of 'n' bit through an addition operation by receiving the first and the second input of the 'n' bit. An accumulator(30) of the 'n' bit accumulates the output of the operator(20). A guard bit processor(40) compares respective code bit by inputting the first and the second input upper than 'p', and the upper 'p' bit of the operator's output, and processes the guard bit by adding or subtracting 1 to a current guard bit value according to a comparison result.

Description

Arithmetic unit for processing guard bits simply in DSP and guard bits processing method in the Arithmetic unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to arithmetic units in a DSP, and more particularly, to arithmetic units with simple processing of guard bits in arithmetic units and a method of processing guard bits performed in the arithmetic units.

In general, in a DSP, an operator consists of a size that includes the guard bit size to process the guard bit. Fixed Point DSPs typically have a 16-bit or 24-bit word structure. In this case, a combination of a multiplier and an operator exists on a circuit to perform a MAC (Multiply and Accumulation) operation, which is a characteristic of a general DSP. At this time, the multiplier consists of hardware whose input is word x word and the output is 2 x word. In this structure, the MAC operation is repeated in designing a filter, which is one of the main applications of the DSP, and a temporary overflow may occur during the repetition of the MAC operation.

In general, the MAC operation repeats multiply and accumulation as shown in Equation 1 below.

P (32-bit) = X (16-bit) * Y (16-bit)

ACC (32-bit) = ACC '+ P (32-bit)

X and Y are two factors for performing multiplication, and ACC is the result of adding the current multiplication result P to the previous accumulated value ACC '. As such, you need a 16x16 multiplier and a 32-bit operator (ALU) to multiply the X, Y two factors and accumulate the multiplication result. At this time, the result added by the operator is not always 32-bit, and a temporary overflow may occur. As such, the number of bits of the operator is extended to prevent a calculation error due to an overflow that occurs during MAC operation, and the extended bits are called guard bits. For example, if 4 bits are allocated as guard bits, then a 32-bit operator needs a 4-bit adder for guard bit processing for normal MAC operation. On the other hand, the adder requires two XOR logic, two AND logic, and one OR logic per 1-bit, and eventually, eight XOR logic, eight AND logic, and four OR logic are needed to construct a 4-bit adder. This increases the burden on the circuit.

Many DSPs have circuits for guardbit processing in operators and accumulators to prevent this overflow, which leads to an increase in the size of the datapath cell.

The first technical problem to be achieved by the present invention is to provide an arithmetic unit with a simple guard bit processing in a DSP.

A second technical problem to be achieved by the present invention is to provide a guard bit processing method performed in the computing device.

A third technical problem to be achieved by the present invention is to provide a recording medium in which the guard bit processing method is recorded in a program code executable by a computer.

1 is a block diagram schematically showing an arithmetic unit with a simple guard bit process according to the present invention.

FIG. 2 is a flowchart illustrating an example of a method of processing a guard bit performed by the guard bit processing unit of the apparatus illustrated in FIG. 1.

In order to achieve the first task, the computing device according to the present invention receives an n (> 0) -bit first input and an n-bit second input, and adds the result of an arithmetic operator and an operator. The n-bit accumulator and initial guard bit value, which accumulates the output, is equal to the value of the upper m bits of the accumulator, the upper p (<n) bits of the first input, the upper p bits of the second input, and the upper p bits of the operator output. It is preferable to include a guard bit processing unit of m (<n) bits to compare the respective coded bits by inputting and to add or subtract 1 to the current guard bit value to perform guard bit processing.

In order to achieve the second task, an operator that receives and adds a first input of n (> 0) bits and a second input of n bits to output an n-bit addition result, and an n-bit accumulating the output of the operator. In an arithmetic unit in a DSP including an m (<n) bit guard bit processing unit for processing guard bits of an accumulator and an operator, the guard bit processing method according to the present invention performed in the guard bit processing unit is a In step (a), the initial value is initialized to be equal to the upper m bits of the accumulator, and in step (b) and (b), it is determined whether the overflow has occurred in the operator. If an overflow occurs in steps (c) and (c) of determining whether an underflow has occurred, if the overflow has not occurred, subtract 1 from the current guard bit value, and under And the inclusion of the step (d) that if the row is not generated as it maintains the current value of the guard bit are preferred.

Hereinafter, a description will be given of an arithmetic unit with a simple guard bit processing in a DSP according to the present invention and a method of processing a guard bit in the arithmetic apparatus as follows.

1 is a block diagram schematically illustrating an arithmetic unit with a simple guard bit process according to the present invention, and includes an operator 20, an accumulator 30, and a guard bit processor 40. For convenience of description, FIG. 1 shows a computing device for MAC operation and shows a multiplier 10 together. The operator 20 and the accumulator 30 are 32-bit calculators and accumulators, respectively, and the multiplier 10 inputs 16 x 16 data to output 32 bits.

Referring to FIG. 1, the operator 20 receives 32 bits of data output from the multiplier 10 as a first input and 32 bits of data output from the accumulator 30 as a second input. The first and second inputs are added to output a 32-bit addition result.

Accumulator 30 accumulates the 32-bit output of operator 20.

The guard bit processing unit 40 has, for example, four bits of addition bits, and the initial guard bit value is set to the value of the upper four bits of the accumulator 30. The guard bit processor 40 compares the first input, the second input, and the accumulator 30 by inputting an upper p (<32, assuming p = 4) bit including the sign bit, and comparing the result. Therefore, guard bit processing is performed by adding or subtracting 1 to the current guard bit value.

That is, the guard bit processing unit 40 may determine whether an overflow or underflow has occurred in the operator 20 by comparing the upper p bits of the first input, the second input, and the accumulator 30. If an overflow occurs in the operator 20, 1 is added to the current guard bit value, and if an overflow occurs, a guard bit process is performed to subtract 1 from the current guard bit value. That is, if an overflow occurs, a carry to an upper bit is generated, so 1 is added. If an underflow occurs, a carry is performed to a lower bit, so 1 is subtracted.

FIG. 2 is a flowchart illustrating an example of a method of processing a guard bit performed by the guard bit processing unit 40 of the apparatus illustrated in FIG. 1.

Referring to FIGS. 1 and 2, first, the guard bit processing unit 40 initializes the initial value of the guard bit of 4 bits to be equal to the upper 4 bits of the accumulator 30. Then, the guard bit processing unit 40 inputs the upper bits including the sign bits from the first input, the second input, and the accumulator 30, and codes each of the sign bits of the first input and the second input and the accumulator. By comparing the bits, it is determined whether an overflow has occurred or whether an underflow has occurred (steps 100 and 110).

If an overflow occurs, the guard bit processing unit 40 adds 1 to the current guard bit value EACC (step 120), and if an overflow occurs, subtracts 1 from the current guard bit value EACC. (Step 130). As described above, when an overflow occurs in the operator 20, a carry to a higher bit is generated, and thus 1 is added. When an underflow occurs, a carry is performed to a lower bit, so 1 is subtracted. It is. In addition, if neither an overflow nor an underflow occurs, the current guard bit value EACC is maintained as it is (step 140).

On the other hand, if overflow occurs, positive and positive numbers are added, but the addition result is negative, or negative numbers are subtracted from the positive number, but the subtraction result is negative. Able to know. That is, the guard bit processing unit 40 compares the sign bits of the data output from the first input, the second input, and the operator 20, and when the first input and the second input are both positive numbers, If the result of adding the first input and the second input is negative, it is determined that the overflow occurs in the calculator 20. In addition, when the first input is positive and the second input is negative, even when the result of subtracting the second input from the first input is negative, the guard bit processor 40 determines that an overflow has occurred in the calculator.

In addition, when an underflow occurs, negative and negative numbers are added, but the addition result is positive, or the positive result is subtracted from negative numbers, but the subtraction result is positive. That is, the guard bit processing unit 40 compares the sign bits of the data output from the first input, the second input, and the operator 20, and when the first input and the second input are both negative, If the result of adding the first input and the second input is a positive number, the operator 20 determines that an underflow has occurred. In addition, when the first input is negative and the second input is positive, even when the result of subtracting the second input from the first input is positive, the guard bit processor 40 determines that an underflow has occurred in the calculator.

As described above, the guard bit processing unit 40 according to the present invention is a simple operation of adding or subtracting 1 to the current guard bit according to whether an overflow or an underflow occurs in the operator. To process That is, a plurality of logic elements are conventionally required to process the guard bits of the operator. However, since only one adder and a subtractor are required in the present invention, the circuit size for the guard bit processing of the operator is reduced, and the number of elements used is large. Reduction can result in cost savings.

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the arithmetic unit with simple guard bit processing in the DSP according to the present invention and the guard bit processing method in the arithmetic unit, according to whether or not overflow or underflow has occurred in the arithmetic unit, A simple operation that adds or subtracts one to handle the guard bits of the operator. That is, since only one adder and a subtractor are needed for the guard bit processing of the operator, the size of the circuit for guard bit processing of the operator is reduced, and the number of elements used can be greatly reduced, thereby achieving cost reduction.

Claims (6)

an operator which receives the first input of n (> 0) bits and the second input of n bits and adds the result to output an n-bit addition result; An n-bit accumulator that accumulates the output of the operator; And The initial guard bit value is equal to the value of the upper m bits of the accumulator, and inputs the upper p (<n) bits of the first input, the upper p bits of the second input, and the upper p bits of the operator output, respectively. And a m (<n) bit guard bit processing unit for comparing the code bits and adding or subtracting 1 to the current guard bit value and performing guard bit processing according to the comparison result. The method of claim 1, wherein the guard bit processing unit And if the overflow occurs in the operator according to the comparison result, 1 is added to the current guard bit value, and if an underflow occurs, 1 is subtracted from the current guard bit value. An operator that accepts and adds an n (> 0) bit first input and an n bit second input to output an n-bit addition result, an n-bit accumulator that accumulates the output of the operator, and a guard bit of the operator In the arithmetic unit in the DSP including a m (<n) bit guard bit processing unit for processing, in the guard bit processing method performed in the guard bit processing unit, (a) initializing an initial value of the m-bit guard bit to be equal to an upper m-bit of the accumulator; (b) determining whether an overflow occurs in the calculator; (c) adding an 1 to a current guard bit value when an overflow occurs in step (b), and determining whether an underflow occurs in the operator if an overflow does not occur; And (d) subtracting 1 from the current guard bit value when an underflow occurs in step (c), and maintaining the current guard bit value as it is if no underflow occurs. Treatment method. The method of claim 3, wherein in step (c) The guard bit processing unit compares the sign bits of the first input and the second input with the sign bits output from the operator, When both the first input and the second input are positive, when the result of adding the first input and the second input in the calculator is negative, when the first input is positive and the second input is negative And if the result of subtracting the second input from the first input is a negative number, the operator determines that an overflow has occurred. The method of claim 3, wherein in step (d) The guard bit processing unit compares the sign bits of the first input and the second input with the sign bits output from the operator, When both the first input and the second input are negative, when the result of adding the first input and the second input in the calculator is positive, when the first input is negative and the second input is positive, And if the result of subtracting the second input from the first input is positive, the operator determines that an underflow has occurred. A cross media having recorded the method of claim 3 to 5 as program code executable on a computer.