KR20030050782A - Method of planarization for semiconductor device - Google Patents

Method of planarization for semiconductor device Download PDF

Info

Publication number
KR20030050782A
KR20030050782A KR1020010081300A KR20010081300A KR20030050782A KR 20030050782 A KR20030050782 A KR 20030050782A KR 1020010081300 A KR1020010081300 A KR 1020010081300A KR 20010081300 A KR20010081300 A KR 20010081300A KR 20030050782 A KR20030050782 A KR 20030050782A
Authority
KR
South Korea
Prior art keywords
ammonia
planarization
tungsten
semiconductor substrate
semiconductor device
Prior art date
Application number
KR1020010081300A
Other languages
Korean (ko)
Inventor
권병호
김운용
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020010081300A priority Critical patent/KR20030050782A/en
Publication of KR20030050782A publication Critical patent/KR20030050782A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

PURPOSE: A planarization method of a semiconductor device is provided to be capable of easily removing slurry residuals by carrying out a buffing process using ammonia after a CMP(Chemical Mechanical Polishing) process. CONSTITUTION: After forming an interlayer dielectric(12) on a semiconductor substrate(10), the interlayer dielectric is selectively etched by using a photoresist pattern as a mask for exposing the predetermined portion of the semiconductor substrate. After depositing a tungsten layer(14) on the resultant structure, a planarization process is carried out for forming a tungsten plug(16). A buffing process is carried out by using ammonia for removing particles(20) remaining on the tungsten plug. Then, a cleaning process is carried out at the resultant structure.

Description

반도체 소자의 평탄화 방법{Method of planarization for semiconductor device}Method of planarization for semiconductor device

본 발명은 반도체 소자의 평탄화 방법에 관한 것으로, CMP(Chemical Mechanical Polishing) 공정을 이용한 반도체 소자의 평탄화 방법에 관한 것이다.The present invention relates to a planarization method of a semiconductor device, and to a planarization method of a semiconductor device using a chemical mechanical polishing (CMP) process.

일반적으로, 텅스텐(W) CMP 공정을 이용한 평탄화 공정시 선택적으로 버핑(Buffing)을 채택하여 사용하고 있으며, 버핑은 펠트 타입의 패드(예를 들면, 로델사의 'Politex pad' 등)를 이용하고, 그 매개로 DI-워터(Water)를 이용하고 있다. 이처럼, 평탄화 공정후 웨이퍼의 표면에 잔존하는 슬러리 잔존물을 제거하기 위해 버핑의 매개로 DI-워터만을 사용하고 있지만, DI-워터만으로는 웨이퍼의 표면에 잔존하는 슬러리 잔존물을 완전히 제거할 수 없는 문제가 발생한다.In general, in the planarization process using a tungsten (W) CMP process, buffing is selectively used. Buffing is performed using a felt-type pad (eg, 'Politex pad' manufactured by Rhodel, etc.) DI-water is used as the medium. As such, although only DI-water is used as a buffing medium to remove slurry residues remaining on the surface of the wafer after the planarization process, a problem arises in that DI-water alone cannot completely remove slurry residues remaining on the surface of the wafer. do.

이에 따라, 최근에는 평탄화 공정(CMP)을 실시하고, DI-워터를 사용하여 버핑을 한 후 클리너에서 암모니아를 이용한 브러쉬 클리닝을 실시하거나, 초음파를 이용하여 클리닝을 실시하여 웨이퍼의 표면에 잔존하는 슬러리 잔존물을 완전히 제거하고 있다. 여기서, 클리닝 용액으로 암모니아를 사용하는 이유는 암모니아가 웨이퍼 표면의 제타 포텐셜(Zeta potential)과 파티클(Paticle)의 제타 포텐셜을 같게 하는 역할을 하기 때문이다. 이로써, 파티클이 웨이퍼의 표면에 흡착되는 것이 아니라, 웨이퍼의 표면으로부터 떨어져 나가는 효과가 발생하여 브러쉬를 이용한 클리닝 효과를 극대화할 수 있다.Accordingly, recently, the planarization process (CMP) is performed, the buffing is performed using DI-water, the brush cleaning using ammonia in the cleaner, or the cleaning using ultrasonic waves is carried out, and the slurry remains on the surface of the wafer. The residue is completely removed. The reason for using ammonia as the cleaning solution is that ammonia acts to equalize the zeta potential of the wafer surface and the zeta potential of the particles. As a result, the particles are not adsorbed on the surface of the wafer, but the effect of falling off from the surface of the wafer is generated, thereby maximizing the cleaning effect using the brush.

그러나, 종래의 기술과 같이 암모니아를 이용한 클리닝 공정을 실시하더라도 웨이퍼의 표면에는 슬러리 잔존물이 일부 잔존하게 된다. 특히, 텅스텐 플러그를 형성하기 위한 텅스텐 평탄화 공정시 텅스텐 플러그가 인접한 절연물에 비해 단차가 조금 낮게 되는 현상, 즉 플러그 리세스(Plug recess) 또는 디싱(Dishing) 현상에 의해 플러그 부위가 인접한 절연물에 비해 대략 100 내지 500Å 정도 낮아짐에따라 파티클이 인접한 절연물인 산화막에 의해 보호를 받아 브러쉬가 효과적으로 파티클을 제거하지 못하는 문제가 발생한다.However, even if a cleaning process using ammonia is performed as in the prior art, some residue of slurry remains on the surface of the wafer. In particular, in the tungsten planarization process for forming a tungsten plug, the tungsten plug has a slightly lower level than the adjacent insulator, that is, the plug recess or dishing causes the plug portion to be roughly lower than the adjacent insulator. As the particle size is lowered by about 100 to 500 mV, the particles are protected by an oxide film, which is an adjacent insulator, and the brush does not effectively remove the particles.

따라서, 본 발명은 상기의 문제를 해결하기 위해 안출된 것으로, CMP(Chemical Mechanical Polishing) 공정후 암모니아를 이용하여 버핑 공정을 실시하여 CMP 공정후 잔존하는 슬러리 잔존물과 파티클을 쉽게 제거함으로써 반도체 소자의 금속 배선 공정의 전기적 특성 및 수율을 향상시킬 수 있는 반도체 소자의 평탄화 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, the buffing process using ammonia after the CMP (Chemical Mechanical Polishing) process to easily remove the residual slurry and particles remaining after the CMP process metal of the semiconductor device It is an object of the present invention to provide a planarization method of a semiconductor device capable of improving electrical characteristics and yield of a wiring process.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 평탄화 방법을 설명하기 위해 도시한 반도체 소자의 단면도.1A to 1C are cross-sectional views of a semiconductor device for explaining the planarization method of the semiconductor device according to the embodiment of the present invention.

도 2는 pH에 따른 물질의 제타 포텐셜 변화를 나타내는 그래프2 is a graph showing the change in zeta potential of a material according to pH

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 반도체 기판 12 : 층간 절연막10 semiconductor substrate 12 interlayer insulating film

14 : 텅스텐 16 : 텅스텐 플러그14: tungsten 16: tungsten plug

18 : 텅스텐 산화층 20 : 파티클18: tungsten oxide layer 20: particles

상술한 목적을 달성하기 위해 본 발명은 반도체 기판 상에 형성된 소정층을 화학적 기계적 평탄화 공정을 실시하여 평탄화하는 단계; 상기 화확적 기계적 평탄화 공정후 상기 소정층 상에 잔존하는 파티클을 제거하기 위해 암모니아를 이용한 버핑 공정을 실시하는 단계; 및 상기 소정층을 포함한 반도체 기판을 클리닝하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises the steps of: planarizing a predetermined layer formed on a semiconductor substrate by performing a chemical mechanical planarization process; Performing a buffing process using ammonia to remove particles remaining on the predetermined layer after the chemical mechanical planarization process; And cleaning the semiconductor substrate including the predetermined layer.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 평탄화 방법을 설명하기 위해 도시한 반도체 소자의 단면도이다.1A to 1C are cross-sectional views illustrating a semiconductor device for explaining the planarization method of the semiconductor device according to the embodiment of the present invention.

도 1a를 참조하면, 메모리 셀 및 트랜지스터를 형성하기 위한 게이트 전극 및 접합 영역(도시하지 않음)이 형성된 반도체 기판(10) 상에 층간절연막(12)을 형성한다.Referring to FIG. 1A, an interlayer insulating film 12 is formed on a semiconductor substrate 10 on which a gate electrode and a junction region (not shown) for forming a memory cell and a transistor are formed.

이어서, 전체 구조 상부에 포토레지스트(Photoresist)를 도포한 후 포토 마스크를 이용한 노광공정을 실시하여 반도체 기판(10)의 소정 부위를 오픈하기 위한 포토레지스트 패턴(도시하지 않음)을 형성한다. 이어서, 포토레지스트 패턴을 이용한 식각공정을 실시하여 반도체 기판(10)의 소정 부위가 오픈되도록 콘택홀(도시하지 않음)을 형성한다. 이어서, 콘택홀을 매립하도록 전체 구조 상부에 텅스텐(W; 14)을 증착한다.Subsequently, a photoresist is applied over the entire structure, followed by an exposure process using a photo mask to form a photoresist pattern (not shown) for opening a predetermined portion of the semiconductor substrate 10. Subsequently, an etching process using a photoresist pattern is performed to form contact holes (not shown) to open predetermined portions of the semiconductor substrate 10. Subsequently, tungsten (W) 14 is deposited on the entire structure to fill the contact holes.

도 1b 및 도 1c를 참조하면, 전체 구조 상부에 CMP(Chemical Mechanical Polishing)를 이용한 평탄화 공정을 실시하여 텅스텐(14)을 연마하여 콘택홀을 매립하도록 텅스텐 플러그(16)을 형성한다.1B and 1C, a tungsten plug 16 is formed to fill a contact hole by grinding tungsten 14 by performing a planarization process using CMP (Chemical Mechanical Polishing) on the entire structure.

이어서, CMP 공정후 텅스텐 플러그(16)의 상부 표면에 잔존하는 슬러리 잔존물인 텅스텐 산화막(WO3; 18)과 파티클(20)을 제거하기 위해 버핑 공정이 실시된다. 이때, 버핑 공정은 펠트 타입의 패드를 이용하여 연마 압력을 2 내지 5psi로 하고, 연마판의 회전속도를 20 내지 100rpm으로 하며, 암모니아(NH4OH)의 유량을 분당 200 내지 300ml등으로 하여 상기 반도체 기판(10)의 상부 표면에 암모니아가 충분히 전달되도록 실시한다. 이로써, 반도체 기판(10)의 상부 표면, 즉 텅스텐 플러그(16)의 상부 표면과 파티클(20)의 제타 포텐셜이 동일해져서 텅스텐 플러그(16)와 파티클(20) 간에 척력이 작용하여 파티클 제거가 쉬워진다. 또한, 암모니아가 텅스텐 산화막(18)을 녹임으로써 텅스텐 산화막(18) 상에 존재하는 파티클(20)을 쉽게 제거할 수 있다.Subsequently, after the CMP process, a buffing process is performed to remove the tungsten oxide film (WO 3 ; 18) and the particles 20, which are slurry residues remaining on the upper surface of the tungsten plug 16. At this time, the buffing process using a felt-type pad, the polishing pressure is 2 to 5psi, the rotation speed of the polishing plate is 20 to 100rpm, the flow rate of ammonia (NH 4 OH) to 200 to 300ml per minute and the like The ammonia is sufficiently transferred to the upper surface of the semiconductor substrate 10. As a result, the upper surface of the semiconductor substrate 10, that is, the upper surface of the tungsten plug 16 and the zeta potential of the particle 20 are equal to each other, so that the repulsive force acts between the tungsten plug 16 and the particle 20 to facilitate particle removal. Lose. In addition, by ammonia melting the tungsten oxide film 18, the particles 20 present on the tungsten oxide film 18 can be easily removed.

이어서, 이루어지는 공정은 종래의 기술과 동일함으로 여기서는 생략하기로 한다.Subsequently, the process made is the same as in the prior art and will be omitted here.

상기에서 설명한 본 발명은 텅스텐 평탄화 공정에 한정되는 것이 아니라, 웨이퍼 표면과 파티클 간의 제타 포텐셜이 같아지는 모든 평탄화 공정에 적용할 수 있다. 예를 들어, 산화막 평탄화 공정 및 STI(Shallow Trench Isolation) 평탄화 공정에 모두 적용할 수 있다.The present invention described above is not limited to the tungsten planarization process, but can be applied to any planarization process in which the zeta potential between the wafer surface and the particles is equal. For example, the present invention can be applied to both an oxide film planarization process and a shallow trench isolation (STI) planarization process.

본 발명은 CMP 공정후 이루어지는 버핑 공정시 DI-워터 대신 암모니아를 이용하는 것을 특징으로 하고 있는데, 도 2에 도시된 바와 같이 암모니아(NH4OH)는 강알칼리성 지역(B area)에 해당하는 11pH을 띠게 되는데, 이 pH에서 웨이퍼의 모든 물질은 모두 같은 '-' 제타 포텐셜을 갖게 됨을 알 수 있다. 예를 들어, 텅스텐(W)의 경우 이 pH에서 '-' 제타 포텐셜을 갖는다. 따라서, 텅스텐과 파티클 간에 서로 척력이 작용하게 됨을 예측할 수 있으며, 암모니아를 사용해서 버핑 공정을 실시하면 종래의 공정처럼 클리닝 공정에서 브러쉬를 사용하여 클리닝하는 것보다 훨씬더 큰 효과를 기대할 수 있다.The present invention is characterized by using ammonia instead of DI-water during the buffing process after the CMP process, as shown in Figure 2 ammonia (NH 4 OH) has an 11pH corresponding to a strong alkaline area (B area) At this pH, all of the materials in the wafer have the same '-' zeta potential. For example, tungsten (W) has a '-' zeta potential at this pH. Therefore, it can be expected that the repulsive force acts between the tungsten and the particles, and the buffing process using ammonia can be expected to have a much larger effect than the cleaning using the brush in the cleaning process as in the conventional process.

본 발명은 CMP(Chemical Mechanical Polishing) 공정후 암모니아를 이용하여 버핑 공정을 실시하여 CMP 공정후 잔존하는 슬러리 잔존물과 파티클을 쉽게 제거함으로써 반도체 소자의 금속 배선 공정의 전기적 특성 및 수율을 향상시킬 수 있다.The present invention can improve the electrical properties and yield of the metal wiring process of the semiconductor device by performing a buffing process using ammonia after the chemical mechanical polishing (CMP) process to easily remove the slurry residue and particles remaining after the CMP process.

Claims (3)

반도체 기판 상에 형성된 소정층을 화학적 기계적 평탄화 공정을 실시하여 평탄화하는 단계;Planarizing a predetermined layer formed on the semiconductor substrate by performing a chemical mechanical planarization process; 상기 화확적 기계적 평탄화 공정후 상기 소정층 상에 잔존하는 파티클을 제거하기 위해 암모니아를 이용한 버핑 공정을 실시하는 단계; 및Performing a buffing process using ammonia to remove particles remaining on the predetermined layer after the chemical mechanical planarization process; And 상기 소정층을 포함한 반도체 기판을 클리닝하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 평탄화 방법.And cleaning the semiconductor substrate including the predetermined layer. 제 1 항에 있어서,The method of claim 1, 상기 소정층은 텅스텐 또는 산화막으로 이루어지는 것을 특징으로 하는 반도체 소자의 평탄화 방법.And the predetermined layer is formed of tungsten or an oxide film. 제 1 항에 있어서,The method of claim 1, 상기 버피 공정은 연마 압력을 2 내지 5psi로 하고, 연마판의 회전속도를 20 내지 100rpm으로 하며, 상기 암모니아(NH4OH)의 유량을 분당 200 내지 300ml로 하여 실시하는 것을 특징으로 하는 반도체 소자의 평탄화 방법.The buffy process is carried out at a polishing pressure of 2 to 5 psi, a rotational speed of the polishing plate to 20 to 100 rpm, and a flow rate of the ammonia (NH 4 OH) at 200 to 300 ml per minute. Planarization method.
KR1020010081300A 2001-12-19 2001-12-19 Method of planarization for semiconductor device KR20030050782A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010081300A KR20030050782A (en) 2001-12-19 2001-12-19 Method of planarization for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010081300A KR20030050782A (en) 2001-12-19 2001-12-19 Method of planarization for semiconductor device

Publications (1)

Publication Number Publication Date
KR20030050782A true KR20030050782A (en) 2003-06-25

Family

ID=29576482

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010081300A KR20030050782A (en) 2001-12-19 2001-12-19 Method of planarization for semiconductor device

Country Status (1)

Country Link
KR (1) KR20030050782A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100606133B1 (en) * 2004-12-30 2006-07-31 동부일렉트로닉스 주식회사 Cu Chemical Mechanical Planarization of Semiconductor Wafer
US8974655B2 (en) 2008-03-24 2015-03-10 Micron Technology, Inc. Methods of planarization and electro-chemical mechanical polishing processes

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980028648A (en) * 1996-10-23 1998-07-15 김광호 Cleaning method
US5996594A (en) * 1994-11-30 1999-12-07 Texas Instruments Incorporated Post-chemical mechanical planarization clean-up process using post-polish scrubbing
US6074949A (en) * 1998-11-25 2000-06-13 Advanced Micro Devices, Inc. Method of preventing copper dendrite formation and growth
JP2000315668A (en) * 1999-04-30 2000-11-14 Shin Etsu Handotai Co Ltd Polishing method and cleaning method of wafer and protection film
US6218290B1 (en) * 1998-11-25 2001-04-17 Advanced Micro Devices, Inc. Copper dendrite prevention by chemical removal of dielectric
JP2001156029A (en) * 1999-08-23 2001-06-08 Applied Materials Inc POST Cu CMP POLISHING FOR REDUCED DEFECTS
KR20020063732A (en) * 2001-01-30 2002-08-05 주식회사 하이닉스반도체 A chemical and mechanical polishing method of wafer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5996594A (en) * 1994-11-30 1999-12-07 Texas Instruments Incorporated Post-chemical mechanical planarization clean-up process using post-polish scrubbing
KR19980028648A (en) * 1996-10-23 1998-07-15 김광호 Cleaning method
US6074949A (en) * 1998-11-25 2000-06-13 Advanced Micro Devices, Inc. Method of preventing copper dendrite formation and growth
US6218290B1 (en) * 1998-11-25 2001-04-17 Advanced Micro Devices, Inc. Copper dendrite prevention by chemical removal of dielectric
JP2000315668A (en) * 1999-04-30 2000-11-14 Shin Etsu Handotai Co Ltd Polishing method and cleaning method of wafer and protection film
JP2001156029A (en) * 1999-08-23 2001-06-08 Applied Materials Inc POST Cu CMP POLISHING FOR REDUCED DEFECTS
KR20020063732A (en) * 2001-01-30 2002-08-05 주식회사 하이닉스반도체 A chemical and mechanical polishing method of wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100606133B1 (en) * 2004-12-30 2006-07-31 동부일렉트로닉스 주식회사 Cu Chemical Mechanical Planarization of Semiconductor Wafer
US8974655B2 (en) 2008-03-24 2015-03-10 Micron Technology, Inc. Methods of planarization and electro-chemical mechanical polishing processes

Similar Documents

Publication Publication Date Title
KR100873759B1 (en) Manufacturing Method of Semiconductor Integrated Circuit Device
JP3344615B2 (en) Method for manufacturing semiconductor device
KR100570060B1 (en) Method for forming landing plug contact in semiconductor device
US20070161203A1 (en) Method with high gapfill capability and resulting device structure
KR100382727B1 (en) Method for fabricating pad without void using self-aligned contact etch process in semiconductor device
US6451698B1 (en) System and method for preventing electrochemical erosion by depositing a protective film
JPH10214809A (en) Manufacture of semiconductor device
US6001708A (en) Method for fabricating a shallow trench isolation structure using chemical-mechanical polishing
US6190999B1 (en) Method for fabricating a shallow trench isolation structure
KR20030050782A (en) Method of planarization for semiconductor device
US6265325B1 (en) Method for fabricating dual gate dielectric layers
US9768064B1 (en) Formation method of semiconductor device structure
US6087262A (en) Method for manufacturing shallow trench isolation structure
US6133114A (en) Method for fabricating a shallow trench isolation
JP4966116B2 (en) Manufacturing method of semiconductor integrated circuit device
JPH10180619A (en) Grinding agent, grinding method and manufacture of semiconductor device
KR100390838B1 (en) Method for forming landing plug contact in semiconductor device
KR100732309B1 (en) Manufacturing method for semiconductor device
KR100732308B1 (en) Method for chemical mechanical polishing of semiconductor device
KR100474856B1 (en) Method of cleaning in a semiconductor device
KR100403197B1 (en) Method of forming a metal wiring in a semiconductor device
KR100451986B1 (en) Method for forming strage node contact plug of semiconductor device
KR100574912B1 (en) Meta wiring structure body protecting metal bridge due to scratch by chemical mechanical polishing on insulating layer, for semiconductor device &amp;manufacturing method thereof
KR100431815B1 (en) Manufacturing method of semiconductor device
KR101175275B1 (en) Method for forming landing plug contact in semiconductor device

Legal Events

Date Code Title Description
N231 Notification of change of applicant
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application