KR20030049570A - Method for forming metal line of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a metal wiring in a semiconductor device is provided to be capable of preventing defects due to photoresist residues and bridge between metal lines. CONSTITUTION: The first etch stop layer(22), the first insulating layer(23), the second etch stop layer(24), the second insulating layer(25) and the third etch stop layer are sequentially formed on a semiconductor substrate(21). The third etch stop layer is selectively etched using the first photoresist pattern for defining a contact region. After removing the first photoresist pattern, the exposed third etch stop layer, the second insulating layer(25) and the second etch stop layer(24) are selectively etched using the second photoresist pattern for defining a metal wiring region. After removing the second photoresist pattern, a trench and a contact hole are simultaneously formed. A metal wiring(29) is then formed by filling a metal film into the contact hole and the trench and polishing the metal film.

Description

METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE

The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to a method for forming a metal wiring by forming a contact hole and a metal wiring trench at the same time using a high etching selectivity between the photosensitive film, the insulating film and the etch stop film. It is about.

As the degree of integration of semiconductor memory devices increases, memory cells are stacked in structure, and thus, metal wiring diagrams for electrical connection between the cells are formed in a multi-layer structure that can facilitate wiring design. Such a multilayer metal wiring structure has advantages in that the wiring design can be freely set and the setting of the wiring resistance and the current capacity can be made free.

Meanwhile, aluminum (Al) or an alloy film thereof having relatively high electrical conductivity has been mainly used as a metal wiring material, and recently, studies have been conducted to use tungsten as well as copper (Cu) having better electrical conductivity than aluminum. .

Hereinafter, a conventional metallization process will be described schematically.

First, in a state in which a first metal film is deposited on a semiconductor substrate on which a predetermined base layer such as a transistor is formed, a photoresist pattern is formed on the first metal film through a known photolithography process, and covered by the photoresist pattern. A portion of the first metal film that is not supported is etched to form a lower metal wiring.

Then, after removing the photoresist pattern used as an etch mask, an oxide film is deposited by HDP (High Density Plasma) deposition on the entire area of the substrate to cover the lower metal wiring, and then chemical mechanical polishing (CMP). The surface is ground by a step to form an interlayer insulating film having a flat surface.

Next, a portion of the interlayer insulating film is selectively etched to form a contact hole exposing the lower metal wiring, and then a tungsten film is deposited on the interlayer insulating film to completely fill the contact hole, and then the tungsten film is polished to A contact plug in electrical contact with the lower metal wire is formed in the contact hole.

Then, after depositing the second metal film on the contact plug and the interlayer insulating film, the formation of the photoresist pattern through the photolithography process, the etching of the second metal film using the photoresist pattern and the removal of the photoresist pattern in order to perform the contact By forming the upper metal wiring in contact with the plug, the multilayer metal wiring structure is completed.

However, in the case of forming the metal wiring according to the related art, as shown in FIG. 1, a bridge 10 between adjacent metal wirings 4 is formed after dry etching of the metal film with respect to the etching characteristics of the metal film. In addition, there is a problem that the metal film remains in the form of a compound, which adversely affects the electrical characteristics of the device. In particular, this problem is expected to be more serious as the integration of semiconductor devices proceeds.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate, 2 an interlayer insulating film, and 3 a contact plug, respectively.

Meanwhile, in order to solve the above problem, a multilayer metallization process using a damascene, in particular, a dual-damascene process has been proposed. By the way, although not shown and described in detail, in the case of the conventional dual-damacin process, another defect may occur due to the photoresist residue, and thus, there is a difficulty in using the same.

Accordingly, the present invention has been made to solve the above problems, a method of forming a metal wiring of a semiconductor device capable of preventing the occurrence of defects in the process due to the photoresist residue while preventing the bridge between neighboring metal wirings. The purpose is to provide.

1 is a view for explaining a conventional problem.

2A to 2G are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 first etching stop film

23: first insulating film 24: second etching stop film

25: second insulating film 26: third etching stop film

27; First photoresist pattern 28: Second photoresist pattern

29: metal wiring C: contact hole

T: Trench

In order to achieve the above object, the metal wire forming method of the present invention includes a first etch stop film, a first insulating film, a second etch stop film, a second insulating film, and a third etch stop on a semiconductor substrate provided with an underlayer. Sequentially forming the films; Forming a first photoresist pattern defining a contact region on the third etch stop layer, and etching the third etch stop layer by using the first photoresist pattern; Removing the first photoresist pattern; Forming a second photoresist pattern defining a metal wiring region on the third etch stop layer, and using the second photoresist pattern, the portion of the third etch stop layer and the second insulating layer and the second etch stop below Etching the membrane portion; Removing the second photoresist pattern; Blanket etching is performed on the resultant up to the step to etch the second insulating film portion not covered by the third etching stop film and the third etching stop film, and the second etching stop film portion below the metal wiring by etching. Forming a trench to be formed and simultaneously forming a contact hole exposing the substrate by etching the exposed first insulating film portion and the first etch stop film portion below it; Depositing a metal film on the resultant material to fill the contact hole and the trench; And polishing the metal film until the second insulating film is exposed.

Here, the first and second etch stop layer is made of SiON or Si 3 N 4, it is formed to a thickness of 500 ~ 1,000Å. The third etch stop layer is made of TaN, SiON, and Si3N4, and is formed to a thickness of 1,000 to 1500 Å. The first and second insulating layers are formed of oxide films deposited by HDP.

According to the present invention, by using a dual damascene process, by using a high etching selectivity between the photoresist, the insulating film and the anti-etching film, it is possible to prevent the generation of bridges between adjacent metal wirings, and also to the photoresist residue The occurrence of defects can be prevented.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views of processes for describing a method of forming a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a semiconductor substrate 21 having a lower metal wiring (not shown) is formed by depositing and patterning a predetermined underlayer, for example, a metal film. Then, the first etch stop layer 22, the first insulating layer 23, the second etch stop layer 24, the second insulating layer 25, and the third etch stop are formed over the entire region of the semiconductor substrate 21. The film 26 is formed in turn.

The first etch stop layer 22 is used to perform an etch stop function for anisotropic etching of the substrate, and is formed by depositing a material such as SiON and Si 3 N 4 to a thickness of 500 to 1,000 Å. The two-etch stop film 24 is also formed by depositing SiON, Si 3 N 4, or the like to a thickness of 500 to 1,000 GPa. The first and second insulating layers 23 and 25 are formed by the HDP method. The third etch stop layer 26 functions as an etch blocking layer, and is formed by depositing a material such as TaN, SiON, and Si 3 N 4 to a thickness of 1,000 to 1500 Å.

Referring to FIG. 2B, a first photoresist layer pattern 27 defining a contact formation region is formed by sequentially depositing, exposing and developing a photoresist layer on the third etch stop layer 26. Thereafter, the exposed portion of the third etch stop layer is etched away using the first photoresist pattern 27 as an etch mask.

Referring to FIG. 2C, in a state in which the first photoresist layer pattern used as an etching mask is removed, a photoresist forming region including a contact formation region may be defined by sequentially applying, exposing and developing the photoresist layer on the resultant. The two photosensitive film patterns 28 are formed.

Referring to FIG. 2D, anisotropic etching is performed on the resultant product by using the second photoresist pattern 28. In this process, the exposed third etch stop layer is etched by the width of the metal wiring, and the exposed second insulating film portion and the lower portion of the second etch stop layer are etched together by the size of the contact hole.

Referring to FIGS. 2E and 2F, a blanket etch is performed on the resultant up to this step in a state in which the second photoresist pattern used as an etching mask is removed. In this process, the third etch stop layer is completely etched away to expose the second insulating layer 25, and the portion of the second insulating layer that is not covered by the third etch stop layer is etched, as well as the second etched portion thereunder. The trench T is defined to define the region where the stop layer is to be etched to form the metal wiring, and at the same time, the exposed first insulating layer is etched, and the first etch stop layer below is etched to lower the metal wiring. Alternatively, a contact hole C exposing a predetermined region of the substrate is formed.

Referring to FIG. 2G, after cleaning the resultant, a metal film of aluminum, copper, tungsten, or the like is deposited to completely fill the contact hole C and the trench T, and then, a second The metal film 29 of the present invention is electrically contacted with the substrate or the lower metal wiring in the contact hole C and the trench T by polishing the metal film by the CMP process until the insulating film 25 is exposed. Complete

According to the metal wiring forming method of the present invention as described above, first, since the metal wiring is formed through the damascene process, bridge generation between adjacent metal wirings does not occur fundamentally; By forming the contact holes and trenches by using the etching selectivity between the etch stop layer made of SiON or Si3N4 and the insulating film made of oxide, the etching profile of the trenches and contact holes is improved without defects caused by photoresist residues. can do.

As described above, the present invention uses a dual-damacin process, but instead of etching using a photoresist film, the contact hole and the metal wiring forming region are defined using a material having a high etching selectivity with an HDP oxide film. It is possible to secure process margins, such as to prevent defects, and to improve the etching profile of the contact holes and trenches, thereby improving the reliability of the metal wiring.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (6)

Sequentially forming a first etch stop layer, a first etch stop layer, a second etch stop layer, a second etch stop layer, and a third etch stop layer on the semiconductor substrate including the underlayer; Forming a first photoresist pattern defining a contact region on the third etch stop layer, and etching the third etch stop layer by using the first photoresist pattern; Removing the first photoresist pattern; Forming a second photoresist pattern defining a metal wiring region on the third etch stop layer, and using the second photoresist pattern, the portion of the third etch stop layer and the second insulating layer and the second etch stop below Etching the membrane portion; Removing the second photoresist pattern; Blanket etching is performed on the resultant up to the step to etch the second insulating film portion not covered by the third etching stop film and the third etching stop film, and the second etching stop film portion below the metal wiring by etching. Forming a trench to be formed and simultaneously forming a contact hole exposing the substrate by etching the exposed first insulating film portion and the first etch stop film portion below it; Depositing a metal film on the resultant material to fill the contact hole and the trench; And And polishing the metal layer until the second insulating layer is exposed. The method of claim 1, wherein the first and second etch stop layers comprise SiON or Si 3 N 4. 3. The method of claim 1 or 2, wherein the first and second etch stop layers are formed to a thickness of 500 to 1,000 GPa. The method of claim 1, wherein the third etch stop layer is one selected from the group consisting of TaN, SiON, and Si 3 N 4. 5. The method of claim 1 or 4, wherein the third etch stop layer is formed to a thickness of 1,000 to 1500 Å. The method of claim 1, wherein the first and second insulating layers are oxide films deposited by HDP (High Density Plasma).