KR20030046116A - Media access controller for wireless lan - Google Patents

Abstract

PURPOSE: An MAC(Media Access Controller) for a wireless LAN is provided to transceive data signals and control signals with a baseband processor, thereby feeding back the transceived signals without connecting the baseband processor to the MAC. CONSTITUTION: A transmitter(120) outputs data signals to be transmitted to a baseband processor(200). A receiver(140) receives the data signals received from the baseband processor(200). A main processor interface transceives the data signals and control signals through the first GPIO(General Purpose Input Output) port(130), and transmits the data signals to the receiver(140) through the second GPIO port(150). The first loopback circuit(160) transmits the control signals to the transmitter(120), and transmits the data and the control signals to the first GPIO register(165). The second loopback circuit(170) transmits the data and the control signals to the receiver(140), and transmits the control signals to the second GPIO register(175).

Description

MEDIA ACCESS CONTROLLER FOR WIRELESS LAN}

The present invention relates to a wireless LAN, and more particularly, to a media access controller (MAC) for a wireless LAN having a loop-back circuit capable of feeding back signals transmitted and received.

The loop-back circuit is a circuit that can check the operation of the chip itself without connecting to the outside by connecting the transmitting side and the receiving side inside the chip. In other words, it is a very useful circuit in the initial test because it is possible to check the normal operation of the internal functions of the chip without the external signal transceiver.

FIG. 1 is a diagram illustrating a configuration of a media access controller (hereinafter, referred to as a MAC) of a typical wired LAN. Referring to FIG. 1, the MAC 10 includes a buffered DMA interface (BMI) 11, a transmitter 12, a receiver 13, a transmission interface 14, a reception interface 15, and a loop-back circuit 16. ). The loop-back circuit 16 consists of a multiplexer 17 and a register 18.

The MAC 10 of the wired LAN having such a configuration performs a general data transmission / reception operation when the in-signal data EN stored in the register 18 is logic '0', and the in-signal stored in the register 18. When the data EN is a logic '1', the signal output from the transmitter 12 is received by the receiver 13 through the loop-back circuit 16. Therefore, whether the internal circuit of the MAC 10 operates normally can be determined in an easy manner. By the way, this technology is generalized in the MAC controller of the wired LAN but is not supported by the MAC controller of the wireless LAN. The reason for this is as follows.

2 is a diagram illustrating a configuration of a MAC provided in a general wireless LAN. The MAC as shown in Fig. 2 is a common circuit configuration such as HFA3842A [2] of Intersil Corporation and AT76C502A [3] of Atmel Corporation. Referring to FIG. 2, the MAC 20 for a wireless LAN includes an ARM bus architecture (AMBA) interface 21, a transmitter 22, a receiver 23, and a baseband interface 24. The baseband interface 24 is connected to a baseband processor 30 that converts digital data into an analog radio signal, and the AMBA interface 21 is connected to an advanced RISC machines (ARM) processor.

During the transmission mode, the signal output through the AMBA interface 21 is provided to the baseband processor 30 via the transmitter 22 and the baseband interface 24. On the other hand, during the reception mode, the signal received from the baseband processor 30 is provided to the AMBA interface 21 through the baseband interface 24 and the receiver 23. Signal transmission and reception between the wireless LAN MAC 20 and the baseband processor 30 having such a configuration is performed by a handshaking method.

3A is a timing diagram showing signals transmitted and received between two chips when transmitting data from Intersil HFA3842A [2], a representative chip of a wireless LAN MAC, to a baseband processor.

Referring to FIG. 3A, when the transmitter 22 activates the control signal BBTXPE from the low level to the high level, the baseband processor 30 receiving the high level control signal BBTXPE activates the control signal TXRDY. As the control signal TXRDY is activated, the transmission clock signal TXCLK is supplied, and the data TXDATA is transmitted to the baseband processor 30 through the baseband interface 24. When data transmission is completed, the transmitter 22 deactivates the control signal BBTXPE to a low level. As the control signal BBTXPE from the MAC 20 is deactivated, the baseband processor 30 deactivates the control signal TXRDY to a low level. Thus, data transmission from the MAC 20 to the baseband processor 30 is terminated.

FIG. 3B is a timing diagram showing signals transmitted and received between two chips when transmitting data from ATmel's MAC AT76C502A [3] to RFMD's baseband processor RF300 [4].

Referring to FIG. 3B, as the transmitter 22 activates the control signal BBTXPE from the low level to the high level, the baseband processor 30 activates the control signal TXRDY from the low level to the high level. As the control signal TXRDY is activated, the transmission clock signal TXCLK is supplied, and the data TXDATA is transmitted to the baseband processor 30. When the data transmission is completed, the baseband processor 30 deactivates the control signal TXRDY to the low level, and as the control signal TXRDY is deactivated, the transmitter 22 deactivates the control signal BBTXPE to the low level. Thus, data transmission from the MAC 20 to the baseband processor 30 is terminated.

As described above, in the wired LAN MAC controller, having a loop-back circuit is a generalized technology, but the MAC controller of the wireless LAN is not supported. The reason is that, unlike wired LAN, signal exchange between wireless LAN MAC and baseband processor is done by handshaking method, and it is not realized by simple signal connection. Second, the MAC-PHY interface of wireless LAN is manufactured by each company. This is because it is different from each other, so it is difficult to generalize it.

Since the signal transmission / reception relations between the WLAN MAC and the baseband processor are slightly different between manufacturers, it is difficult to have a generalized loop-back circuit in the WLAN MAC.

Accordingly, an object of the present invention is to provide a medium access controller (MAC) for a wireless LAN having a loop-back circuit capable of feeding back signals transmitted and received.

1 is a diagram illustrating a configuration of a media access controller (hereinafter, referred to as a MAC) of a typical wired LAN.

2 is a diagram illustrating a configuration of a MAC provided in a general wireless LAN;

FIG. 3A is a timing diagram showing signals transmitted and received between two chips when transmitting data from Intersil's HFA3842A [2], a representative chip of a MAC for wireless LAN, to a baseband processor; FIG.

4 is a view showing the configuration of a MAC for a wireless LAN according to a preferred embodiment of the present invention;

FIG. 5 is a flowchart showing a control procedure of an AMBA interface for testing a transmission operation of the MAC shown in FIG. 4, that is, for transmission loop-back; FIG. And

FIG. 6 is a flowchart illustrating a control procedure of an AMBA interface for testing a reception operation of the MAC illustrated in FIG. 4, that is, for reception loop-back.

* Description of the main parts of the drawings *

100: media access controller 110: AMBA interface

120: transmitter 130, 150: GPIO port

140: receiver 160: transmit loop-back circuit

170: receive loop-back circuit 180: baseband interface

190: input and output interface 200: baseband processor

(Configuration)

A wireless LAN media access controller for transmitting and receiving data signals and control signals with a baseband processor for achieving the above object includes: a transmitter for outputting the data signal to be transmitted to the baseband processor, received from the baseband processor A receiver for receiving the data signal, coupled to first and second general purpose input output (GPIO) ports, and transmitting and receiving the data signal and the control signal through the first GPIO port during a transmit loop-back mode; A main processor interface for transmitting the data signal to the receiver via the second GPIO port during loop-back mode, transmitting the control signals from the first GPIO register to the transmitter during the transmit loop-back mode, and The data signal from the transmitter and the control scene A first loop-back circuit for transmitting a signal to the first GPIO register and the data signals and control signals from the second GPIO register to the receiver during the receive loop-back mode, and the control from the receiver. And a second loop-back circuit for passing a signal to the second GPIO register.

In a preferred embodiment, the first loop-back circuit provides the control signals from the baseband processor to the transmitter during normal transmission mode.

In a preferred embodiment, the second loop-back circuit provides the data signal from the baseband processor to the receiver during normal reception mode.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a configuration of a MAC for a wireless LAN according to a preferred embodiment of the present invention. Referring to FIG. 4, the MAC 100 for a wireless LAN includes an ARM bus architecture (AMBA) interface 110, a transmitter 120, GPIO ports 130 and 150, a receiver 140, and a loop-back circuit for transmission ( 160, the reception loop-back circuit 170, the baseband interface 180, and the input / output interface 190.

Most MACs include GPIO ports 130 and 150 that can be used in various ways depending on the user's needs. In the present invention, the loop-back circuit is implemented by using the GPIO ports 130 and 150.

The transmit loop-back circuit 160 consists of multiplexers 161-164 and a register 165. The register 165 stores transmission mode information TXEN indicating whether the transmission loop-back mode or the normal transmission mode. For example, a value stored in the register 165 is '1' to indicate a transmit loop-back mode, and '0' to indicate a normal transmit mode.

The multiplexers 161-164 operate in response to the transmission mode information TXEN stored in the register 165. That is, when the transmission mode information TXEN is '1', the control signal BBTXPE and the data signal BBTXDATA output from the transmitter 120 are input to the GPIO port 130 through the multiplexers 161 and 162. The control signal and the clock signal output from the GPIO port 130 are provided to the transmitter 120 through the multiplexers 163 and 164. When the transmission mode information TXEN is '0', the GPIO port 130 is connected to the input / output interface 190 to operate in the normal mode, and is controlled from the baseband processor 200 through the baseband interface 180. The signal and the clock signal are provided to the transmitter 120 through the multiplexers 163 and 164.

The receive loop-back circuit 170 is composed of multiplexers 171-174 and a register 175. The register 175 stores the reception mode information RXEN indicating whether the reception loop-back mode or the normal reception mode is used. For example, if a value stored in the register 175 is '1', it indicates a receive loop-back mode, and '0' indicates a normal receive mode.

The multiplexers 171-174 operate in response to the receive mode information RXEN stored in the register 175. That is, when the reception mode information RXEN is '1', the control signal BBRXPE output from the reception unit 140 is transmitted to the GPIO port 150 through the multiplexer 171 and output from the GPIO port 150. The data, control signal, and clock signal are provided to the receiver 140 through the multiplexers 172-174. On the other hand, when the reception mode information RXEN is '0', the GPIO port 150 is connected to the input / output interface 190 to operate in the normal mode, and from the baseband processor 200 through the baseband interface 180. The input data signal, the control signal, and the clock signal are provided to the receiver 140 through the multiplexers 172-174.

Control of the AMBA interface 110 included in the WLAN MAC having the above-described configuration will be described with reference to FIGS. 5 and 6.

FIG. 5 is a flowchart showing the control procedure of the AMBA interface 110 for transmission loop-back when testing the transmission operation of the MAC 100 shown in FIG. However, the transmission mode information TXEN stored in the register 165 during the transmission loop-back mode is '1'.

In step S100, the AMBA interface 110 initializes the transmitter 120 and the GPIO port 130.

In operation S110, the AMBA interface 110 transmits a data signal through the transmitter 120. At this time, since the transmission mode information TXEN stored in the register 165 is '1', the control signal BBTXPE and the data signal BBTXDATA output from the transmitter 120 are connected to the GPIO port through the multiplexers 161 and 162. The control signals transmitted to the 130 and output from the GPIO port 130 are transmitted to the transmitter 120. In operation S120, the AMBA interface 110 receives signals output from the transmitter 120 through the GPIO port 130. In operation S130, the AMBA interface 110 compares the data signal output to the transmitter 120 with the data signal input through the GPIO port 130.

FIG. 6 is a flowchart showing a control procedure of the AMBA interface 110 for receiving loop-back when testing the receiving operation of the MAC 100 shown in FIG. However, the reception mode information RXEN stored in the register 175 during the reception loop-back mode is '1'.

In step S200, the AMBA interface 110 initializes the receiver 140 and the GPIO port 150.

In step S210, the AMBA interface 110 transmits a data signal through the GPIO port 150. At this time, since the reception mode information RXEN stored in the register 175 is '1', the control signal and the data signal output from the GPIO port 150 are transmitted to the receiver 140 through the multiplexers 172, 173, and 174. The control signal BBRXPE that is transmitted and output from the receiver 140 is transferred to the GPIO port 150. In step S220, the AMBA interface 110 receives signals output from the GPIO port 150 through the receiver 140. In operation S230, the AMBA interface 110 compares the data signal output through the GPIO port 150 with the data signal input through the receiver 140.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

According to the present invention, it is possible to feed back signals transmitted and received without connecting a baseband processor to a medium access controller (MAC).

Claims (3)

In a media access controller for a wireless LAN that sends and receives data signals and control signals with a baseband processor: A transmitter for outputting the data signal to be transmitted to the baseband processor; A receiving unit which receives the data signal received from the baseband processor; Connects to first and second general purpose input output (GPIO) ports and transmits and receives the data signal and the control signal through the first GPIO port during transmit loop-back mode and the second during receive loop-back mode. A main processor interface for transmitting the data signal to the receiving unit through a GPIO port; A first loop-back circuit for transferring the control signals from the first GPIO register to the transmitter and transmitting the data signal and the control signal from the transmitter to the first GPIO register during the transmit loop-back mode ; And A second loop-back circuit for transferring the data signals and control signals from the second GPIO register to the receiver and the control signal from the receiver to the second GPIO register during the receive loop-back mode; Media access controller for a wireless LAN comprising a. The method of claim 1, And wherein the first loop-back circuit provides the control signals from the baseband processor to the transmitter during a normal transmission mode. The method of claim 1, And the second loop-back circuit provides the data signal from the baseband processor to the receiver during normal reception mode.