KR20030037572A - Interrupt controller - Google Patents

Abstract

PURPOSE: An interrupt controller is provided to transmit an interrupt request signal to a CPU for an ARM(Advanced RISC Machines) instruction model only when an interrupt request exists from an interrupt source prior to the currently processed interrupt source. CONSTITUTION: An interrupt controller(10) generates an interrupt request signal(nIRQ) by responding to interrupt requests of the 'n' number of interrupt sources(SOURCE0-SOURCEn-1). An interrupt register(11) includes the 'n' number of bits corresponded to the 'n' number of interrupt sources(SOURCE0-SOURCEn-1). The bits are set individually in accordance with an interrupt request of corresponding interrupt source. When an interrupt is requested from the interrupt source, a bit corresponded to the interrupt register(11) is set as '1'. A priority is decided by a position of a bit of a register. For example, an interrupt source corresponded to the '0'th bit of the interrupt register(11) has the highest priority. Also, an interrupt source corresponded to the 'n'th bit of the interrupt register(11) has the lowest priority. Each bit of the interrupt register(11) is inputted to an interrupt request signal generator(12).

Description

Interrupt Controller {INTERRUPT CONTROLLER}

The present invention relates to an interrupt controller, and more particularly, to an interrupt controller capable of interrupt nesting in an instruction model of ARM (Advanced RISC Machines).

An interrupt is an asynchronous event that interrupts normal processing and executes an interrupt handler routine (or interrupt service routine). Interrupts are generated by hardware such as input / output devices, timers, and machinechecks, and by hardware such as supervisors, system call or trap instructions. do.

The instruction model of Advanced RISC Machines (ARM) sets the I flag of the current program status register (CPSR) to 1 before processing the interrupt service routine. Next, the I flag of the current program status register (CPSR) must be changed from 1 to 0 for interrupt nesting.

On the other hand, in order to prevent an interrupt from being generated by an interrupt source having a lower priority than the interrupt service routine currently being executed, the interrupts having a lower priority than the interrupt service routine currently being executed are disabled one by one. . This method had a problem in that each interrupt service routine had to be aware of all interrupts lower than itself. This is because the ARM instruction models do not support interrupt nesting.

Accordingly, an object of the present invention is to solve the above-described problems, an interrupt for the ARM instruction model that transmits an interrupt request signal to the CPU only when there is an interrupt request from an interrupt source having a higher priority than the interrupt source currently being processed. To provide a controller.

1 shows the configuration of an interrupt controller according to a preferred embodiment of the present invention; And

FIG. 2 is a flowchart showing a control procedure for enabling / disabling an interrupt request signal by the interrupt controller shown in FIG. 1.

10: interrupt controller 11: interrupt register

12: interrupt request signal generator 13: virtual interrupt generator

20: register

(Configuration)

In accordance with one aspect of the present invention for achieving the above object, an interrupt controller is configured to determine an interrupt source being serviced by the processor when the processor is executing an interrupt service routine in response to an interrupt request from a predetermined interrupt source. Generate a virtual interrupt having a priority higher than the priority, and activate an interrupt request signal to the processor when there is an interrupt request from an interrupt source having a higher priority than the virtual interrupt among the interrupt sources.

In particular, the priority of the virtual interrupt is one step above the priority of the interrupt source being serviced by the processor.

According to another aspect of the invention, an interrupt controller comprises: a first register, each of which comprises bits corresponding to a plurality of interrupt sources, each of which is individually set according to an interrupt request from a corresponding interrupt source; A second register for storing information of an interrupt source in service, a virtual interrupt generator for generating a virtual interrupt having a higher priority than the priority of the currently serving interrupt source stored in the second register, and of the first register And an interrupt request signal generator that accepts the bits and the virtual interrupt and activates an interrupt request signal when a bit of the first register having a higher priority than the virtual interrupt is set.

In this embodiment, the interrupt request signal generator activates the interrupt request signal when at least one of the bits of the first register is set when the virtual interrupt is not input from the virtual interrupt generator.

In this embodiment, the priority of the virtual interrupt is one step higher than the priority of the currently serving interrupt source stored in the second register.

(Example)

The interrupt controller of the present invention generates a virtual interrupt having a priority higher than that of an interrupt source being serviced by the processor when the processor is executing an interrupt service routine in response to an interrupt request from a predetermined interrupt source, The interrupt request signal is activated to the processor when an interrupt request is received from an interrupt source having a higher priority than the virtual interrupt among the interrupt sources. This eliminates the need for each of the conventional interrupt service routines for interrupt nesting to know information about interrupts with a lower priority than themselves, and the interrupt to be executed before the CPU performs the interrupt service routine. There is no need to disable interrupts of lower priority than routines.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings, FIGS. 1 and 2.

1 is a diagram illustrating a configuration of an interrupt controller according to a preferred embodiment of the present invention.

Referring to FIG. 1, the interrupt controller 10 includes an interrupt register 11, a priority determination circuit 12, and a virtual interrupt generator 13. The interrupt controller 10 shown in FIG. 1 generates an interrupt request signal nIRQ in response to interrupt requests from n interrupt sources.

Referring to FIG. 1, the interrupt register 11 includes n bits corresponding to n interrupt sources SOURCE0 to SOURCEn-1, respectively. The bits can be set individually according to the interrupt request of the corresponding interrupt source. For example, when there is an interrupt request from an interrupt source, the corresponding bit in register 11 is set to '1'. The priority is determined by the position of the bits in this register. For example, the interrupt source corresponding to the 0th bit of the register 11 has the highest priority, and the interrupt source corresponding to the nth bit of the register 11 has the lowest priority. Each bit of the register 11 is input to an interrupt request signal generator 12.

FIG. 2 is a flowchart showing a control procedure by which the interrupt controller 10 shown in FIG. 1 activates / deactivates the interrupt request signal nIRQ.

2, in step S100, the interrupt request signal generator 12 receives the bits of the interrupt register 11 to determine whether an interrupt has occurred. If at least one of the bits of the register 11 is set (i.e., '1') as a result of the determination, the control proceeds to step S101. In step S101, the interrupt request signal generator 12 activates the interrupt request signal nIRQ. The enabled interrupt request signal nIRQ is provided to the CPU (not shown).

When there are interrupt requests from several interrupt sources at the same time, they are processed sequentially according to the interrupt priority. ARM microprocessors provide only two interrupts: a fast interrupt request (FIQ) and a slow interrupt request (IRQ). Thus, microprocessors, which typically have dozens of interrupt sources, employ software or hardware methods to increase the number of interrupts and check interrupt priority. In the case of using the software method, hardware cost is advantageous, but the performance deterioration has to be so much that priority checking by hardware is widely used in many products. The method of checking interrupt priority by hardware varies from design to design. The priority checking method includes a method of loading an address which becomes an interrupt service routine from a special purpose register (SFR) into a program counter register, an interrupt service routine by intercepting an instruction read from an external memory by a specific address and manipulating an instruction field. How to go to.

The CPU that receives the interrupt request signal nIRQ from the interrupt controller 10 performs an interrupt service routine corresponding to the interrupt source selected according to the priority.

In step S102, the interrupt request signal generator 12 determines whether an interrupt response signal nINTACK activated from the CPU is received. As a result of the determination, when the interrupt response signal nINTACK activated from the CPU is received, the control proceeds to step S103. In step S103, the interrupt request signal generator 12 deactivates the interrupt request signal nIRQ. On the other hand, information on the interrupt source currently being serviced by the CPU is stored in the register 20.

In step S104, the virtual interrupt generator 13 generates a virtual interrupt V_INT having a priority higher than the priority of the current interrupt source stored in the register 20.

In step S105, the interrupt request signal generator 12 performs a priority comparison operation when any one of the bits of the interrupt register 11 is set while the virtual interrupt V_INT from the virtual interrupt generator 13 is input. . If the priority of the virtual interrupt V_INT from the virtual interrupt generator 13 is lower than the priority of the set bit of the interrupt register 11, the control is terminated, and the virtual interrupt from the virtual interrupt generator 13 ( If the priority of V_INT) is higher than the priority of the set bit of the interrupt register 11, the control proceeds to step S106. In step S106, the interrupt request signal generator 12 activates the interrupt request signal nIRQ. As the interrupt request signal nIRQ is activated, the CPU may perform an interrupt nesting operation that stops an interrupt in service and services a new interrupt.

The interrupt controller 10 of the present invention as described above enables interrupt nesting only with information on the interrupt currently being serviced. This eliminates the hassle of each conventional interrupt service routine having to know information about interrupts of lower priority than itself, and has a higher priority than the interrupt routine currently being serviced before the CPU can service the interrupt service routine. There is no need to disable low interrupts.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

According to the present invention as described above, the inconvenience that each of the conventional interrupt service routines need to know information about interrupts lower than itself in advance is eliminated, and the interrupt to be executed before the CPU performs the interrupt service routine. There is no need to disable interrupts of lower priority than routines.

Claims (5)

A method of controlling an interrupt controller when a processor is executing an interrupt service routine in response to an interrupt request from a predetermined interrupt source: Generating a virtual interrupt having a priority higher than that of an interrupt source being serviced by the processor; And Activating an interrupt request signal to the processor when an interrupt request is received from an interrupt source having a higher priority than the virtual interrupt among the interrupt sources. The method of claim 1, The priority of the virtual interrupt is one step higher than the priority of the interrupt source being serviced by the processor. For interrupt controllers: A first register comprising bits corresponding respectively to a plurality of interrupt sources, each of the bits being individually set according to an interrupt request from a corresponding interrupt source; A second register for storing information of an interrupt source currently in service; A virtual interrupt generator for generating a virtual interrupt having a higher priority than a priority of the currently serving interrupt source stored in the second register; And And an interrupt request signal generator which accepts the bits of the first register and the virtual interrupt and activates an interrupt request signal when a bit of the first register having a higher priority than the virtual interrupt is set. Interrupt controller. The method of claim 3, wherein And the interrupt request signal generator activates the interrupt request signal when at least one of the bits of the first register is set when the virtual interrupt is not input from the virtual interrupt generator. The method of claim 3, wherein The priority of the virtual interrupt is one step higher than the priority of the currently serving interrupt source stored in the second register.