KR20030024238A - Apparatus and control method for framer of ATU-C - Google Patents

Abstract

PURPOSE: An ATU-C(ADSL(Asynchronous Digital Subscriber Line) Terminal Unit-Office) framer device and a control method therefor are provided to be applied to an STM(Synchronous Transfer Mode) and ATM(Asynchronous Transfer Mode) transmission and effectively reduce a payload transfer delay. CONSTITUTION: FIFOs(32) temporarily store parallel data of a downstream channel. A DSP(Digital Signal Processor)(33) outputs a 'transmission speed(BF(the number of bytes of a fast buffer),BI(the number of bytes of an interleaved buffer))' signal, a 'start' signal, and a 'mode(framing structure number)' signal determined after training an ADSL line state. A framer controller(34) receives the 'start' signal, the 'transmission speed' signal, and the 'mode' signal from the DSP(33), and controls the FIFOs(32) so that a variable optimum value about a pointer value to be recognized as a 'normal flag' of the FIFOs(32) is determined and data of the FIFOs(32) are transmitted.

Description

ATI-C framer device and its control method {Apparatus and control method for framer of ATU-C}

The present invention relates to an ADSL Terminal Unit Central Office (ATU-C) of an Asynchronous Digital Subscriber Line (ADSL) system. In particular, the present invention is applicable to Synchronous Transfer Mode (STM) and Asynchronous Transfer Mode (ATM) transmission, and reduces payload transmission delay. The present invention relates to an ATU-C framer device and a control method thereof, which are adapted to be effectively reduced.

In general, ADSL uses the existing telephone line to communicate (asymmetrically) 8Mbps in the downstream direction and 1Mbps in the upstream direction to realize services such as high-speed Internet, VOD, remote LAN access, and on-demand multimedia. It is a technology that can.

1 is a block diagram of a general ADSL system.

Here, VC performs an interface between ATU-C and digital network elements such as one or more switching systems, and TR performs an interface between an ADSL Transceiver Unit-Remote terminal (ATU-R) and a switching (ATM or STM) layer. The UC performs the line interface at the end of the telephone station side (CO), and the UR performs the line interface at the end of the subscriber side (RT). In addition, NT is a network terminal device, T / S is an interface between an ADSL network end and a home network, ISDN is a comprehensive information communication network, SM is a service module, and POTS (Plain Old Telephone Service) Is a general telephone service using a voice band and is used as a general name for all voice band services.

FIG. 2 is a detailed block diagram of ATU-C and ATU-R in FIG. 1.

Here, reference numeral 11 is an ATU-C, 12 is a framer part in the ATU-C 11, 13 is a DME (DMT Engine) part in the ATU-C 11, and 14 is a ATU-C (11). AFE (Analog Front-End) in Reference numeral 15 is an ATU-R, 16 is an AFE part in the ATU-R 15, 17 is a DME part in the ATU-R 15, and 18 is a framer part in the ATU-R 15. to be.

Therefore, in the rate adaptive data transmission of ADSL, the ATU-C (11) and the ATU-R (15) on the subscriber side check the ADSL line status to determine the highest performance transmission rate. Allows data transfer between them. At this time, the framer of the transmitter of each modem transmits when there is more than a certain amount (fixed value) in the 'frame buffer'.

3 is a block diagram of a FIFO of the conventional ATU-C framer and its peripheral device.

Here, reference numeral 21 is a serial to parallel (S / P) conversion unit, 22 is a First In First Out (FIFO), 23 is a Digital Signal Processor (DSP), 24 is a FIFO controller, and 25 is a multiplexing / synchronous control unit. to be.

4 is a flowchart illustrating a conventional ATU-C framer control method.

As shown therein, upon receiving the 'Start' signal from the processor 23, enabling the 'Write' signal (ST11) (ST13); When the 'light' signal is enabled, data from the channel is stored in the FIFO 22 and 'Read' until the pointer value of the FIFO 22 reaches the 'Normal Flag'. Disabling the signals (ST13 to ST15); When the pointer value of the FIFO 22 reaches the 'normal flag', it enables the 'lead' signal and then starts data transmission from the FIFO 22 to start the 'Mode' from the processor 23. In step ST16 to ST18, the multiplexing and synchronization of payload data and overhead are performed according to the values 'BF' and 'BI'.

Thus, in the case of the conventional ADSL framer 12, as shown in Figs. 3 and 4, when the 'start' signal is received from the processor 23, the 'write' signal is enabled and the data from the channel is FIFO (Framer Buffer). To the FIFO by disabling the 'read' signal until the 'Pointer' value in the Framer Buffer reaches the normal flag value and then enabling the first 'read' signal when the normal flag value is reached. Start 'data' transfer from (22).

Then, the multiplexing and synchronization functions of payload data and overhead are performed by 'mode', 'BF' and 'BI' values from the processor 23.

Here, 'mode' is a framing structure number, 'BF' is a number of bytes of a fast buffer, and 'BI' is a number of bytes of an interleaved buffer.

As such, the framer depends only on the pointer value of the FIFO 22, that is, the fixed Normal Flag value. In general, the value defined by the Normal Flag uses the middle value of the FIFO size.

In the conventional ATU-C framer, communication is started when the 'BF', 'BI', that is, the 'Pointer' value in the FIFO is greater than or equal to the Normal Flag value regardless of the data transmission rate.

The 'payload transfer delay' during data transmission of the modem refers to a one way transfer delay for payload bits from V-C to T-R of FIG. 1.

However, this conventional technique has a problem in that the payload transmission delay is long due to the large latency in the FIFO (buffer) of the ATU-C framer, which degrades the performance of the entire modem.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is applicable to STM and ATM transmission and can effectively reduce payload transmission delay and control thereof. To provide a way.

In order to achieve the above object, the ATU-C framer device according to an embodiment of the present invention,

A framer unit of the ATU-C, comprising: a FIFO for temporarily storing parallel data of a downstream channel; A DSP for outputting a 'baud rate' signal, a 'start' signal, and a 'mode' signal determined by training an ADSL line state; The FIFO data is transmitted by receiving a 'start' signal, a 'baud rate' signal, and a 'mode' signal from the DSP and determining a variable optimal value for a pointer value to be recognized as a 'normal flag' of the FIFO. It is characterized by the technical configuration that comprises a framer controller to control.

ATU-C framer control method according to an embodiment of the present invention to achieve the above object,

Training the ADSL line state and applying a determined transmission rate and a 'start' signal to the framer unit; After the first step, the enable time of the 'light' signal and the 'lead' signal is variably optimized according to the determined transmission rate to determine and transmit a variable optimal value for the pointer value to be recognized as the 'normal flag' of the FIFO. Including the second step is characterized by its technical configuration.

1 is a block diagram of a general ADSL system.

FIG. 2 is a detailed block diagram of ATU-C and ATU-R in FIG. 1.

3 is a block diagram of a FIFO of the conventional ATU-C framer and its peripheral device.

4 is a flowchart illustrating a conventional ATU-C framer control method.

5 is a block diagram of an ATU-C framer device according to the present invention.

6 is a detailed block diagram of the FIFO and its peripherals in FIG.

7 is a flowchart illustrating a method for controlling an ATU-C framer according to the present invention.

Explanation of symbols on the main parts of the drawings

11: ATU-C 12, 18: Framer part

13, 17: DME section 14, 16: AFE section

15: ATU-R 31: S / P converter

32: FIFO 33: DSP

34: Framer controller 35: Multiplexing / synchronous control

36, 37: CRC 38, 39: Scrambler

40, 41: FEC 42: Interleaver

43: FEC controller 44: merge unit

Hereinafter, an embodiment according to the present invention, the ATU-C framer device configured as described above and a control method thereof will be described in detail with reference to the accompanying drawings.

FIG. 5 is a block diagram of an ATU-C framer device according to the present invention, and FIG. 6 is a detailed block diagram of a FIFO and peripheral devices thereof in FIG. 5.

As shown here, the framer unit 12 of the ATU-C 11 includes: a FIFO 32 for temporarily storing parallel data of a downstream channel; A DSP 33 for outputting a 'baud rate (BF, BI)' signal, a 'start' signal, and a 'mode' signal determined by training an ADSL line state; The DSP 33 receives a 'start' signal, a 'baud rate' signal, and a 'mode' signal to determine a variable optimal value for a pointer value to be recognized as a 'normal flag' of the FIFO 32. And a framer controller 34 that controls the data of the FIFO 32 to be transmitted.

Here, reference numeral 31 denotes an S / P conversion unit, 35 denotes a multiplexing / synchronous control unit, 36 and 37 denote cyclic redundancy checks (CRCs) of fast paths and interleaved paths, and 38 and 39 denote scramblers of fast paths and interleaved paths. , 40 and 41 are forward error correction (FEC) of fast path and interleaved path, 42 is interleaver, 43 is FEC controller, and 44 is merge.

7 is a flowchart illustrating a method for controlling an ATU-C framer according to the present invention.

As shown therein, a first step (ST21) of training the ADSL line state and applying the transmission rate (BF, BI) and the 'start' signal determined to the framer unit 12; After the first step, the enable time of the 'light' signal and the 'lead' signal is variably optimized according to the determined transmission rate to determine a variable optimal value for the pointer value to be recognized as the 'normal flag' of the FIFO 32. And the second step ST22 is transmitted.

The operation of the ATU-C framer device and its control method according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the present invention is to effectively reduce the payload transmission delay.

Thus, when each processor of the ATU-C 11 and the ATU-R 15 trains the ADSL line state and applies the transmission rate (BF, BI) and the 'start' signal determined to the framer 12, the framer determines the determined transmission. 'Write' signal enable to store data from channel to FIFO 32 according to speed (BF, BI) and first 'read' to transfer first data from FIFO 32 to multiplex / sync control 35 'The signal enable time is variably optimized according to the data rate and transmitted. That is, according to the determined transmission rate, the optimal value is variably determined and transmitted with respect to the pointer value to be recognized as the 'normal flag' of the FIFO 32.

ATU-C's Discrete Multi Tone (DMT) modem method modulates transmission data into multiple carriers (tones and bins) and transmits the data. In this method, by analyzing the characteristics of the line in each frequency band section in advance, it is possible not only to determine and transmit the optimal amount of data that enables the maximum data rate for each band, but also to transmit data of various data rates.

The DMT modem consists of 256 subcarriers with a band of 4.3125 KHz in the range of 0 to 1.104 MHz. These subcarriers are divided into downstream and upstream, and the ratio of allocated subcarriers is formed in an asymmetric shape allocated relatively much on the downstream side. Each subcarrier is allocated up to 15 bits, and the DMT symbol rate is 4KHz. Thus, the maximum transmission rate of 256 subcarriers is as follows.

15.36 Mbps = 4K (symbol / sec) * 256 (bins / symbol) * 15 (bits / bin)

In fact, Modem can be up to 8 Mbps for downstream and 1 Mbps for upstream considering the characteristics of POTS, Pilot Tone, Nyquist frequency, and frequency.

Equation 1 below shows the amount of data (bytes) that can be transmitted per symbol for the data rate (n * 32 K bps).

n * 32 K (bits / sec) = 1 / 4K (sec / symbol) = n * 8 (bits / symbol) = n * 1 (bytes / symbol)

Here, 'n * 32 K bps' is the data rate of the ADSL DMT modem, and '4 K (symbol / sec)' is the symbol rate of the ADSL DMT modem.

In addition, the data rate of 'n * 32 K bps' allows the size of a data buffer (FIFO) constituting a frame to be configured in bytes, and the input channel is' n * It is possible to enable transmission for 32 K bps', that is, 32 Kbps multiples.

The input channel of the DMT modem includes Simplex Channels (AS0, AS1, AS2, AS3) applied downstream and Duplex channels (LS0, LS1, LS2) applied both upstream and downstream. Both channels consist of a bit rate of 'n * 32 K bps'. The transmission speed of ATU-C (11) and ATU-R (15) is determined by the initialization process when transmitting data of modem. It means 'n' value of 'n * 32 K bps' of each channel and BF (AS0), BF (AS1),... … , BI (AS0), BI (AS1),... … Is applied to the framer unit controller 34 from the DSP 33.

Here, 'BF' is the number of bytes of the fast buffer for each of ASx and LSx, and 'BI' is the number of bytes of the interleaved buffer for each of ASx and LSx.

Meanwhile, FIG. 3 illustrates a structure of a conventional framer unit, and FIG. 6 illustrates a structure of a framer unit according to the present invention.

Therefore, in the case of a conventional framer, the latency of the frame buffer (FIFO) when transmitting at a random transmission rate (n * 32 Kbps) for any channel (any one of AS0, AS1, and AS2) As follows. (When normal flag is defined as 256 * 8)

1) When input channel = 640 KHz

From the point of view of the input channel of the FIFO 22, it takes 1/640 KHz * 256 * 8 = 3.2 msec, since it is a continuous stream to kick to the Normal Flag.

From the point of view of the output of the FIFO 22, it is a burst stream, and in order to apply a symbol rate to the normal flag,

640K (bits / sec) * 1 / 4K (sec / symbol) = 160 (bits / symbol) = 20 (bytes / symbol)

This takes

Therefore, 256 bytes requires 256/20 = 12.8 symbols.

Therefore, 1/4 KHz * 12.8 = 3.2 msec.

The input and output of the FIFO 22 are of the same rate, only the difference between the 'Continuos stream' or the 'Burst stream', and a 3.2msec latency is required to reach the FIFO 22's Normal Flag. do.

2) When input channel = 1536 KHz

From the perspective of the input channel of the FIFO 22, it takes 1/1536 KHz * 256 * 8 = 1.333 msec.

From the output point of view of the FIFO 22, 1536K (bits / sec) * 1 / 4K (sec / symbol) = 48 (bytes / symbol). So it takes 1/4 KHz * (256/48) = 1.333 msec.

3) When input channel = 6144 KHz

From the point of view of the input channel of the FIFO 22, it takes 1/6144 KHz * 256 * 8 = 333.333 usec.

From the output point of view of the FIFO 22, 6144K (bits / sec) * 1 / 4K (sec / symbol) = 192 (bytes / symbol). So it takes 1/4 KHz * (256/192) = 333.333 usec.

As described above, in the case of a conventional framer, when a random bit rate is applied to an input channel, the framer's latency is different. In particular, a lower bit rate of the input channel is more critical. This is the value that ATU-C (11) and ATU-R (15) can securely transmit data by focusing only on FIFO logic regardless of transmission rate (BF, BI) determined through initialization process. Because I made it.

On the other hand, the framer according to the present invention operates as follows.

First, when the transmission rates (BF, BI) are determined by the ATU-C 11 and the ATU-R 15 through an initialization process, the DSP 33 transmits the transmission rates (BF, BI) and the 'start' signal to the framer. When the frame is applied, the framer sends a 'write' signal enable that stores data from the channel to the FIFO 32 and the original data from the FIFO 32 to the multiplexing / synchronous control unit 35 according to the determined transmission rates (BF, BI). The first 'read' signal enable time to transmit is optimized and transmitted according to the transmission speed.

Thus, the framer controller 34 determines the pointer value of the FIFO 32 to be recognized as the 'start' time and the 'Normal Flag' from the FIFO 32 to control the transmission. The factor is

The input (channel) of the FIFO 32 is a continuous stream.

The output of the FIFO 32 is a burst stream

-Payload transmission delay

-Value that can stably and stuffing (Deleting) of framer

-BF, BI (transmission rate for each channel received from DSP)

Accordingly, the latency of the frame buffer (FIFO) when transmitting with an arbitrary transmission rate (n * 32 Kbps) for any channel (any one of AS0, AS1, and AS2) is as follows.

Here, Normal Flag = n value, that is, BF and BI. This is a pointer value to be recognized as 'Normal Flag' according to the transmission speed.

1) When input channel = 640 KHz (Normal Flag = 20 * 8)

In terms of the input channel of the FIFO 32, 1/640 KHz * 20 * 8 = 250 usec.

In terms of the output of the FIFO 32, 640K (bits / sec) * 1 / 4K (sec / symbol) = 160 (bits / symbol) = 20 (bytes / symbol).

Therefore, to have 20 bytes, one symbol is required. Therefore, 1/4 KHz = 250 usec.

2) When input channel = 1536 KHz (Normal Flag = 48 * 8)

From the perspective of the input channel of the FIFO 32, 1/1536 KHz * 48 * 8 = 250usec.

From the output point of view of the FIFO 32, 1536K (bits / sec) * 1 / 4K (sec / symbol) = 48 (bytes / symbol). Therefore, 1/4 KHz = 250usec.

3) Input channel = 6144 KHz (Normal Flag = 192 * 8)

From the perspective of the input channel of the FIFO 32, 1/6144 KHz 192 8 = 250 usec.

From the output point of view of the FIFO 32, 6144K (bits / sec) * 1 / 4K (sec / symbol) = 192 (bytes / symbol). Therefore, 1/4 KHz = 250 usec.

As described above, in the case of the framer of the present invention, when a random bit rate is applied to the input channel, the framer's latency is 250usec, which enables stable transmission with a minimum latency.

Meanwhile, the payload transmission delay (one-way transmission delay for payload bits from V-C to T-R) of the ADSL modem according to the present invention is as follows.

In the case of an interleaved path, the payload transmission delay defined in the ADSL specification is shown in Equation 2 below.

Payload Transmission Delay = 4 + (S-1) / 4 + SD / 4

Where S is a DMT symbol per Reed Solomon (RS) code word and D is an interleaved depth.

This delay is as follows for each ATU-C 11 block (see FIG. 2).

-Framer Buffer (FIFO) = 250 us

-Framer section (except FIFO) = S * D * 250us

= 250 us (if S = 1, D = 1)

-DME + AFE = 500 us

Therefore, ATU-C + ATU-R = (250 + 250 + 500) us * 2 = 2ms.

Therefore, it is possible to have a lot of margin compared to the specification defined in equation (2).

The delay defined by the specification is

-[4 + (S-1) / 4 + SD / 4] ms = 4.25 ms (if S = 1 and D = 1).

The delay according to the present invention,

-ATU-C + ATU-R = (250 + 250 + 500) us 2 = 2ms.

As described above, by determining the optimal value variably for the pointer value to be recognized as the normal flag of the FIFO according to the transmission rate determined according to the framer according to the present invention, the latency of the framer unit can be reduced to the minimum stable value as well as the entire modem. This can greatly improve performance.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the ATU-C framer device and its control method according to the present invention can be applied to STM and ATM transmission and can effectively reduce the payload transmission delay.

In addition, in the conventional frame buffer, the latency is different between the highest and lowest conditions of the transmission, and when the lowest conditions are used, the overall performance of the modem is degraded. However, the present invention always requires a constant and minimum delay for a variable data rate. This improves the modem's 'payload transmission delay' and at the same time improves overall performance.

Claims (2)

In the framer part of ATU-C, A FIFO for temporarily storing parallel data of a downstream channel; A DSP for outputting a 'baud rate' signal, a 'start' signal, and a 'mode' signal determined by training an ADSL line state; The FIFO data is transmitted by receiving a 'start' signal, a 'baud rate' signal, and a 'mode' signal from the DSP and determining a variable optimal value for a pointer value to be recognized as a 'normal flag' of the FIFO. An ATU-C framer device comprising a framer controller for controlling. Training the ADSL line state and applying a determined transmission rate and a 'start' signal to the framer unit; After the first step, the enable time of the 'light' signal and the 'lead' signal is variably optimized according to the determined transmission rate to determine and transmit a variable optimal value for the pointer value to be recognized as the 'normal flag' of the FIFO. ATU-C framer control method characterized in that it comprises a second step.