KR20030007438A - Multilayer printed wiring board and method for producing multilayer printed wiring board - Google Patents

Multilayer printed wiring board and method for producing multilayer printed wiring board Download PDF

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Publication number
KR20030007438A
KR20030007438A KR1020027011073A KR20027011073A KR20030007438A KR 20030007438 A KR20030007438 A KR 20030007438A KR 1020027011073 A KR1020027011073 A KR 1020027011073A KR 20027011073 A KR20027011073 A KR 20027011073A KR 20030007438 A KR20030007438 A KR 20030007438A
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KR
South Korea
Prior art keywords
layer
substrate
multilayer printed
insulating layer
circuit board
Prior art date
Application number
KR1020027011073A
Other languages
Korean (ko)
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KR100890534B1 (en
Inventor
사카모토하지메
스기야마타다시
왕돈돈
카리야타카시
Original Assignee
이비덴 가부시키가이샤
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Publication of KR20030007438A publication Critical patent/KR20030007438A/en
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Publication of KR100890534B1 publication Critical patent/KR100890534B1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
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    • H05K1/00—Printed circuits
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    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

다층프린트배선판은, 코어기판(30)에 IC칩(20)을 미리 내장시키고, 해 IC칩(20)의 패드(24)에는 트랜지션층(38)을 배설시키고 있다.In the multilayer printed circuit board, the IC chip 20 is embedded in the core substrate 30 in advance, and the transition layer 38 is disposed on the pad 24 of the IC chip 20.

이 때문에, 리드부품이나 봉지수지를 사용하지 않고, IC칩과 다층프린트배선판과의 전기적 접속을 취하는 것이 가능하다. 또, 다이패드(24) 상에 동제의 트랜지션층(38)을 설치하는 것으로, 패드(24) 상의 수지잔재를 방지할 수 있어, 패드(24)와 바이어홀(60)과의 접속성이나 신뢰성을 향상시킨다.For this reason, it is possible to make electrical connection with an IC chip and a multilayer printed wiring board, without using a lead component or sealing resin. Moreover, by providing the copper transition layer 38 on the die pad 24, the resin residue on the pad 24 can be prevented, and the connection and reliability of the pad 24 and the via hole 60 can be prevented. To improve.

Description

다층프린트배선판 및 다층프린트배선판의 제조방법{Multilayer printed wiring board and method for producing multilayer printed wiring board}Multilayer printed wiring board and method for producing multilayer printed wiring board

IC칩은, 와이어본딩, TAB, 플립칩 등의 실장방법에 의해, 프린트배선판과의 전기적 접속을 취하여 왔다.IC chips have been electrically connected to printed wiring boards by mounting methods such as wire bonding, TAB, and flip chips.

와이어본딩은, 프린트배선판에 IC칩을 접착제에 의해 다이본딩시켜, 프린트배선판의 패드와 IC칩의 패드를 금선 등의 와이어로 접속시킨 후, IC칩 및 와이어유지하기 위해 열경화성수지 혹은 열가소성수지 등의 봉지수지를 시공하고 있다.Wire bonding die-bonds an IC chip to a printed wiring board with an adhesive, and connects the pad of the printed wiring board and the pad of the IC chip with a wire such as a gold wire, and then the thermosetting resin or the thermoplastic resin to maintain the IC chip and the wire. We are constructing bag resin.

TAB는, IC칩의 범프와 프린트배선판의 패드를 리드라고 불리는 선을 납땜 등에 의해 일괄하여 접속시킨 후, 수지에 의한 봉지를 행하고 있었다.TAB encapsulated with resin after connecting the bump of an IC chip and the pad of a printed wiring board collectively by connecting the line called lead by soldering etc.

플립칩은, IC칩과 프린트배선판의 패드부를 범프를 개재하여 접속시키고, 범프와의 사이에 수지를 충진시키는 것에 의한 행하고 있었다.The flip chip was performed by connecting the pad part of an IC chip and a printed wiring board through bumps, and filling resin between bumps.

그러나, 각각의 실장방법은, IC칩과 프린트배선판의 사이에 접속용의 리드부품(와이어, 리드, 범프)을 개재하여 전기적 접속을 행하고 있다. 그들의 각 리드부품은, 절단, 부식하기 쉽고, 이로 인해, IC칩과의 접속이 끊어진다든지, 오작동의 원인이 되는 일이 있었다.However, in each of the mounting methods, electrical connection is performed between the IC chip and the printed wiring board via lead parts (wires, leads, bumps) for connection. Each of these lead parts is easy to be cut and corroded, which may cause disconnection of the IC chip or cause malfunction.

또, 각각의 실장방법은, IC칩을 보호하기 위해 에폭시수지 등의 열가소성수지에 의한 봉지를 행하고 있는데, 그 수지를 충진하는 때에 기포를 함유하면, 기포를 기점으로 하여, 리드부품의 파괴나, IC패드의 부식, 신뢰성의 저하를 초래하게 된다. 열가소성수지에 의한 봉지는, 각각의 부품에 맞추어 수지장진용 프랜저, 금형을 제작할 필요가 있고, 또, 열경화성수지라 할지라도 리드부품, 솔더레지스트 등의 재질 등을 고려한 수지를 선정하지 않으면 안되기 때문에, 각각에 있어서, 비용이 상승하게 되는 원인이 되었다.In addition, each mounting method is encapsulated with a thermoplastic resin such as an epoxy resin in order to protect the IC chip. If air bubbles are included when the resin is filled, the lead parts may be destroyed and the lead parts may be broken. This may cause corrosion of the IC pad and deterioration of reliability. Since encapsulation with thermoplastic resin needs to produce a resin-strengthening flanger and a mold for each component, and even a thermosetting resin, a resin must be selected in consideration of materials such as lead parts and solder resists. In each case, it became the cause which cost rose.

본 발명은, 빌드업다층프린트배선판에 관한 것으로서, 특히 IC칩 등의 전자부품을 내장하는 다층프린트배선판 및 다층프린트배선판의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buildup multilayer printed circuit board, and more particularly, to a method for manufacturing a multilayer printed circuit board and a multilayer printed circuit board containing electronic components such as an IC chip.

도 1 은, 본 발명의 제 1 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.1 is a manufacturing process diagram of a multilayer printed circuit board according to the first embodiment of the present invention.

도 2 는 , 제 1 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.2 is a manufacturing process diagram of a multilayer printed circuit board according to the first embodiment.

도 3 은, 제 1 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.3 is a manufacturing process diagram of a multilayer printed circuit board according to the first embodiment.

도 4 는, 제 1 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.4 is a manufacturing process diagram of the multilayer printed circuit board according to the first embodiment.

도 5 는, 제 1 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.5 is a manufacturing process diagram of the multilayer printed circuit board according to the first embodiment.

도 6 은, 제 1 실시형태에 관계하는 다층프린트배선판의 단면도이다.6 is a cross-sectional view of the multilayer printed circuit board according to the first embodiment.

도 7 에서, (A) 는, 도 3 (A) 중의 트랜지션층을 확대하여 도시하는 도이며, (B)는, 도 7 (A)의 B 화살표도이며, (C), (D), (E)는, 트랜지션층의 개선례의 설명도이다.In FIG. 7, (A) is the figure which expands and shows the transition layer in FIG. 3 (A), (B) is the B arrow of FIG. 7 (A), (C), (D), ( E) is explanatory drawing of the improvement example of a transition layer.

도 8 에서, (A)는, 제 1실시형태에 관계하는 다층프린트배선판의 사시도이고, (B)는, 해당 다층프린트배선판의 일부를 확대하여 도시하는 설명도이다.In FIG. 8, (A) is a perspective view of the multilayer printed circuit board which concerns on 1st Embodiment, (B) is explanatory drawing which expands and shows a part of this multilayer printed wiring board.

도 9 에서, (A)는, 제 1실시형태의 제 1변형예에 관계하는 다층프린트배선판의 사시도이고, (B)는, 해 다층프린트배선판의 일부를 확대하여 도시하는 설명도이다.In FIG. 9, (A) is a perspective view of the multilayer printed circuit board which concerns on the 1st modified example of 1st Embodiment, (B) is explanatory drawing which expands and shows a part of the multilayer printed circuit board.

도 10 은, 제 1 실시형태의 제 2변형예에 관계하는 다층프린트배선판의 단면도이다.10 is a cross-sectional view of the multilayer printed circuit board according to the second modification of the first embodiment.

도 11 은 , 제 1 실시형태의 제 2변형예에 관계하는 다층프린트배선판의 단면도이다.11 is a cross-sectional view of the multilayer printed circuit board according to the second modification of the first embodiment.

도 12 는, 제 1 실시형태의 제 2변형예에 관계하는 다층프린트배선판의 단면도이다.12 is a sectional view of a multilayer printed circuit board according to a second modification of the first embodiment.

도 13 은, 제 2 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.FIG. 13 is a manufacturing process diagram of a multilayer printed circuit board according to the second embodiment. FIG.

도 14 는, 제 2 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.14 is a manufacturing process diagram of the multilayer printed circuit board according to the second embodiment.

도 15 는, 제 2 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.FIG. 15 is a manufacturing process diagram of a multilayer printed circuit board according to the second embodiment. FIG.

도 16 은, 제 2 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.FIG. 16 is a manufacturing process diagram of a multilayer printed circuit board according to the second embodiment. FIG.

도 17 은, 제 2 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.17 is a manufacturing process diagram of the multilayer printed circuit board according to the second embodiment.

도 18 은, 제 2 실시형태에 관계하는 다층프린트배선판의 단면도이다.18 is a cross-sectional view of the multilayer printed circuit board according to the second embodiment.

도 19 에서, (A)는, 제 13도(D) 중의 코어기판의 평면도이고, (B)는, 제 13도(E)의 평면도이다.In Fig. 19, (A) is a plan view of the core substrate in Fig. 13D, and (B) is a plan view of Fig. 13E.

도 20 에서, (A)는, 포토마스크필름 적재 전의 코어기판의 평면도이고, (B)는, 포토마스크필름을 적재한 상태의 코어기판의 평면도이다.In Fig. 20, (A) is a plan view of the core substrate before the photomask film is loaded, and (B) is a plan view of the core substrate with the photomask film loaded.

도 21 은, 제 2 실시형태의 제 1 변형예에 관계하는 다층프린트배선판의 단면도이다.21 is a cross-sectional view of the multilayer printed circuit board according to the first modification of the second embodiment.

도 22 는, 제 3 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.Fig. 22 is a manufacturing process diagram of the multilayer printed circuit board according to the third embodiment.

도 23 은, 제 3 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.23 is a manufacturing process diagram of the multilayer printed circuit board according to the third embodiment.

도 24 는, 제 3 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.24 is a manufacturing process diagram of the multilayer printed circuit board according to the third embodiment.

도 25 는, 제 3 실시형태에 관계하는 다층프린트배선판의 제조공정도이다.25 is a manufacturing process diagram of a multilayer printed circuit board according to the third embodiment.

도 26 은, 제 3 실시형태에 관계하는 다층프린트배선판의 단면도이다.Fig. 26 is a sectional view of the multilayer printed circuit board according to the third embodiment.

도 27 에서 (A)는, 도 22 (C) 중의 다이패드 부분을 확대하여 도시하는 설명도이고, (B)는, 도 23 (A) 중의 다이패드 부분을 확대하여 도시하는 설명도이고, (C)는, 도 24 (A) 중의 다이패드 부분을 확대하여 도시하는 설명도이다.(A) is explanatory drawing which expands and shows the diepad part in FIG. 22 (C), (B) is explanatory drawing which expands and shows the diepad part in FIG. C) is explanatory drawing which expands and shows the die pad part in FIG. 24 (A).

도 28 은, 제 3 실시형태의 제 1 변형예에 관계하는 다층프린트배선판의 단면도이다.FIG. 28 is a cross-sectional view of the multilayer printed circuit board according to the first modification of the third embodiment. FIG.

도 29 는 제 3 실시형태의 제 1 변형예에 관계하는 다이패드부분을 확대하여 도시하는 도이며, (A)는, 산화피막제거처리되기 전의 상태를 도시하는 도, (B)는, 산화막제거처리 후의 상태를 도시하는 도, (C)는, 다이패드 상에 트랜지션층을 형성한 후를 도시하는 도이다.FIG. 29 is an enlarged view of a die pad portion according to a first modification of the third embodiment, (A) is a diagram showing a state before the oxide film removal treatment, and (B) is an oxide film removal (C) which shows the state after a process is a figure which shows after forming a transition layer on a die pad.

도 30 은, 제 3 실시형태와 비교예의 다층프린트배선판을 1) 단면상태, 2)저항측정치, 3) 신뢰성시험 후의 단면상태, 4) 저항측정치의 계 4항목에 대하여 평가를 행한 결과를 도시하는 도표이다.Fig. 30 shows the results of evaluating the multilayered printed circuit boards of the third embodiment and the comparative example with respect to 4 items of 1) cross-sectional state, 2) resistance measurement value, 3) cross-sectional state after reliability test, and 4) resistance measurement value. It is a chart.

본 발명은 상술한 과제를 해결하기 위해 행해진 것이며, 그 목적으로 하는 것은, 리드부품을 개재하지 않고, IC칩과 직접 전기적으로 접속할 수 있는 다층프린트배선판 및 다층프린트배선판의 제조방법을 제안하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to propose a method for manufacturing a multilayer printed circuit board and a multilayer printed circuit board which can be directly connected to an IC chip without a lead component. It is done.

본 발명자는 예의 연구한 결과, 수지절연성 기판에 개구부, 통공이나 스폿페이싱부를 설치하고, IC칩 등의 전자부품을 미리 내장시켜서, 층간절연층을 적층하고, 해당 IC칩의 다이패드 상에, 포토에칭 혹은 레이저에 의해, 바이어홀을 설치하고, 도전층인 도체회로를 형성시킨 후, 다시, 층간절연층과 도전층을 반복하여, 다층프린트배선판을 설치하는 것에 의해, 봉지수지를 사용하지 않고, 리드레스에 의해 IC칩과의 전기적 접속을 취하는 것이 가능한 구조를 제안하였다.As a result of intensive studies, the inventors have provided openings, through holes, and spot facing portions in a resin insulating substrate, and previously built electronic components such as IC chips, laminated interlayer insulating layers, and formed a photo on the die pad of the IC chips. After the via hole is formed by etching or laser to form the conductive circuit as the conductive layer, the interlayer insulating layer and the conductive layer are repeated, and the multilayer printed circuit board is provided, thereby eliminating the use of the encapsulating resin. A structure capable of allowing electrical connection with an IC chip by leadless has been proposed.

또, 본 발명자는, 수지절연성기판에 개구부, 통공이나 스폿페이싱부를 설치하여, IC칩 등의 전자부품을 미리 내장시켜서, 층간절연층을 적층하고, 해당 IC칩의 다이패드 상에, 포토에칭 혹은 레이저에 의해, 바이어홀을 설치하여, 도전층인 도체회로를 형성시킨 후, 다시, 층간절연층과 도전층을 반복하여, 다층프린트배선판의 표층에도 IC칩 등의 전자부품을 실장시킨 구조를 제안하였다. 그로 인해, 봉지수지를 사용하지 않고, 리드레스에 의해 IC칩과의 전기적 접속을 취하는 것이 가능하다. 또, 각각의 기능이 다른 IC칩 등의 전자부품을 실장시키는 것이 가능하고, 보다 고기능적인 다층프린트배선판을 얻는 것이 가능하다. 구체예로서, 내장 IC칩에는, 캐쉬메모리를 매입시키고, 표층에는 연산기능을 가지는 IC칩을 실장시키는 것에 의해, 원료의 낭비가 적은 캐쉬메모리를 IC칩과 별도로 제조하면서, IC칩과 캐쉬메모리를 근접하여 배치하는 것이 가능하게 된다.In addition, the present inventors provide openings, through holes, and spot facing portions in the resin insulating substrate, embed electronic components such as IC chips in advance, and layer an interlayer insulating layer, and photoetch or After a via hole is formed by a laser to form a conductive circuit as a conductive layer, the interlayer insulating layer and the conductive layer are repeated, and a structure in which electronic components such as IC chips are mounted on the surface layer of the multilayer printed circuit board is proposed. It was. Therefore, it is possible to establish electrical connection with the IC chip by leadless without using the sealing resin. In addition, it is possible to mount electronic components such as IC chips having different functions, and it is possible to obtain a more functional multilayer printed circuit board. As a specific example, an IC chip and a cache memory may be manufactured while a cache memory with less waste of raw materials is manufactured separately from the IC chip by embedding a cache memory in the built-in IC chip and mounting an IC chip having a calculation function on the surface layer. It becomes possible to arrange | position closely.

또 다시, 본 발명자는, 예의 연구한 결과, 수지절연성기판에 개구부, 통공이나 스폿페이싱부를 설치하고, IC칩 등의 전자부품을 미리 수용시켜, 해당 IC칩의 다이패드에는 적어도 2층구조로 이루어지는 트랜지션층을 형성시키는 것을 안출하였다. 트랜지션층의 상층에는 층간절연층을 적층하고, 해당 IC칩의 트랜지션층인 바이어홀 상에, 포토에칭 혹은 레이저에 의해, 바이어홀을 설치하고, 도전층인 도체회로를 형성시킨 후, 다시, 층간절연층과 도전층을 반복하여, 다층프린트배선판을 설치하는 것에 의해, 봉지수지를 사용하지 않고, 리드레스에 의해 IC칩과의 전기적 접속을 취하는 것이 가능하다. 또, IC칩 부분에 트랜지션층이 형성되고 있는 것에 의하여, IC칩 부분에는 평탄화되기 때문에, 상층의 층간절연층도 평탄화되고, 막두께도 균일하게 된다. 또, 상술한 트랜지션층에 의해, 상층의 바이어홀을 형성할 때에도, 형상의 안정성을 지키는 것이 가능하다.Further, as a result of intensive studies, the inventors have provided openings, through holes, and spot facing portions in the resin insulating substrate, and previously contained electronic components such as IC chips, and the die pad of the IC chips had at least a two-layer structure. It was conceived to form a transition layer. An interlayer insulating layer is laminated on the transition layer, and via holes are formed by photoetching or laser on the via hole, which is the transition layer of the IC chip, and the conductor circuit serving as the conductive layer is formed. By repeating the insulating layer and the conductive layer and providing the multilayer printed circuit board, it is possible to establish electrical connection with the IC chip by leadless without using a sealing resin. In addition, since the transition layer is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer is also flattened and the film thickness is uniform. In addition, with the above-described transition layer, it is possible to maintain the stability of the shape even when forming the upper via hole.

IC칩의 패드에 트랜지션층을 설치하는 이유는, 다음과 같다. 첫째, 다이패드가 미세한(파인한) 구성 및 스몰사이즈가 되면, 비어를 형성하는 때의 어라인먼트(alignment)가 곤란하게 되기 때문에, 트랜지션층을 설치하여 어라인먼트를 하기 쉽게 한다. 트랜지션층을 설치하면, 다이패드피치 150 ㎛ 이하, 패드사이즈 20 ㎛ 이하로도 빌드업층이 안정하게 형성할 수 있다. 트랜지션층을 형성시키지 않은 다이패드인 채로 포토에칭에 의해 층간절연층의 비어를 형성시키면, 비어경이 다이패드경보다도 크고, 비어바닥 잔사제거, 층간수지절연층 표면조화처리로서 행하는 때에, 다이패드 표면의 보호층인 폴리이미드층을 용해, 손상시킨다. 한편, 레이저의 경우, 비어경이 다이패드경보다 클 때에는, 다이패드 및 패시베이션막인 폴리미드층(IC의 보호막)이 레이저에 의해 파괴된다. 또, IC칩의 다이패드가 매우 작고, 비어경이 다이패드 사이즈보다 커지면, 포토에칭법으로도, 레이저법으로도 위치맞춤이 매우 곤란하고, 다이패드와 비어와의 접속불량이 다발한다.The reason why the transition layer is provided on the pad of the IC chip is as follows. First, when the die pad has a fine (fine) configuration and a small size, alignment at the time of forming the via becomes difficult, so that the alignment layer is easily provided for alignment. When the transition layer is provided, the buildup layer can be stably formed even with a die pad pitch of 150 m or less and a pad size of 20 m or less. If the via layer of the interlayer insulating layer is formed by photoetching with the die pad without forming the transition layer, the via diameter is larger than that of the die pad, and the bottom surface of the die pad is used as the bottom residue removal and the interlayer resin insulating layer surface roughening treatment. The polyimide layer, which is a protective layer, is dissolved and damaged. On the other hand, in the case of a laser, when the via diameter is larger than the die pad diameter, the polyimide layer (the protective film of the IC) serving as the die pad and the passivation film is destroyed by the laser. In addition, when the die pad of the IC chip is very small and the via diameter is larger than the die pad size, the alignment is very difficult by the photoetching method or the laser method, and the connection between the die pad and the via is frequent.

이에 대하여, 다이패드 상에 트랜지션층을 설치함으로서, 다이패드피치 150 ㎛ 이하, 패드사이즈 20 ㎛ 이하로 되어도 다이패드 상에 비어를 확실하게 접속시키는 것이 가능하고, 패드와 비어와의 접속성이나 신뢰성을 향상시킨다. 또, IC칩의 패드 상에 보다 큰 직경의 트랜지션층을 개재시키는 것으로, 데스미어, 도금공정 등의 후공정 시에, 산이나 에칭액에 침적시키거나, 각종 아닐공정을 거쳐도, 다이패드 및 IC의 보호막을 용해, 손상하는 위험이 없어진다.On the other hand, by providing a transition layer on the die pad, the via can be reliably connected on the die pad even when the die pad pitch is 150 μm or less and the pad size is 20 μm or less. To improve. In addition, by interposing a larger diameter transition layer on the pad of the IC chip, the die pad and the IC may be deposited in an acid or an etchant during a post-process such as a desmear or plating process, or subjected to various annealing processes. There is no risk of melting and damaging the protective film.

각각에 다층프린트배선판 만으로 기능을 수행하고도 있지만, 경우에 따라서는 반도체장치로서의 패키지기판으로서 기능시키기 위해서 외부기판인 마더보드나 도터보드와의 접속을 위해, BGA, 납땜범프나 PGA(도전성접속핀)를 배설시켜도 좋다, 또, 이 구성은, 종래의 실장방법으로 접속한 경우보다도 배선길이를 짧게 할 수 있고, 루프인덕턴스도 저감할 수 있다.Each of them functions only as a multilayer printed circuit board, but in some cases, BGA, solder bumps, or PGA (conductive connecting pins) can be used for connection with a motherboard or daughter board, which is an external board, in order to function as a package board as a semiconductor device. In addition, this structure can shorten a wiring length and can also reduce loop inductance compared with the case where it is connected by the conventional mounting method.

본원 발명에서 정의되고 있는 트랜지션층에 대하여 설명한다.The transition layer defined in the present invention will be described.

트랜지션층은, 종래 기술의 IC칩 실장기술을 사용하지 않고, 반도체소자인 IC칩과 프린트배선판을 직접적으로 접속을 취하기 위해, 설치된 중간의 중개층을 의미한다. 그 특징으로서, 2층 이상의 금속층으로 형성되고 있다. 또는, 반도체소자인 IC칩의 다이패드보다도 크게 하는 것이다. 그로 인해, 전기적 접속이나 위치맞춤성을 향상시키는 것이며, 또, 다이패드에 손상을 부여하는 일 없이 레이저나 포토에칭에 의한 바이어홀가공을 가능하게 하는 것이다. 그 때문에, IC칩의 프린트배선판으로의 매입, 수용, 수납이나 접속을 확실하게 하는 것이 가능하다, 또, 트랜지션층 상에는, 직접, 프린트배선판의 도체층인 금속을 형성하는 것을 가능하게 한다. 그 도체층의 일례로서는, 층간수지절연층의 바이어홀이나 기판 상의 스루홀 등이 있다.The transition layer means an intermediate intermediate layer provided so as to directly connect an IC chip, which is a semiconductor element, and a printed wiring board, without using a conventional IC chip mounting technology. As a characteristic, it is formed from two or more metal layers. Alternatively, it is larger than the die pad of the IC chip which is a semiconductor element. Therefore, electrical connection and alignment are improved, and via hole processing by laser or photo etching is possible without damaging the die pad. Therefore, it is possible to ensure the embedding, accommodating, accommodating or connection of the IC chip to the printed wiring board, and also to form a metal which is a conductor layer of the printed wiring board directly on the transition layer. Examples of the conductor layer include a via hole of an interlayer resin insulating layer, a through hole on a substrate, and the like.

본원 발명에 사용되는 IC칩 등의 전자부품을 내장시키는 수지제 기판으로서는, 에폭시수지, BT수지, 페놀수지 등에 글래스에폭시수지 등의 보강재나 심재를 함침시킨 수지, 에폭시수지를 함침시킨 프리프레그를 적층시킨 것 등이 사용되는데, 일반적으로 프린트배선판으로 사용되는 것은 이용가능하다. 그 이외에도 양면 동장적층판, 편면판, 금속막을 가지지 않는 수지판, 수지필름을 사용하는 것이 가능하다. 단, 350 ℃ 이상의 온도를 가하면 수지는, 용해, 탄화하여 버린다. 또, 세라믹으로는, 외형가공성이 떨어지기 때문에 사용할 수 없다.As a resin board | substrate which embeds electronic components, such as an IC chip used for this invention, laminated | stacked the epoxy resin, BT resin, and phenol resin etc., the resin which impregnated the reinforcement materials, such as glass epoxy resin, the core material, and the prepreg which impregnated the epoxy resin is laminated | stacked. And the like, and generally used as a printed wiring board is available. In addition, it is possible to use a double-sided copper clad laminate, a single-sided plate, a resin plate not having a metal film, and a resin film. However, when temperature of 350 degreeC or more is added, resin will melt | dissolve and carbonize. Moreover, since ceramics are inferior in formability, they cannot be used.

코어기판 등의 초벌의 수지제 절연기판에 IC칩 등의 전자부품을 수용하는 캐비티를 스폿페이싱, 통공, 개구를 형성한 것에 해당 IC칩을 접착제 등으로 접착시킨다.A cavity for accommodating electronic components, such as an IC chip, is formed on a primary resin insulating substrate such as a core substrate, and the IC chip is bonded with an adhesive or the like to form spot facings, through holes, and openings.

IC칩을 내장시킨 코어기판의 전면에 증착, 스패터링 등을 행하고, 전체면에 도전성의 금속막(제 1박막층)을 형성한다. 그 금속으로서는, 주석, 크롬, 티탄, 니켈, 아연, 코발트, 금, 동 등이 좋다. 두께는, 0.001 ~ 2.0 ㎛ 의 사이로 형성시키는 것이 좋다. 0.001 ㎛ 미만으로는, 전면에 균일하게 적층할 수 없다. 2.0 ㎛ 를 넘겨 형성시키는 것은 곤란하고, 효과가 높아지는 것도 아니다. 특히, 0.01 ~ 1.0 ㎛ 가 바람직하다. 크롬의 경우는 0.1 ㎛ 의 두께가 바람직하다.Deposition, sputtering, and the like are carried out on the entire surface of the core substrate in which the IC chip is incorporated, and a conductive metal film (first thin film layer) is formed on the entire surface. As the metal, tin, chromium, titanium, nickel, zinc, cobalt, gold, copper and the like are preferable. It is good to form thickness between 0.001-2.0 micrometers. If it is less than 0.001 micrometer, it cannot be laminated uniformly on the whole surface. It is difficult to form over 2.0 micrometers, and an effect does not become high. In particular, 0.01-1.0 micrometer is preferable. In the case of chromium, a thickness of 0.1 mu m is preferred.

제 1 박막층에 의해, 다이패드의 피복을 행하고, 트랜지션층과 IC칩에 다이패드와의 계면의 밀착성을 높이는 것이 가능하다. 또, 이들 금속으로 다이패드를 피복하는 것으로, 계면으로의 습기의 칩입을 방지하고, 다이패드의 용해, 부식을 방지하며, 신뢰성을 높이는 것이 가능하다. 또, 이 제 1 박막층에 의해, 리드가 없는 실장방법에 의해 IC칩과의 접속을 취하는 것이 가능하다. 여기서, 크롬, 니켈, 티탄을 사용하는 것은, 계면으로의 습기의 침입을 방지하고, 금속밀착성이 뛰어나기 때문이다. 크롬,티탄의 두께는, 스패터층에 크랙이 유발되어 들어가지 않고, 또, 상층의 금속과의 밀착성을 얻을 수 있는 두께로 한다. 그리고, IC칩의 위치결정마크를 기준으로 하여 코어기판에 위치결정마크를 형성한다.By the 1st thin film layer, it is possible to coat | cover a die pad and to improve the adhesiveness of the interface of a die pad to a transition layer and an IC chip. In addition, by coating the die pads with these metals, it is possible to prevent invasion of moisture to the interface, to prevent dissolution and corrosion of the die pads, and to increase reliability. In addition, the first thin film layer can be connected to the IC chip by a mounting method without a lead. The use of chromium, nickel, and titanium is because the intrusion of moisture into the interface is prevented and the metal adhesion is excellent. The thickness of the chromium and titanium is such that no crack is caused to enter the spatter layer, and the thickness of the chromium and titanium can be obtained. Then, the positioning mark is formed on the core substrate based on the positioning mark of the IC chip.

제 1 박막층 상에, 스패터, 증착, 또는, 무전해도금에 의해 제 2 박막층을 형성시킨다. 그 금속으로서는 니켈, 동, 금, 은 등이 있다. 전기특성, 경제성, 또는, 후공정에서 형성되는 두께형성층인 후부층은 주로 동이라는 사실로부터, 동을 사용하면 좋다.On the first thin film layer, a second thin film layer is formed by spattering, vapor deposition, or electroless plating. Examples of the metal include nickel, copper, gold and silver. Copper may be used from the fact that the back layer, which is a thickness-forming layer formed in an electrical property, economics, or a later step, is mainly copper.

여기서 제 2 박막층을 설치하는 이유는, 제 1 박막층으로는, 후술하는 두께형성도금층을 형성하기 위한 전해도금용의 리드를 취하는 것이 불가능하기 때문이다. 제 2 박막층(36)은, 두께형성의 리드로 사용할 수 있다. 그 두께는 0.01 ~ 5 ㎛ 의 범위로 행하는 것이 좋다. 0.01 ㎛ 미만에서는, 리드로서의 역할을 다 할 수 없고, 5 ㎛ 를 넘으면, 에칭 시에, 하층의 제 1 박막층이 보다 많이 부식되어 간극이 생겨, 습기가 침입하기 쉬우며, 신뢰성이 저하되기 때문이다.The reason for providing the second thin film layer is that it is impossible to take a lead for electroplating for forming the thickness forming plating layer described later as the first thin film layer. The second thin film layer 36 can be used as a lead for forming the thickness. It is good to perform the thickness in the range of 0.01-5 micrometers. If the thickness is less than 0.01 µm, it cannot serve as a lead. If the thickness exceeds 5 µm, the first thin film layer under corrosion is more corroded at the time of etching, so that a gap is formed, moisture easily enters, and reliability is lowered. .

제 2 박막층 상에, 무전해 혹은 전해도금에 의해 두께를 형성시킨다. 형성되는 금속의 종류로서는 동, 니켈, 금, 은, 아연, 철 등이 있다. 전기특성, 경제성, 트랜지션층으로서의 강도나 구조상의 내성, 또, 후공정에서 형성되는 빌드업인 도체층은 주로 동이라는 사실로부터, 동을 사용하여 전해도금으로 형성하는 것이 바람직하다. 그 두께는 1 ~ 20 ㎛ 의 범위에서 행하는 것이 좋다. 1 ㎛ 보다 얇으면, 상층의 바이어홀과의 접속신뢰성이 저하하고, 20 ㎛ 보다도 두꺼워지면, 에칭 시에 언더컷이 발생하여, 형성되는 트랜지션층과 바이어홀과 계면에 틈이 발생하기 때문이다. 또, 경우에 따라서는, 제 1 박막층 상에 직접 후부(두꼐형성)도금하여도, 또, 다층으로 적층하여도 좋다.The thickness is formed on the second thin film layer by electroless plating or electroplating. Examples of the metal to be formed include copper, nickel, gold, silver, zinc, iron and the like. It is preferable to form the electrolytic plating using copper from the fact that the conductor layer, which is the build-up formed in the post process, is mainly formed of copper because of its electrical characteristics, economical efficiency, strength as a transition layer, and structural resistance. It is good to perform the thickness in the range of 1-20 micrometers. If the thickness is smaller than 1 µm, the connection reliability with the upper via hole is lowered, and if the thickness is larger than 20 µm, an undercut occurs during etching, and a gap is generated between the formed transition layer and the via hole. In some cases, the film may be directly plated on the first thin film layer or may be laminated in multiple layers.

그 후, 코어기판의 위치결정마크를 기준으로서 에칭레지스트를 형성하고, 노광, 현상하여 트랜지션층 이외의 부분의 금속을 노출시켜 에칭을 행하며, IC칩의 다이패드 상에 제 1 박막층, 제 2 박막층, 후부도금층으로 이루어지는 트랜지션층을 형성시킨다.Subsequently, an etching resist is formed on the basis of the positioning mark of the core substrate, exposed and developed to expose metals other than the transition layer, and etching is performed. The first thin film layer and the second thin film layer are formed on the die pad of the IC chip. The transition layer which consists of a back plating layer is formed.

또, 서브트래프로세스로 트랜지션층을 형성하는 경우에는, 금속막 상에, 무전해 혹은 전해도금에 의해, 후부(두께형성)시킨다. 형성되는 도금의 종류로서는, 동, 니켈, 금, 은, 아연, 철 등이 있다. 전기특성, 경제성, 또, 후공정에서 형성되는 빌드업인 도체층은 주로 동이라는 사실로부터, 동을 사용하는 것이 좋다. 그 두께는 1 ~ 20 ㎛ 의 범위에서 행하는 것이 좋다. 그보다 두꺼워지면, 에칭 시에 언더컷이 발생해하여, 형성되는 트랜지션층과 비어와 계면에 간극이 발생하는 일이 있다. 그 후, 에칭레지스트를 형성하고, 노광, 현상하여 트랜지션층 이외의 부분의 금속을 노출시켜 에칭을 행하고, IC칩의 패드 상에 트랜지션층을 형성시킨다.In the case where the transition layer is formed by the sub-track process, the back layer (thickness formation) is formed on the metal film by electroless or electroplating. Examples of the plating to be formed include copper, nickel, gold, silver, zinc, iron and the like. It is good to use copper from the fact that the conductor layer which is a buildup formed in an electrical property, economics, and a post process is mainly copper. It is good to perform the thickness in the range of 1-20 micrometers. If it becomes thicker than that, undercut may generate | occur | produce at the time of an etching, and the clearance gap may generate | occur | produce in the interface with the transition layer and via which are formed. Thereafter, an etching resist is formed, exposed and developed to expose metals other than the transition layer, and etching is performed to form a transition layer on the pad of the IC chip.

상술한 바와 같이 본 발명자들은, 코어기판에 형성한 오목부인 요부에 IC칩을 수용하고, 해 코어기판 상에 층간수지절연층과 도체회로를 적층시키는 것으로, 패키지기판 내에 IC칩을 내장시키는 것을 안출하였다.As described above, the inventors have found that the IC chip is housed in a recess, which is formed in the core substrate, and the interlayer resin insulating layer and the conductor circuit are laminated on the core substrate to embed the IC chip in the package substrate. It was.

이 방법으로는, IC칩이 수납된 코어기판 상의 전체면에 금속막을 형성하고, 전자부품인 IC칩의 패드를 피복시키거나, 보호시키고, 경우에 따라서는, 해당 패드 상에 트랜지션층을 형성시키는 것에 의해, 패드와 층간수지절연층의 바이어홀과의 전기적 접속을 취한다.In this method, a metal film is formed on the entire surface of the core substrate on which the IC chip is housed, the pad of the IC chip as an electronic component is covered or protected, and in some cases, a transition layer is formed on the pad. This makes electrical connection between the pad and the via hole of the interlayer resin insulating layer.

그러나, 전체면에 금속막이 시공되어 있기 때문에, IC칩 상에 형성된 위치결정마크가 숨겨져 버리기 때문에, 배선 등이 그려진 마스크나 레이저장치 등과 기판의 위치맞춤이 행해질 수 없다. 그 때문에, 해 IC칩의 패드와 바이어홀과의 위치어긋남이 발생해버려, 전기적 접속이 취해질 수 없게 되는 일이 예상되었다.However, since the metal film is constructed on the entire surface, since the positioning mark formed on the IC chip is hidden, the alignment of the substrate with the mask, the laser device, or the like on which the wiring is drawn cannot be performed. For this reason, the positional shift between the pad and the via hole of the IC chip occurs, and electrical connection cannot be established.

본 발명은 상술한 과제를 해결하기 위하여 이루어진 것이며, 그 목적으로 하는 바는, 내장한 IC칩과의 접속을 적절하게 취하는 것이 가능한 다층프린트배선판의 제조방법을 제안하는 것을 목적으로 한다.This invention is made | formed in order to solve the above-mentioned subject, The objective of this invention is to propose the manufacturing method of the multilayer printed wiring board which can take suitably the connection with the built-in IC chip.

청구항 14의 다층프린트배선판의 제조방법으로는, 기판 상에 층간절연층과 도체층을 반복하여 형성하고, 해당 층간절연층에 바이어홀을 형성하며, 해당 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법이며, 적어도 (a) ~ (c) 공정을 구비하는 것을 기술적 특징으로 한다. :In the method for manufacturing a multilayer printed circuit board of claim 14, a multilayer printed circuit board is formed by repeatedly forming an interlayer insulating layer and a conductor layer on a substrate, forming a via hole in the interlayer insulating layer, and electrically connecting the via hole. It is a manufacturing method of, Comprising: It is a technical feature to provide at least (a)-(c) process. :

(a) 상기 기판에 전자부품을 수용하는 공정 ;(a) accommodating an electronic component in the substrate;

(b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 형성하는 공정 ;(b) forming a positioning mark on the substrate based on the positioning mark of the electronic component;

(c) 상기 기판의 위치결정마크에 기초하여 가공 혹는 형성을 행하는 공정.(c) Process of forming or forming based on the positioning mark of the said board | substrate.

청구항 14에서는, 전자부품의 위치결정마크에 기초하여, 전자부품을 수용하는 기판에 위치결정마크를 형성하고, 기판의 위치결정마크에 기초하여 가공 혹은 형성을 행한다. 이 때문에, 전자부품과 위치가 정확히 맞추어지도록, 기판 상의 층간수지절연층에 바이어홀을 형성하는 것이 가능하다.In Claim 14, a positioning mark is formed in the board | substrate which accommodates an electronic component based on the positioning mark of an electronic component, and it processes or forms based on the positioning mark of a board | substrate. For this reason, it is possible to form a via hole in the interlayer resin insulating layer on the substrate so that the position is exactly aligned with the electronic component.

이 경우의 가공이라는 것은, 전자부품인 IC칩 또는 기판 상에 형성되는 것 모두를 의미한다. 예를 들면, IC칩의 패드 상의 트랜지션층, 인식문자(알파벳, 숫자 등), 위치결정마크 등이다.Processing in this case means both the one formed on an IC chip or a substrate which is an electronic component. For example, a transition layer, a recognition character (alphabet, numeral, etc.), a positioning mark, etc. on the pad of an IC chip.

또, 이 경우의 형성이라는 것은, 코어기판 상에 시공된 층간수지절연층(글래스크로스 등의 보강재가 포함되지 않은 것) 상에 형성되는 모든 것을 의미한다. 예를 들면, 바이어홀, 배선, 인식문자(알파벳, 숫자 등), 위치결정마크 등이 있다.In this case, the term "formation" means all formed on an interlayer resin insulating layer (not including reinforcing material such as glass cloth) constructed on a core substrate. For example, there are via holes, wiring, recognition characters (alphabet, numbers, etc.), positioning marks, and the like.

청구항 15의 다층프린트배선판의 제조방법에서는, 기판 상에 층간절연층과 도체층을 반복하여 형성하고, 해당 층간절연층에 바이어홀을 형성하며, 해당 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법이며, 적어도 이하의 (a) ~ (d) 공정을 구비하는 것을 기술적 특징으로 한다.In the method of manufacturing a multilayer printed circuit board of claim 15, the multilayer printed circuit board is formed by repeatedly forming an interlayer insulating layer and a conductor layer on a substrate, forming a via hole in the interlayer insulating layer, and electrically connecting the via hole. It is a manufacturing method, Comprising: It is a technical feature to provide at least the following (a)-(d) processes.

(a) 상기 기판에 전자부품을 수용하는 공정 ;(a) accommodating an electronic component in the substrate;

(b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 레이저로 형성하는 공정 ;(b) forming a positioning mark on the substrate with a laser based on the positioning mark of the electronic component;

(c) 상기 기판의 위치결정마크에 금속막을 형성하는 공정 ;(c) forming a metal film on the positioning mark of the substrate;

(d) 상기 기판의 위치결정마크에 기초하여 가공 혹은 형성을 행하는 공정.(d) Process of processing or forming based on the positioning mark of the said board | substrate.

청구항 15에서는, 전자부품의 위치결정마크에 기초하여, 전자부품을 수용하는 기판에 위치결정마크를 레이저로 천공설치하고, 레이저로 천공설치한 위치결정마크에 금속막을 형성한 후, 기판의 위치결정마크에 기초하여 가공 혹은 형성을 행한다.The method according to claim 15, wherein the positioning mark is punctured with a laser on the substrate containing the electronic component on the basis of the positioning mark of the electronic component, and after the metal film is formed on the positioning mark punctured with the laser, the substrate is positioned. Processing or forming are performed based on the mark.

이 때문에, 전자부품과의 위치가 정확히 맞추어 지도록, 기판 상의 층간수지절연층에 바이어홀을 형성하는 것이 가능하다. 또, 레이저로 천공설치한 위치결정마크에 금속막을 형성하고 있기 때문에, 반사식으로 용이하게 위치결정마크를 인식할 수 있고, 정확하게 위치맞춤을 할 수 있다.For this reason, it is possible to form a via hole in the interlayer resin insulating layer on the substrate so that the position with the electronic component is exactly aligned. In addition, since the metal film is formed on the positioning mark punctured by the laser, the positioning mark can be easily recognized by the reflection type, and the positioning can be accurately performed.

청구항 16의 다층프린트배선판의 제조방법에서는, 기판 상에 층간절연층과 도체층을 반복하여 형성하고, 해당 층간절연층에 바이어홀을 형성하고, 해당 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서, 적어도 이하의 (a) ~ (e) 공정을 구비하는 것을 기술적 특징으로 한다 :In the method for manufacturing a multilayer printed circuit board of claim 16, the multilayer printed circuit board is formed by repeatedly forming an interlayer insulating layer and a conductor layer on a substrate, forming a via hole in the interlayer insulating layer, and electrically connecting the via hole. In the manufacturing method, it is characterized by including at least the following steps (a) to (e):

(a) 상기 기판에 전자부품을 수용하는 공정 ;(a) accommodating an electronic component in the substrate;

(b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 레이저로 형성하는 공정 ;(b) forming a positioning mark on the substrate with a laser based on the positioning mark of the electronic component;

(c) 상기 기판의 위치결정마크에 금속막을 형성하는 공정.(c) forming a metal film on the positioning mark of the substrate.

(d) 상기 기판에 층간절연층을 형성하는 공정 ;(d) forming an interlayer insulating layer on the substrate;

(e) 상기 기판의 위치결정마크에 기초하여 상기 층간절연층에 바이어홀용 개구를 가공 혹은 형성하는 공정.(e) processing or forming the via hole opening in the interlayer insulating layer based on the positioning mark of the substrate.

청구항 16에서는, 전자부품의 위치결정마크에 기초하여, 전자부품을 수용하는 기판에 위치결정마크를 형성하고, 위치결정마크에 금속막을 형성한 후, 기판의 위치결정마크에 기초하여 가공 또는 형성을 행한다. 이 때문에, 전자부품과의 위치가 정확히 맞추어 지도록, 기판 상의 층간절연층에 바이어홀을 형성하는 것이 가능하다. 또, 레이저로 천공설치한 위치결정마크에도 금속막을 형성하고 있기 때문에, 해당 위치결정마크 상에 층간절연층이 형성되어도, 반사식에 의해 화상인식을 행하면, 용이하게 위치결정마크를 인식할 수 있고, 정확하게 위치를 맞추는 것이 가능하다.The method according to claim 16, wherein the positioning mark is formed on a substrate containing the electronic component based on the positioning mark of the electronic component, the metal film is formed on the positioning mark, and processing or forming is performed based on the positioning mark of the substrate. Do it. For this reason, it is possible to form a via hole in the interlayer insulating layer on the substrate so that the position with the electronic component can be exactly aligned. In addition, since the metal film is also formed on the positioning mark punctured by the laser, even if the interlayer insulating layer is formed on the positioning mark, the image can be easily recognized by the reflection type, so that the positioning mark can be easily recognized. , It is possible to precisely position.

상술한 바와 같이 발명자는, 수지절연성기판에 개구부, 통공이나 스폿페이싱을 설치하여, IC칩 등의 전자부품을 미래 내장시켜서, 층간절연층을 적층하고, 해 IC칩의 패드 상에, 포토에칭 혹은 레이저에 의해, 비어를 설치하고, 도체층인 도체회로를 형성시킨 후, 다시, 층간절연층과 도체층을 반복하여 설치해, 다층프린트배선판을 형성하는 것에 의해, 봉지수지를 사용하지 않고, 리드레스, 범프레스에 의해 IC칩과의 전기적 접속을 취하는 것이 가능한 구조를 출안하였다.As described above, the inventors have provided openings, through holes, and spot facings in the resin insulating substrate to embed electronic components such as IC chips in the future, to laminate the interlayer insulating layers, and to photoetch or By using a laser, vias are formed to form a conductor circuit which is a conductor layer, and then an interlayer insulating layer and a conductor layer are repeatedly provided to form a multilayer printed circuit board, thereby forming a multilayer printed wiring board without using a lead resin. The structure which can make electrical connection with an IC chip by bump press was devised.

그러나, IC칩의 패드는, 일반적으로 알루미늄 등으로 제조되고 있고, 제조공정에서 산화하고, 표면에 산화피막이 형성되고 있다. 이 때문에, 표면에 형성된 산화피막에 의해, 패드의 접속저항이 상승해버려서, IC칩으로 적절한 전기적 접속을 얻는 것이 불가능하다는 것이 판명되었다. 또, 다이패드의 상에 산화막이 잔재하면, 패드와 트랜지션층의 밀착성이 불충분하게 되고 신뢰성을 만족시키는 것이 불가능하다는 것을 알게 되었다.However, the IC chip pad is generally made of aluminum or the like, oxidized in the manufacturing process, and an oxide film is formed on the surface. For this reason, it has turned out that the connection resistance of a pad rises by the oxide film formed in the surface, and it is impossible to obtain an appropriate electrical connection with an IC chip. In addition, it has been found that when an oxide film remains on the die pad, the adhesion between the pad and the transition layer becomes insufficient and it is impossible to satisfy the reliability.

본 발명은 상술한 과제를 해결하기 위해 이루어진 것이며, 그 목적으로 하는 것은, IC칩에 리드레스로 적절하게 전기적 접속을 취하는 것이 가능한 다층프린트배선판 및 다층프린트배선판의 제조방법을 제안하는 것을 목적으로 한다.This invention is made | formed in order to solve the above-mentioned subject, and an object of this invention is to propose the manufacturing method of a multilayer printed wiring board and a multilayer printed wiring board which can be suitably made electrical connection to an IC chip. .

상기한 목적을 달성하기 위해, 청구항 17의 다층프린트배선판의 제조방법으로는, 적어도 이하의 (a) ~ (e) 의 공정을 구비하는 것을 기술적 특징으로 한다 :In order to achieve the above object, the manufacturing method of the multilayer printed circuit board of claim 17 is characterized by comprising at least the following steps (a) to (e):

(a) 상기 기판에 전자부품을 수용하는 공정 ;(a) accommodating an electronic component in the substrate;

(b) 상기 전자부품의 다이패드의 표면의 피막을 제거하는 공정 ;(b) removing the coating on the surface of the die pad of the electronic component;

(c) 상기 다이패드 상에, 최하층의 층간절연층의 바이어홀과 접속시키기 위한 트랜지션층을 형성하는 공정.(c) forming a transition layer on the die pad to connect with the via hole of the lowest interlayer insulating layer.

(d) 상기 기판 상에, 층간절연층을 형성하는 공정 ;(d) forming an interlayer insulating layer on the substrate;

(e) 상기 층간절연층에, 도체회로 및 트랜지션층에 접속하는 바이어홀을 형성하는 공정.(e) forming a via hole connected to the conductor circuit and the transition layer in the interlayer insulating layer.

청구항 17에서는, 기판 내에 IC칩을 수용하기 때문에, 리드레스로 IC칩과의 전기적 접속을 취하는 것이 가능하였다. 또, IC칩 등의 전자부품의 다이패드의 접속면에 산화피막제거처리를 시공하기 때문에, 다이패드의 전기저항을 낮추고, 도전성을 높이는 것이 가능해진다. 또, IC칩 부분에 트랜지션층을 설치하는 것에 의해, IC칩 부분이 평탄화되기 때문에, 상층의 층간절연층도 평탄화되고, 막의 두께도 일정하게 된다. 그 뿐 아니라, 바이어홀을 형성하는 때에도, 형성의 안정성을 유지하는 것이 가능하다. 피막은 완전하게 제거하는 것이 바람직하다.In claim 17, since the IC chip is accommodated in the substrate, it is possible to establish electrical connection with the IC chip in a leadless manner. In addition, since the oxide film removing treatment is applied to the connection surface of the die pad of an electronic component such as an IC chip, the electrical resistance of the die pad can be lowered and the conductivity can be increased. In addition, since the IC chip portion is flattened by providing a transition layer in the IC chip portion, the interlayer insulating layer in the upper layer is also flattened and the film thickness is constant. In addition, it is possible to maintain the stability of the formation even when forming the via hole. It is preferable to remove a film completely.

청구항 18에서는, 산화피막을 역스패터, 플래즈마처리의 어느 하나로 완전히 제거하는 것에 의해, IC칩의 다이패드의 도전성을 높이는 것이 가능하게 된다.In claim 18, by completely removing the oxide film by either reverse spattering or plasma treatment, the conductivity of the die pad of the IC chip can be increased.

역스패터를 행하는 경우는, 스패터링가스로서 아르곤 등의 불활성가스를 사용하고, 다이패드 표면의 산화피막에 역스패터링을 행하여 산화피막을 완전하게 제거한다. 플라즈마처리로 행하는 경우는, 기판을 진공상태로 한 장치 내에 넣어, 산소, 혹은, 질소, 탄소가스, 사불화탄소 중에 플라즈마를 방출시켜 다이패드 표면의 산화피막을 제거시킨다.In the case of reverse sputtering, an inert gas such as argon is used as the sputtering gas, and reverse sputtering is performed on the oxide film on the surface of the die pad to completely remove the oxide film. In the case of performing the plasma treatment, the substrate is placed in a vacuum apparatus, and plasma is released in oxygen, nitrogen, carbon gas, and carbon tetrafluoride to remove the oxide film on the surface of the die pad.

청구항 19에서는, 피막제거와, 트랜지션층의 최하층의 형성을, 연속적으로 비산소분위기 중에서 행하기 때문에, 패드표면에 산화피막이 다시 형성되는 일이 없고, IC칩의 다이패드와 트랜지션층과의 사이의 도전성을 밀착성을 높이는 것이가능하다.19. Since the film removal and the formation of the lowest layer of the transition layer are continuously performed in a non-oxygen atmosphere, the oxide film is not formed on the pad surface again, and the die pad of the IC chip and the transition layer are not formed. It is possible to improve the adhesiveness of the conductivity.

청구항 20의 다층프린트배선판은, 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 해당 층간절연층에는, 바이어홀이 형성되고, 해당 바이어홀을 개재하여 전기적 접속되는 다층프린트배선판에 있어서,In the multilayer printed circuit board of claim 20, wherein the interlayer insulating layer and the conductor layer are repeatedly formed on the substrate, the via insulation layer is formed in the interlayer insulating layer, and is electrically connected through the via hole.

상기 기판에는, 전자부품이 내장되고,In the substrate, an electronic component is embedded,

상기 전자부품의 다이패드 상에는, 최하층의 층간절연층의 바이어홀과 접속시키기 위한 트랜지션층이 형성되고,On the die pad of the electronic component, a transition layer for connecting with the via hole of the lowest interlayer insulating layer is formed,

상기 다이패드의 표면의 피막이 제거되어 있는 것을 기술적 특징이라고 한다.It is called technical feature that the film of the surface of the said die pad is removed.

청구항 20에서는, 기판 내에 IC칩을 수용하기 때문에, 리드레스로 IC칩과의 전기적 접속을 취하는 것이 가능하다. 또, IC칩 등의 전자부품의 다이패드의 접속면에 산화피막제거처리를 시공하기 때문에, 다이패드의 전기저항을 낮추고, 도전성을 높이는 것이 가능해진다. 또, IC칩 부분에 트랜지션층을 설치하는 것에 의해, IC칩 부분이 평탄화되기 때문에, 상층의 층간절연층도 평탄화되고, 막의 두께도 일정하다. 그 뿐 아니라, 바이어홀을 형성하는 때에도, 형상의 안정성을 유지하는 것이 가능하다. 피막은 완전하게 제거하는 편이 좋다.In claim 20, since the IC chip is accommodated in the substrate, it is possible to establish electrical connection with the IC chip in a leadless manner. In addition, since the oxide film removing treatment is applied to the connection surface of the die pad of an electronic component such as an IC chip, the electrical resistance of the die pad can be lowered and the conductivity can be increased. In addition, since the IC chip portion is flattened by providing a transition layer in the IC chip portion, the interlayer insulating layer in the upper layer is also flattened and the film thickness is constant. In addition, it is possible to maintain the stability of the shape even when forming the via hole. It is better to remove the film completely.

이하, 본 발명의 실시형태에 대하여 도면을 참조하여 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

〔제 1 실시형태〕[First Embodiment]

우선, 본 발명의 제 1 실시형태에 관계하는 다층프린트배선판의 구성에 대하여, 다층프린트배선판(10)의 단면을 도시하는 도 6 을 참조하여 설명한다.First, the structure of the multilayer printed circuit board according to the first embodiment of the present invention will be described with reference to FIG. 6 showing a cross section of the multilayer printed circuit board 10.

도 6 에 도시하는 바와 같이 다층프린트배선판(10)은, IC칩(20)을 수용하는 코어기판(30)과, 층간수지절연층(50), 층간수지절연층(150)으로 된다. 층간수지절연층(50)에는, 바이어홀(60) 및 도체회로(58)가 형성되고, 층간수지절연층(150)에는, 바이어홀(160) 및 도체회로(158)이 형성되고 있다.As shown in FIG. 6, the multilayer printed circuit board 10 includes a core substrate 30 accommodating the IC chip 20, an interlayer resin insulating layer 50, and an interlayer resin insulating layer 150. The via hole 60 and the conductor circuit 58 are formed in the interlayer resin insulating layer 50, and the via hole 160 and the conductor circuit 158 are formed in the interlayer resin insulating layer 150.

IC칩(20)에는, 패시베이션막(24)이 피복되고, 패시베이션막(24)의 개구 내에 입출력단자를 구성하는 다이패드(24)가 배설되고 있다. 알루미늄제의 다이패드(24) 상에는, 트랜지션층(38)이 형성되고 있다. 트랜지션층(38)은, 제 1 박막층(33), 제 2 박막층(36), 후부(두께형성)막(37)의 3 층으로 이루어딘다.The passivation film 24 is covered with the IC chip 20, and a die pad 24 constituting the input / output terminal is disposed in the opening of the passivation film 24. The transition layer 38 is formed on the die pad 24 made from aluminum. The transition layer 38 is composed of three layers of the first thin film layer 33, the second thin film layer 36, and the rear (thickness forming) film 37.

층간수지절연층(150) 상에는, 솔더레지스트층(70)이 배설되고 있다. 솔더레지스트층(70)의 개구부(71) 하의 도체회로(158)에는, 도시하지 않은 도터보드, 마더보드 등의 외부기판과 접속하기 위한 BGA(76)가 설치되어있다.On the interlayer resin insulating layer 150, a solder resist layer 70 is disposed. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with a BGA 76 for connecting to an external substrate such as a daughter board, a motherboard, and the like which is not shown.

제 1 실시형태의 다층프린트배선판(10)에는, 코어기판(30)에 IC칩(20)을 미리 내장시키고, 해당 IC칩(20)의 다이패드(24)에는 트랜지션층(38)을 배설시키고 있다. 이 때문에, 리드부품이나 봉지수지를 사용하지 않고, IC칩과 다층프린트배선판(패키지기판)과의 전기적 접속을 취하는 것이 가능하다. IC칩 부분에는 평탄화시키기 때문에, 상층의 층간절연층(50)도 평탄화되고, 막두께도 균일하게 된다. 또, 트랜지션층에 의해, 상층의 바이어홀(60)을 형성할 때에도 형상의 안정성을 유지하는 것이 가능하다.In the multilayer printed circuit board 10 of the first embodiment, the IC chip 20 is built in the core substrate 30 in advance, and the transition layer 38 is disposed in the die pad 24 of the IC chip 20. have. For this reason, it is possible to make electrical connection with an IC chip and a multilayer printed wiring board (package substrate), without using a lead component or sealing resin. Since the IC chip portion is planarized, the upper interlayer insulating layer 50 is also planarized and the film thickness is uniform. In addition, it is possible to maintain the stability of the shape even when the upper layer via hole 60 is formed by the transition layer.

또, 다이패드(24) 상에 동제의 트랜지션층(38)을 설치하는 것으로서, 다이패드(24) 상의 수지잔류를 방지할 수 있고, 또, 후가공 시에 산이나 산화제 혹은 에칭액에 침적시키거나, 각각의 아닐공정을 거쳐도 다이패드(24)의 변색, 용해가 발생하지 않는다. 이로 인해, IC칩의 다이패드와 바이어홀과의 접속성이나 신뢰성을 향상시킨다. 또, 40 ㎛ 전후의 직경의 다이패드(24) 상에 60 ㎛ 직경 이상의 트랜지션층(38)을 개재시키는 것으로, 60 ㎛ 직경의 바이어홀을 정확하게 접속시키는 것이 가능하다.Moreover, by providing the copper transition layer 38 on the die pad 24, the resin residue on the die pad 24 can be prevented, and it is immersed in an acid, an oxidizing agent, or an etching solution at the time of post-processing, Discoloration and dissolution of the die pad 24 do not occur even after each annealing process. This improves the connectivity and reliability of the die pad of the IC chip and the via hole. Moreover, via the transition layer 38 of 60 micrometers diameter or more on the die pad 24 of 40 micrometers diameter around, the via hole of 60 micrometers diameter can be connected correctly.

계속해서, 도 6 을 참조하여 상술한 다층프린트배선판의 제조방법에 대하여, 도 1 ~ 도 5 를 참조하여 설명한다.Subsequently, the manufacturing method of the multilayer printed wiring board described above with reference to FIG. 6 will be described with reference to FIGS. 1 to 5.

(1) 우선, 글래스크로스 등의 심재에 에폭시 등의 수지를 함침시킨 프리프래그를 적층한 절연수지기판(코어기판)(30)을 출발재료로 한다(도 1(A)참조). 다음으로, 코어기판(30)의 한쪽 면에, 스폿페이싱가공으로 IC칩 수용부의 오목부인 요부(32)를 형성한다.(도 1(B)참조). 여기서는, 스폿페이싱가공에 의해 요부를 설치하고 있지만, 개구를 설치한 절연수지기판과 개구를 설치하지 않은 수지절연기판을 맞춰붙임으로써, 수용부를 구비하는 코어기판을 형성할 수 있다.(1) First, an insulating resin substrate (core substrate) 30 having a prepreg obtained by impregnating a resin such as epoxy on a core material such as glass cross is used as a starting material (see Fig. 1 (A)). Next, a recess 32 is formed on one surface of the core substrate 30 as a recess of the IC chip accommodating portion by spot facing processing (see Fig. 1 (B)). In this case, the recessed portion is provided by spot facing, but the core substrate provided with the accommodation portion can be formed by joining the insulating resin substrate with the opening and the resin insulating substrate without the opening.

(2) 그 후, 요부(32)에, 인쇄기를 사용하여 접착재료(34)를 도포한다. 이 때, 도포 이외에도, 폿팅 등을 하여도 좋다. 다음으로, IC칩(20)을 접착재료(34) 상에 적재한다.(도 1(C)참조).(2) Then, the adhesive material 34 is apply | coated to the recessed part 32 using the printing machine. At this time, potting or the like may be performed in addition to the coating. Next, the IC chip 20 is mounted on the adhesive material 34 (see Fig. 1C).

(3) 그리고, IC칩(20)의 상면을 누르거나 혹은 두드려서 요부(32) 내에 완전히 수용시킨다(도 1(D)참조). 이로 인해, 코어기판(30)을 평활하게 하는 것이 가능하다.(3) Then, the upper surface of the IC chip 20 is pressed or knocked to completely accommodate the recess 32 (see FIG. 1 (D)). For this reason, it is possible to make the core board | substrate 30 smooth.

(4) 그 후, IC칩(20)을 수용시킨 코어기판(30)의 전면에 증착, 스팻터링 등을 행하고, 전체면에 도전성의 제 1 박막층(33)을 형성시킨다.(도 2(A)). 그 금속으로서는, 주석, 크롬, 티탄, 니켈, 아연, 코발트, 금, 동 등이 좋다. 특히, 니켈, 크롬, 티탄을 사용하는 것이, 계면에서의 습기의 침입을 억제하고, 또 막형성 상, 전기특성 상으로 적합하다. 두께로서는, 0.001 ~ 2.0 ㎛ 의 사이에서 형성시키는 것이 좋고, 특히 0.01 ~ 1.0 ㎛ 이 더욱 바람직하다. 크롬의 경우에는 0.1 ㎛ 의 두께가 바람직하다.(4) After that, vapor deposition, spattering, and the like are carried out on the entire surface of the core substrate 30 containing the IC chip 20, thereby forming a conductive first thin film layer 33 on the entire surface. )). As the metal, tin, chromium, titanium, nickel, zinc, cobalt, gold, copper and the like are preferable. In particular, the use of nickel, chromium, or titanium is suitable for suppressing the ingress of moisture at the interface and in terms of film formation and electrical properties. As thickness, it is good to form between 0.001-2.0 micrometers, and especially 0.01-1.0 micrometer is more preferable. In the case of chromium, a thickness of 0.1 mu m is preferred.

제 1 박막층(33)에 의해, 다이패드(24)의 피복을 행하고, 트랜지션층과 IC칩에 다이패드(24)와의 계면의 밀착성을 높이는 것이 가능하다. 또, 이들 금속으로다이패드(24)를 피복하는 것으로, 계면으로의 습기의 침입을 방지하고, 다이패드의 용해, 부식을 방지하고, 신뢰성을 높이는 것이 가능하다. 또, 이 제 1 박막층(33)에 의해, 리드가 없는 실장방법에 의해 IC칩과의 접속을 취하는 것이 가능하다. 여기서, 크롬, 티탄, 니켈을 사용하는 것이, 계면으로의 습기의 침입을 방지하고, 금속밀착성이 높인다는 점에서 좋다.By the first thin film layer 33, the die pads 24 can be coated to increase the adhesion of the interface between the die pads 24 to the transition layer and the IC chip. In addition, by coating the die pads 24 with these metals, it is possible to prevent ingress of moisture into the interface, to prevent dissolution and corrosion of the die pads, and to increase reliability. In addition, the first thin film layer 33 can be connected to the IC chip by a mounting method without a lead. It is preferable to use chromium, titanium and nickel in that it prevents the invasion of moisture to an interface and improves metal adhesiveness.

(5) 제 1 박막층(33) 상에, 스패터, 증착, 또는, 무전해도금에 의해, 제 2 박막층(36)을 형성시킨다.(도 2(B)). 그 금속으로서는 니켈, 동, 금, 은 등이 있다. 전기특성, 경제성, 또, 후공정에서 형성되는 빌드업인 도체층은 주로 동이라는 사실로부터, 동을 사용하면 좋다.(5) On the first thin film layer 33, the second thin film layer 36 is formed by spattering, vapor deposition, or electroless plating. (FIG. 2B). Examples of the metal include nickel, copper, gold and silver. It is good to use copper from the fact that the conductor layer which is a buildup formed in an electrical property, economics, and a post process is mainly copper.

제 2 박막층을 설치하는 이유는, 제 1 박막층에서는, 후술하는 후부층을 형성하기 위한 전해도금용의 리드를 취하는 것이 불가능하였기 때문이다. 제 2 박막층(36)은, 후부의 리드로서 사용된다. 그 두께는 0.01 ~ 5 ㎛ 의 범위에서 행하는 것이 좋다. 특히, 0.1 ~ 3 ㎛ 의 사이가 바람직하고, 제 1 박막층의 피복과 리드에 최적이다. 0.01 ㎛ 미만에서는, 리드로서의 역학을 다할 수 없고, 5 ㎛ 을 넘으면, 에칭 시, 하층의 제 1 박막층보다 많이 부식되어 간격이 생겨버려, 습기가 침입하기 쉽고, 신뢰성이 저하하기 때문이다.The reason for providing the second thin film layer is that in the first thin film layer, it was impossible to take a lead for electroplating for forming a rear layer which will be described later. The second thin film layer 36 is used as the rear lead. It is good to perform the thickness in the range of 0.01-5 micrometers. Especially, between 0.1-3 micrometers is preferable, and it is optimal for coating | coating and lead of a 1st thin film layer. If the thickness is less than 0.01 µm, the mechanics as a lead cannot be fulfilled. If the thickness exceeds 5 µm, it is more corroded than the first thin film layer at the time of etching, causing gaps, leading to moisture intrusion, and lowering of reliability.

또, 바람직한 제 1 박막층과 제 2 박막층과의 조합은, 크롬-동, 크롬-니켈, 티탄-동, 티탄-니켈 등이다. 금속과의 신뢰성이나 전기전도성이라는 점에서 다른 조합보다도 뛰어나다.Moreover, the combination of a preferable 1st thin film layer and a 2nd thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel etc. It is superior to other combinations in terms of reliability and electrical conductivity with metals.

(6) 그 후, 레지스트를 도포하고, 노광, 현상하여 IC칩의 다이패드의 상부에개구를 설치하도록 도금레지스트(35)를 설치하고, 이하의 조건에서 전해도금을 시공하고, 전해도금막(후부막)(37)을 설치한다(도 2(C)).(6) After that, a resist is applied, exposed and developed to provide a plating resist 35 so as to provide an opening on the die pad of the IC chip, and electroplating is applied under the following conditions. Thick film) 37 (FIG. 2C).

〔전해도금수용액〕[Electrolytic plating solution]

유산 2.24 mol/1Heritage 2.24 mol / 1

유산동 0.26 mol/1Lactic acid copper 0.26 mol / 1

첨가제(어드텍저팬제, 카파라시드HL) 19.5 ml/119.5 ml / 1 of additives (product made in the protector fan, capara seed HL)

〔전해도금조건〕[Electroplating condition]

전류밀도 1 A/dm2 Current density 1 A / dm 2

시간 65 분65 minutes

습도 22 ± 2 ℃Humidity 22 ± 2 ℃

도금레지스트(35)를 제거한 후, 도금레지스트(35) 하의 무전해 제 2 박막층(36), 제 1 박막층(33)을 에칭으로 제거하는 것으로, IC칩의 다이패드(24) 상에 트랜지션층(38)을 형성한다(도 2(D)). 여기서는, 도금레지스트에 의해 트랜지션층을 형성하였는데, 무전해 제 2 박막층(36) 상에 전해도금막을 균일하게 형성한 후, 에칭레지스트를 형성하고, 노광, 현상하고 트랜지션층 이외의 부분의 금속을 노출시켜서 에칭을 행하고, IC칩의 다이패드 상에 트랜지션층을 형성시키는 것도 가능하다. 전해도금막의 두께는 1 ~ 20 ㎛ 의 범위가 좋다. 그보다 두꺼워지면, 에칭 시에 언더컷이 발생해버리고, 형성되는 트랜지션층과 바이어홀과 계면에 간격이 발생하는 일이 있기 때문이다.After removing the plating resist 35, the electroless second thin film layer 36 and the first thin film layer 33 under the plating resist 35 are removed by etching to form a transition layer on the die pad 24 of the IC chip. 38) (FIG. 2 (D)). Here, a transition layer was formed of a plating resist. After forming an electroplating film uniformly on the electroless second thin film layer 36, an etching resist was formed, exposed and developed, and the metals of parts other than the transition layer were exposed. And etching to form a transition layer on the die pad of the IC chip. The thickness of the electroplated film is preferably in the range of 1 to 20 µm. If it is thicker than that, undercut may occur during etching, and a gap may occur between the transition layer, the via hole, and the interface formed.

(7) 다음으로, 기판에 에칭액을 스프레이로 뿌리고, 트랜지션층(38)의 표면을 에칭하는 것에 의해 조화면(38α)를 형성한다(도 3(A)참조). 무전해도금이나 산화환원처리를 사용하여 조화면을 형성하는 것도 가능하다. 도 3(A) 중의 트랜지션층(38)을 확대하여 도 7(A)에 도시하고, 도 7(A)의 B 화살표에서 본 도면을 도 7(B)에 도시한다. 트랜지션층(38)은, 제 1 박막층(33), 제 2 박막층(36), 후부막(37)의 3층 구조로 이루어진다. 도 7(A)에 도시하는 바와 같이, 트랜지션은 원형으로 형성되고 있지만, 그 대신에, 도 7(C)에 도시하는 바와 같이 타원형으로, 도 7(D)에 도시하는 바와 같이 사각형으로, 도 7(E)에 도시하는 바와 같이 작은 모서리가 둥근 사각형으로 형성하는 것도 가능하다.(7) Next, an etching solution is sprayed onto the substrate, and the rough surface 38α is formed by etching the surface of the transition layer 38 (see Fig. 3A). It is also possible to form a roughened surface using electroless plating or redox treatment. The transition layer 38 in FIG. 3 (A) is enlarged and shown in FIG. 7 (A), and the figure seen from the arrow B of FIG. 7 (A) is shown in FIG. The transition layer 38 has a three-layer structure of the first thin film layer 33, the second thin film layer 36, and the rear film 37. As shown in Fig. 7 (A), the transition is formed in a circular shape, but instead is elliptical as shown in Fig. 7 (C) and in a rectangle as shown in Fig. 7 (D). As shown in 7 (E), it is also possible to form a small square with a rounded corner.

(8) 상기 공정을 거친 기판에, 두께 50 ㎛ 의 열경화형수지시트를 온도 50 ~ 150 ℃ 까지 승온하면서 압력 5 ㎏/㎠ 로 진공압착 라미네이트하고, 층간수지절연층(50)을 설치한다(도 3(B)참조). 진공압착 시의 진공도는, 10 mmHg 이다.(8) On the substrate subjected to the above process, a thermosetting resin sheet having a thickness of 50 µm was vacuum-pressed laminated at a pressure of 5 kg / cm 2 while raising the temperature to a temperature of 50 to 150 ° C, and an interlayer resin insulating layer 50 was provided (Fig. 3 (B)). The vacuum degree at the time of vacuum compression is 10 mmHg.

(9) 다음으로, 파장 10.4 ㎛ 의 CO2가스레이저로, 빔경 5 mm, 톱핫모드, 펄스폭 5.0 마이크로 초, 마스크 구멍경 0.5 mm, 1 쇼트의 조건으로, 층간수지절연층(50)에 직경 80 ㎛ 의 바이어홀용 개구(48)을 설치한다(도 3(C)참조). 크롬산을 사용하여, 개구(48) 내의 수지잔재를 제거한다. 다이패드(24) 상에 동제의 트랜지션층(38)을 설치하는 것으로, 다이패드(24) 상의 수지잔재를 방지하는 것이 가능하고, 이로 인해, 다이패드(24)와 후술하는 바이어홀(60)과의 접속성이나 신뢰성을 향상시킨다. 또, 40 ㎛ 경 전후의 다이패드(24) 상에 60 ㎛ 이상의지름의 트랜지션층(38)을 개재시키는 것으로, 60 ㎛ 경의 바이어홀용 개구(48)을 확실하게 접속시키는 것이 가능하다. 또, 여기서는, 과망간산을 사용하여 수지잔재를 제거하고 있지만, 산소플라즈마를 사용하여 데스미어처리를 행하는 것도 가능하다.(9) Next, the CO 2 gas laser having a wavelength of 10.4 μm, the diameter of the interlayer resin insulating layer 50 under conditions of a beam diameter of 5 mm, a top hot mode, a pulse width of 5.0 microseconds, a mask hole diameter of 0.5 mm, and one shot. An 80 μm via hole opening 48 is provided (see FIG. 3 (C)). Using chromic acid, the resin residue in the opening 48 is removed. By providing the copper transition layer 38 on the die pad 24, it is possible to prevent the resin residue on the die pad 24, and thus the die pad 24 and the via hole 60 to be described later. Improves connectivity and reliability. In addition, by interposing a transition layer 38 having a diameter of 60 µm or more on the die pads 24 around 40 µm diameter, the via hole opening 48 having a diameter of 60 µm can be reliably connected. In addition, although the resin residue is removed using permanganic acid here, it is also possible to perform a desmear process using oxygen plasma.

(10) 다음으로, 크롬산, 과망간산염 등의 산화제 등에 침적시킴에 의하여, 층간수지절연층(50)의 조화면(50α)을 설치한다(도 3(D)참조). 상기 조화면(50α)은, 0.05 ~ 5 ㎛ 의 범위로 형성하는 것이 좋다. 그 일례로서, 과망간산나트륨용액 50 g/1, 습도 60 ℃ 중에서 5 ~ 25 분간 침적시키는 것에 의해, 1 ~ 5 ㎛ 의 조화면(50α)을 설치한다. 상기 이외에는, 일본진공기술주식회사제의 SV-4540 을 사용하여 플라즈마처리를 행하고, 층간수지절연층(50)의 표면에 조화면(50α)을 형성하는 것도 가능하다. 이 때, 불활성가스로서는 아르곤가스를 사용하고, 전력 200 W, 가스압 0.6 Pa, 온도 70 ℃의 조건으로, 2분간 플라즈마처리를 실시한다.(10) Next, by immersing in an oxidizing agent such as chromic acid, permanganate, or the like, a roughened surface 50 alpha of the interlayer resin insulating layer 50 is provided (see FIG. 3 (D)). It is preferable to form the roughened surface 50α in the range of 0.05 to 5 µm. As an example, a rough surface 50α of 1 to 5 탆 is provided by immersing for 5 to 25 minutes in 50 g / 1 of sodium permanganate solution and 60 ° C of humidity. In addition to the above, plasma treatment may be performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. to form a roughened surface 50α on the surface of the interlayer resin insulating layer 50. At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under conditions of a power of 200 W, a gas pressure of 0.6 Pa, and a temperature of 70 ° C.

(11) 조화면(50α)이 형성된 층간수지절연층(50) 상에, 금속층(52)을 설치한다(도 4(A)참조). 금속층(52)은, 무전해도금에 의해 형성시킨다. 미리 층간수지절연층(50)의 표층에 팔라디움 등의 촉매를 부여시키고, 무전해도금액에 5 ~ 60 분간 침적시키는 것에 의해, 0.1 ~ 5 ㎛ 의 범위로 도금막인 금속층(52)를 설치한다. 그 일례로서,(11) A metal layer 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (see Fig. 4A). The metal layer 52 is formed by electroless plating. By applying a catalyst such as palladium to the surface layer of the interlayer resin insulating layer 50 in advance and depositing it in the electroless solution for 5 to 60 minutes, the metal layer 52 serving as the plating film is provided in the range of 0.1 to 5 mu m. As an example

〔무전해도금수용액〕(Electroless plating solution)

NiSO40.003 mol/1NiSO 4 0.003 mol / 1

주석산 0.200 mol/1Tartaric acid 0.200 mol / 1

유산동 0.030 mol/1Lactic acid copper 0.030 mol / 1

HCHO 0.050 mol/1HCHO 0.050 mol / 1

NaOH 0.100 mg/1NaOH 0.100 mg / 1

α,α`-비피르딜 100 mg/1α, α`-bipyridyl 100 mg / 1

폴리에틸렌글리콜(PEG) 0.10 g/1Polyethylene glycol (PEG) 0.10 g / 1

34℃의 액온도로 40분간 침적시켰다.It was deposited for 40 minutes at a liquid temperature of 34 ° C.

상기 이외에도 상술한 플래즈마처리와 같은 장치를 사용하고, 내부의 아르곤가스를 교환한 후, Ni 및 Cu를 타켓으로 한 스패터링을, 기압 0.6 Pa, 온도 80 ℃, 전력 200 W, 시간 5분간의 조건에서 행하고, Ni/Cu 금속층(52)를 층간수지절연층(50)의 표면에 형성하는 것도 가능하다. 이 때, 형성되는 Ni/Cu 금속층(52)의 두께는 0.2 ㎛ 이다. 또, 스패터 대신에, 증착, 전착 등으로 금속막을 형성하는 것도 가능하다. 또, 스패터, 증착, 전착 등의 물리적인 방법으로 얇은층을 형성한 후, 무전해도금을 실시하는 것도 가능하다.In addition to the above, after using an apparatus such as the plasma treatment described above, the internal argon gas was exchanged, and then sputtering targeting Ni and Cu was performed at an air pressure of 0.6 Pa, a temperature of 80 ° C., a power of 200 W, and a time of 5 minutes. Under the conditions, the Ni / Cu metal layer 52 may be formed on the surface of the interlayer resin insulating layer 50. At this time, the thickness of the formed Ni / Cu metal layer 52 is 0.2 탆. In addition, it is also possible to form a metal film by vapor deposition, electrodeposition, etc. instead of a spatter. Moreover, after forming a thin layer by physical methods, such as spatter, vapor deposition, and electrodeposition, electroless plating can also be performed.

(12) 상기 처리를 끝낸 기판(30)에, 시판의 감광성 드라이필름을 붙이고, 크롬글래스 마스크를 적재하고, 40 mJ/㎠ 로 노광한 후, 0.8 % 탄산나트륨으로 현상처리하고, 두께 25 ㎛ 의 도금레지스트(54)를 설치한다. 다음으로, 이하의 조건에서 전해도금을 실시하고, 두께 18 ㎛ 의 전해도금막(56)을 형성한다(도 4(B)참조). 또, 전해도금수용액의 첨가제는, 어드텍저팬사제의 카파라시드HL이다.(12) A commercially available photosensitive dry film was attached to the substrate 30 after the above treatment, a chromium glass mask was loaded, exposed to 40 mJ / cm 2, then developed with 0.8% sodium carbonate, and plated with a thickness of 25 μm. The resist 54 is provided. Next, electroplating is carried out under the following conditions to form an electroplating film 56 having a thickness of 18 탆 (see Fig. 4B). In addition, the additive of the electroplating aqueous solution is kappa seed HL made from the protector fan company.

〔전해도금수용액〕[Electrolytic plating solution]

유산 2.24 mol/1Heritage 2.24 mol / 1

유산동 0.26 mol/1Lactic acid copper 0.26 mol / 1

첨가제(어드택저팬제, 카파라시드HL) 19.5 ml/119.5 ml / 1 of additives (adjuster pan agent, capara seed HL)

〔전해도금조건〕[Electroplating condition]

전류밀도 1 A/dm2 Current density 1 A / dm 2

시간 65 분65 minutes

습도 22 ± 2 ℃Humidity 22 ± 2 ℃

(13) 도금레지스트(54)를 5 % NaOH 로 박리제거한 후, 그 도금레지스트 하의 금속층(52)을 초산 및 유산과 과산화수소의 혼합액을 사용하는 에칭으로 용해제거하고, 금속층(52)와 전해도금막(56)으로 이루어진 두께 16 ㎛ 의 도체회로(58) 및 바이어홀(60)을 형성하고, 제 2동착체와 유기산을 함유하는에칭액에 의해, 조화면 58α, 60α을 형성한다(도 4(C)참조). 무전해도금이나 산화환원처리를 사용하여 조화면을 형성하는 것이 가능하다.(13) After the plating resist 54 is peeled off with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixture of acetic acid, lactic acid and hydrogen peroxide, and the metal layer 52 and the electroplated film. A conductive circuit 58 and a via hole 60 having a thickness of 16 µm made of 56 are formed, and roughened surfaces 58α and 60α are formed by etching liquid containing a second complexing body and an organic acid (Fig. 4 (C). )Reference). It is possible to form a roughened surface using electroless plating or redox treatment.

(14) 이어서, 상기 (9) ~ (13)의 공정을, 반복하는 것에 의해, 또 상층의 층간수지절연층(150) 및 도체회로(158)(바이어홀(160)을 포함)을 형성한다(도 5(A)참조).(14) Subsequently, the steps (9) to (13) are repeated to form an upper interlayer resin insulating layer 150 and a conductor circuit 158 (including the via hole 160). (See FIG. 5 (A)).

(15) 다음으로, 디에틸렌글리콜디메틸에테르(DMDG)에 60 중량% 의 농도가 되도록 용해시킨, 크레졸노볼락형 에폭시수지(일본화약사제)의 에폭시기 50 % 를 아크릴화한 감광성부여의 오리고머(분자량 4000) 46.67 중량부, 메틸에틸케톤에 용해시킨 80 중량% 의 비스페놀A형 에폭시수지(유화셀사제, 상품명 : 에피코트1001) 15 중량부, 이미다졸경화제(사국화성사제, 상품명 : 2E4MZ-CN) 1.6 중량부, 감광성 모노머인 다관능아크릴모노마(공영화학사제, 상품명 : R604) 3 중량부, 마찬가지로 다가아크릴모노머(공영화학사제, 상품명 : DPE6A) 1.5 중량부, 분산계소포제(산높코사제, 상품명 : S-65) 0.71 중량부를 용기에 덜어, 교반, 혼합하여 혼합조합물을 조정하고, 이 혼합조합물에 대하여 광중량개시제로서 벤조페논(관동화학사제) 2.0 중량부, 광증감제로서의 미히라케톤(관동화학제) 0.2 중량부를 가하여, 점도를 25 ℃ 에서 2.0 Pa·s 로 조정한 솔더레지스트조성물(유기수지절연재료)을 얻는다.(15) Next, a photosensitive impregnated oligomer (molecular weight) in which 50% of an epoxy group of a cresol novolak-type epoxy resin (manufactured by Nippon Chemical Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) was dissolved to a concentration of 60% by weight. 4000) 46.67 parts by weight, 15 parts by weight of 80% by weight of bisphenol A epoxy resin dissolved in methyl ethyl ketone (manufactured by Emulsified Cell Company, trade name: Epicoat 1001), imidazole curing agent (manufactured by Chrysanthemum Chemical, trade name: 2E4MZ-CN) 1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kogyo Chemical Co., Ltd., R604), which is a photosensitive monomer, 1.5 parts by weight of polyacrylic monomer (manufactured by Kogyo Chemical Co., Ltd., DPE6A) similarly, a dispersion antifoaming agent (manufactured by Sanko Co., Ltd., trade name: S-65) 0.71 parts by weight of a container is taken, stirred and mixed to adjust the mixture, and 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Ltd.) as a photoinitiator and mihiraketone as a photosensitizer are used for the mixture. Kanto Agent) 0.2 parts by weight was added to obtain a 2.0 Pa · s a solder resist composition (organic resin insulating material) adjusted to a viscosity at 25 ℃.

또, 점도측정은, B형점도계(동경계기사제, DVL-B형)으로 60 rpm 의 경우는 로터 No.4, 6 rpm 의 경우는 로터 No.3 에 의하였다.Viscosity measurement was performed on a rotor type No. 4 at 60 rpm and a rotor No. 3 at 6 rpm using a type B viscometer (DK-L, DVL-B type).

(16) 다음으로, 기판(30)에 상기솔더레지스트조성물을 20 ㎛ 의 두께로 도포하고, 70 ℃ 에서 20분간, 70 ℃ 로 30분간의 조건으로 건조처리를 행한 후, 솔더레지스트레지스트 개구부의 패턴이 그려진 두께 5 mm 의 포토마스크를 솔더레지스트층(70)에 밀착시켜서 1000 mJ/㎠ 의 자외선으로 노광하고, DMTG용액에서 현상처리하고, 랜드경 620 ㎛, 개구경 460 ㎛ 의 개구(71)를 형성한다(도 5(B)참조).(16) Next, the solder resist composition was applied to the substrate 30 with a thickness of 20 μm, and the drying treatment was performed at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, and then the pattern of the solder resist resist openings. The drawn 5 mm thick photomask was brought into close contact with the solder resist layer 70, exposed to ultraviolet light of 1000 mJ / cm 2, developed in DMTG solution, and the opening 71 having a land diameter of 620 µm and an opening diameter of 460 µm. It forms (refer FIG. 5 (B)).

(17) 다음으로, 솔더레지스트층(유기수지절연층)(70)을 형성한 기판을, 염화니켈(2.3×10-1mol/1), 차아인산나트륨(2.8×10-1mol/1), 구연산나트륨(1.6×10-1mol/1)을 포함하는 pH = 4.5 의 무전해니켈도금액에 20분간 침적하고, 개구부(71)에 두께 5 ㎛ 의 니켈도금층(72)를 형성한다. 또, 그 기판을,시안화금칼륨(7.6×10-3mol/1), 염화암모늄(1.9×10-1mol/1),구연산나트륨(1.2×10-1mol/1),차아인산나트륨(1.7×10-1mol/1)을 포함하는 무전해도금액에 80 ℃ 의 조건에서 7.5분간 침적하고, 니켈도금층(72) 상에 두께 0.03 ㎛ 의 금도금층(74)을 형성하는 것으로, 도체회로(158)에 납땜범프(75)를 형성한다(도 5(C)참조).(17) Next, a substrate on which the solder resist layer (organic resin insulating layer) 70 was formed was nickel chloride (2.3 × 10 −1 mol / 1), sodium hypophosphite (2.8 × 10 −1 mol / 1) 20 minutes is immersed in an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 −1 mol / 1), and a nickel plating layer 72 having a thickness of 5 μm is formed at the opening 71. Further, the substrate was prepared using potassium cyanide (7.6 × 10 −3 mol / 1), ammonium chloride (1.9 × 10 −1 mol / 1), sodium citrate (1.2 × 10 −1 mol / 1), sodium hypophosphite ( It was immersed in an electroless solution containing 1.7 × 10 −1 mol / 1) for 7.5 minutes at 80 ° C. to form a gold plated layer 74 having a thickness of 0.03 μm on the nickel plated layer 72. A solder bump 75 is formed at 158 (see Fig. 5C).

(18) 그 후, 솔더레지스트층(70)의 개구부(71)에, 납땜페이스트를 인쇄하고, 200 ℃ 로 리프로하는 것에 의해, BGA(76)을 형성한다. 이에 의해 IC칩(20)을 내장하고, BGA(76)을 가지는 다층프린트배선판(10)을 가지는 것이 가능하다(도 6 참조). BGA의 대신에, PGA(도전성접속핀)을 배설하여도 좋다.(18) After that, the solder paste is printed in the opening 71 of the solder resist layer 70 and leafed at 200 ° C to form the BGA 76. Thereby, it is possible to embed the IC chip 20 and have the multilayer printed circuit board 10 having the BGA 76 (see Fig. 6). Instead of the BGA, a PGA (conductive connecting pin) may be provided.

상술한 실시형태에서는, 층간수지절연층(50, 150)에 열경화형수지시트를 사용하였다. 이 열경화형수지시트는, 난용성수지, 가용성입자, 경화제, 그 외의 성분이 함유되어 있다. 각각에 대하여 이하에 설명한다.In the above-described embodiment, thermosetting resin sheets are used for the interlayer resin insulating layers 50 and 150. This thermosetting resin sheet contains a poorly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.

제 1 실시형태의 열경화형수지시트에 있어서 사용할 수 있는 에폭시계수지는, 산 또는 산화제에 가용성의 입자(이하, 가용성입자라 함)가 산 또는 산화제에 난용성의 수지(이하, 난용성수지라고 함) 중에서 분산한 것이다.The epoxy resin that can be used in the thermosetting resin sheet according to the first embodiment is a resin that is soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) and is poorly soluble in an acid or an oxidizing agent (hereinafter referred to as a poorly soluble resin). ).

또, 제 1 실시형태에서 사용하는 「난용성」「가용성」이라는 말은, 동일의 산 또는 산화제로 이루어지는 용액에 동일시간 침적한 경우에, 상대적으로 용해속도가 빠른 것을 편의상 「가용성」이라고 부르고, 상대적으로 용해속도가 늦은 것을 편의상 「난용성」이라고 부른다.The term " poorly soluble " and " soluble " used in the first embodiment means that the relatively fast dissolution rate is " soluble " for convenience in the case of being immersed in a solution made of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as "solubility" for convenience.

상기 가용성입자로서는, 예를 들면, 산 또는 산화제에 가용성의 수지입자(이하, 가용성수지입자), 산 또는 산화제에 가용성의 무기입자(이하 가용성무기입자), 산 또는 산화제에 가용성의 금속입자(이하 가용성금속입자) 등을 들 수 있다. 이들의 가용성입자는, 단독으로 사용하여도 좋고, 2종 이상 병용하여도 좋다.Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble inorganic particles), and metal particles soluble in an acid or an oxidizing agent (hereinafter Soluble metal particles). These soluble particles may be used alone or in combination of two or more thereof.

상기 가용성입자의 형성은 특별히 제한되지 않고, 구상, 파쇄상 등을 들 수 있다. 또, 상기 가용성입자의 형상은, 일정한 형상인 것이 좋다. 균일한 조도의 요철을 가지는 조화면을 형성하는 것이 가능하기 때문이다.The formation of the soluble particles is not particularly limited, and examples thereof include spherical particles and crushed particles. Moreover, it is good that the shape of the said soluble particle is a fixed shape. This is because it is possible to form a rough surface having unevenness of uniform roughness.

상기 가용성입자의 평균입경으로서는, 0.1 ~ 10 ㎛ 가 바람직하다. 이 입경의 범위라면, 2종류 이상의 다른 입경의 것을 함유하여도 좋다. 즉, 평균입경이 0.1 ~ 5 ㎛ 의 가용성입자와 균일입경이 1 ~ 3 ㎛ 의 가용성입자를 함유하는 등이다. 이로 인해, 보다 복잡한 조화면을 형성하는 것이 가능하고, 도체회로와의 밀착성에도 뛰어나다. 또 제 1 실시형태에 있어서, 가용성입자의 입경이라는 것은, 가용성입자의 가장 긴 부분의 길이이다.As average particle diameter of the said soluble particle, 0.1-10 micrometers is preferable. If it is the range of this particle diameter, you may contain the thing of two or more types of different particle diameters. That is, it contains soluble particles having an average particle diameter of 0.1 to 5 µm and soluble particles having a uniform particle size of 1 to 3 µm. For this reason, it is possible to form a more complicated rough surface, and is excellent also in adhesiveness with a conductor circuit. In the first embodiment, the particle diameter of the soluble particles is the length of the longest portion of the soluble particles.

상기 가용성수지입자로서는, 열경화성수지, 열가소성수지 등으로 이루어지는 것을 들 수 있고, 산 또는 산화제로 이루어지는 용액에 침적한 경우에, 상기 난용성수지보다도 용해속도가 빠르기만 하다면 특별히 한정되지 않는다.Examples of the soluble resin particles include thermosetting resins, thermoplastic resins, and the like, and are not particularly limited as long as their dissolution rate is faster than that of the poorly soluble resin when the solution is immersed in a solution made of an acid or an oxidizing agent.

상기 가용성수지입자의 구체예로서는, 예를 들면, 에폭시수지, 페놀수지, 폴리이미드수지, 폴리페닐렌수지, 폴리오레핀수지, 불소수지 등으로 이루어지는 것을 들 수 있고, 이들의 수지의 한 종류로 이루어지는 것어도 좋으며, 2종류 이상의 수지의 혼합물로 이루어지는 것이어도 좋다.Specific examples of the soluble resin particles include epoxy resins, phenol resins, polyimide resins, polyphenylene resins, polyolefin resins, fluorine resins, and the like. It may be good or it may consist of a mixture of two or more kinds of resins.

또, 상기 가용성수지입자로서는, 고무로 이루어지는 수지입자를 사용하는 것도 가능하다. 상기 고무로서는, 예를 들면, 폴리부타디엔고무, 에폭시변성, 우레탄변성, (메타)아크릴로니트릴변성 등의 각종 변성폴리부타디엔고무, 카르복실기를 함유한 (메타)아크리모니트릴·부타디엔고무 등을 들 수 있다. 이들의 고무를 사용하는 것에 의해, 가용성수지입자가 산 또는 산화제에 용해하기 쉽게 된다. 즉, 산을 사용하여 가용성수지 입자를 용해하는 때에는, 강산 이외의 산에도 용해하는 것이 가능하고, 산화제를 사용하여 가용성수지입자를 용해하는 때에는, 비교적 산화력이 약한 과망간산염으로도 용해하는 것이 가능하다. 또, 크롬산을 사용한 경우에도, 저농도로 용해하는 것이 가능하다. 그 때문에, 산이나 산화제가 수지표면에 잔류하는 일이 없고, 후술하는 바와 같이, 조화면 형성 후, 염화팔라디움 등의 촉매를 부여하는 때에, 촉매가 부여되지 않거나, 촉매가 산화되지 않거나 하는 일이 없다.Moreover, as said soluble resin particle, it is also possible to use the resin particle which consists of rubber | gum. As said rubber, various modified polybutadiene rubbers, such as a polybutadiene rubber, an epoxy modification, a urethane modification, (meth) acrylonitrile modification, the (meth) acrylonitrile butadiene rubber containing a carboxyl group, etc. are mentioned, for example. have. By using these rubbers, soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when dissolving the soluble resin particles using an acid, it is possible to dissolve in an acid other than a strong acid, and when dissolving the soluble resin particles using an oxidizing agent, it is possible to dissolve even with a relatively low oxidizing permanganate. . Moreover, even when chromic acid is used, it can melt | dissolve in low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is added after formation of a roughened surface, no catalyst is provided or the catalyst is not oxidized. none.

상기 가용성무기입자로서는, 예를 들면 알루미늄화합물, 칼슘화합물, 칼륨화합물, 마그네슘화합물 및 규소화합물로 이루어지는 군으로부터 선택되는 적어도 어느 한 종류로 이루어지는 입자 등을 들 수 있다.As said soluble inorganic particle, the particle | grains which consist of at least any one selected from the group which consists of an aluminum compound, a calcium compound, a potassium compound, a magnesium compound, and a silicon compound, etc. are mentioned, for example.

상기 알루미늄화합물로서는, 예를 들면, 알루미나, 수산화알루미늄 등을 들 수 있고, 상기 칼슘화합물로서는, 예를 들면, 탄산칼슘 등을 들 수 있고, 상기 마그네슘화합물로서는, 마그네시아, 도로마이트, 염기성 탄산마그네슘 등을 들 수 있고, 상기 규소화합물로서는, 실리카, 제오라이트 등을 들 수 있다. 이들은 단독으로 사용하여도 좋고, 2종류 이상 병용하여도 좋다.Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate. Examples of the magnesium compound include magnesia, doromite, basic magnesium carbonate, and the like. Examples of the silicon compound include silica and zeolite. These may be used independently and may be used together 2 or more types.

상기 가용성금속입자로서는, 예를 들면, 동, 니켈, 철, 아연, 납, 금, 은,알루미늄, 마그네슘, 칼슘 및 규소로 이루어지는 군으로부터 선택되는 적어도 어느 한 종류로 이루어지는 입자 등을 들 수 있다. 또, 이들이 가용성금속입자는 절연선을 확보하기 위해서, 표층이 수지 등으로 피복되어 있어도 좋다.Examples of the soluble metal particles include particles made of at least one kind selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. In addition, these soluble metal particles may be coated with a resin or the like in order to secure an insulated wire.

상기 가용성입자를, 2종 이상 혼합하여 사용하는 경우, 혼합하는 2종의 가용성입자의 조합으로서는, 수지입자와 무기입자와의 조합이 바람직하다. 양자 모두 도전성이 낮기 때문에 수지필름의 절연성을 확보하는 것이 가능함과 동시에, 난용성수지와의 사이에서 열팽창의 조정을 도모하기 쉽고, 수지필름으로 이루어지는 층간수지절연층에 크랙이 발생하지 않고, 층간수지절연층과 도체회로와의 사이에서 박리가 발생하지 않기 때문이다.In the case where two or more kinds of the soluble particles are mixed and used, as a combination of two kinds of soluble particles to be mixed, a combination of a resin particle and an inorganic particle is preferable. Both of them have low conductivity, which makes it possible to ensure insulation of the resin film and to facilitate thermal expansion adjustment with the poorly soluble resin, without causing cracks in the interlayer resin insulating layer made of the resin film. This is because peeling does not occur between the insulating layer and the conductor circuit.

상기 난용성수지로서는, 층간수지절연층에 산 또는 산화제를 사용하여 조화면을 형성하는 때에, 조화면의 형상을 유지할 수 있는 것이라면 특별히 제한되지 않고, 예를 들면, 열경화성수지, 열가소성수지, 이들의 복합체 등을 들 수 있다. 또, 이들의 수지에 감광성을 부여한 감광성수지도 좋다. 감광성수지를 사용하는 것에 의해, 층간수지절연층에 노광, 현상처리를 사용하여 바이어홀용 개구를 형성하는 것이 가능하다.The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when forming the roughened surface using an acid or an oxidizing agent in the interlayer resin insulating layer. For example, thermosetting resins, thermoplastic resins, and the like Complexes; and the like. Moreover, the photosensitive resin which gave photosensitive property to these resin is also good. By using the photosensitive resin, it is possible to form the via hole opening in the interlayer resin insulating layer by exposure and development.

이들 중에는, 열경화성수지를 함유하고 있는 것이 바람직하다. 그로 인해, 도금액 혹은 각종의 가열처리에 의해서도 조화면의 형상을 유지하는 것이 가능하기 때문이다.Among these, it is preferable to contain a thermosetting resin. Therefore, it is possible to maintain the shape of the roughened surface even by the plating liquid or various heat treatments.

상기 난용성수지의 구체예로서는, 예를 들면, 에폭시수지, 페놀수지, 페노킨수지, 폴리이미드수지, 폴리페닐렌수지, 폴리오레핀수지, 불소수지 등을 들 수 있다. 이들의 수지는 단독으로 사용하여도 좋고, 2종 이상을 병용하여도 좋다. 열경화성수지, 열가소성수지, 그들의 복합체이어도 좋다.Specific examples of the poorly soluble resin include epoxy resins, phenol resins, phenokine resins, polyimide resins, polyphenylene resins, polyolefin resins, fluorine resins, and the like. These resins may be used independently and may use 2 or more types together. A thermosetting resin, a thermoplastic resin, or a composite thereof may be used.

또, 1분자 중에는, 2개 이상의 에폭시기를 가지는 에폭시수지가 보다 바람직하다. 상기의 조화면을 형성하는 것이 가능할 뿐만 아니라, 내열성 등에도 뛰어나기 때문에, 히트사이클 조건 하에 있어서도, 금속층에 응력의 집중이 발생시키지 않고, 금속층의 박리 등이 일어나기 힘들기 때문이다.Moreover, in 1 molecule, the epoxy resin which has two or more epoxy groups is more preferable. This is because it is not only possible to form the roughened surface, but also excellent in heat resistance and the like, and therefore, even under heat cycle conditions, stress concentration does not occur in the metal layer and peeling of the metal layer is difficult to occur.

상기 에폭시수지로서는, 예를 들면, 크레졸노볼락형 에폭시수지, 비스페놀A형 에폭시수지, 비스페놀F형수지, 페놀노볼락형 에폭시수지, 아르킬페놀노볼락형 에폭시수지, 비페놀F형 에폭시수지, 나프탈렌형 에폭시수지, 디시크로펜타디엔형 에폭시수지, 페놀류와 페놀성 수산기를 가지는 방향족 알데히드와의 축합물의 에폭시화물, 트리그리시딜이소시아누레이드, 복환식에폭시수지 등을 들 수 있다. 이들은, 단독으로 사용하여도 좋고, 2종 이상을 병용하여도 좋다. 그로 인해, 내열성 등에 뛰어난 것이 된다.Examples of the epoxy resins include cresol novolac epoxy resins, bisphenol A epoxy resins, bisphenol F resins, phenol novolac epoxy resins, aralkylphenol novolac epoxy resins, and biphenol F epoxy resins. And naphthalene type epoxy resins, dicyclopentadiene type epoxy resins, epoxides of condensates of phenols and aromatic aldehydes having phenolic hydroxyl groups, triglycidyl isocyanuride, and cyclic epoxy resins. These may be used independently and may use 2 or more types together. Therefore, it becomes excellent in heat resistance etc.

제 1 실시형태에서 사용하는 수지필름에 있어서, 상기 가용성입자는, 상기 난용성수지 중에서 거의 균일하게 분산되고 있는 것이 바람직하다. 균일한 조도의 요철을 가지는 조화면을 형성하는 것이 가능하고, 수지필름에 바이어홀이나 스루홀을 형성하여도, 그 위에 형성하는 도체회로의 금속층의 밀착성을 확보하는 것이 가능하기 때문이다. 또, 조화면을 형성하는 표층부만에 가용성입자를 함유하는 수지필름을 사용하여도 좋다. 그로 인해, 수지필름의 표층부 이외는 산 또는 산화제에 산화되는 일이 없기 때문에, 층간수지절연층을 개재한 도체회로 간의 절연성이 확실하게 지켜진다.In the resin film used in the first embodiment, the soluble particles are preferably dispersed almost uniformly in the poorly soluble resin. It is because it is possible to form a roughened surface having unevenness of uniform roughness, and even if a via hole or a through hole is formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Moreover, you may use the resin film containing soluble particle only in the surface layer part which forms rough surface. Therefore, since it does not oxidize to an acid or an oxidizing agent other than the surface layer part of a resin film, the insulation between conductor circuits through an interlayer resin insulation layer is reliably ensured.

상기 수지필름에 있어서, 난용성수지 중에 분산하고 있는 가용성입자의 배합량은, 수지 필름에 대해서, 3 ~ 40 중량% 가 바람직하다. 가용성입자의 배합량이 3 중량% 미만에서는, 소기의 요철을 가지는 조화면을 형성하는 것이 불가능한 경우가 있고, 40 중량% 를 넘으면, 산 또는 산화제를 사용하여 가용성입자를 용해한 때에, 수지필름의 심부까지 용해하여 버리고, 수지필름으로 이루어지는 층간수지절연층을 개재한 도체회로 간의 절연성을 유지할 수 없고, 단락의 원인으로 되는 경우가 있다.In the said resin film, 3-40 weight% of the compounding quantity of the soluble particle disperse | distributing in a poorly soluble resin is preferable with respect to a resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a rough surface having the desired irregularities. If the amount of the soluble particles exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent to the deep portion of the resin film. It may melt | dissolve and cannot maintain insulation between conductor circuits via the interlayer resin insulation layer which consists of resin films, and may cause a short circuit.

상기 수지필름은, 상기 가용성입자, 상기 난용성수지 이외에, 경화제, 그 외의 성분 등을 함유하고 있는 것이 바람직하다.It is preferable that the said resin film contains a hardening | curing agent, other components, etc. other than the said soluble particle and the said poorly soluble resin.

상기 경화제로서는, 예를 들면, 이미다졸계 경화제, 아민계 경화제, 구아딘계 경화제, 이들의 경화제의 에폭시어덕트나 이들의 경화제를 마이크로캅셀화한 것, 트리페닐호스핀, 테트라페놀호스포늄·테트라페놀보레이트 등의 유기포스핀계 화합물 등을 들 수 있다.As said hardening | curing agent, the thing which microcapsulated the imidazole series hardening | curing agent, the amine type hardening | curing agent, the guadin type hardening | curing agent, the epoxy adduct of these hardening | curing agents, and these hardening | curing agents, triphenyl hospin, tetraphenol hosponium, Organic phosphine compounds, such as tetraphenol borate, etc. are mentioned.

상기 경화제의 함유량은, 수지필름에 대하여 0.05 ~ 10 중량% 인 것이 바람직하다. 0.05 중량% 미만에서는, 수지필름의 경화가 불충분하기 때문에, 산 또는 산화제가 수지필름에 침입하는 정도가 커지고, 수지필름의 절연성이 손상되는 일이 있다. 한편, 10 중량% 를 넘으면, 과잉한 경화제 성분이 수지의 조성을 변성시키는 일이 있고, 신뢰성의 저하를 초래해버리는 일이 있다.It is preferable that content of the said hardening | curing agent is 0.05 to 10 weight% with respect to a resin film. If it is less than 0.05 weight%, since hardening of a resin film is inadequate, the grade which an acid or an oxidant penetrates into a resin film becomes large, and the insulation of a resin film may be impaired. On the other hand, when it exceeds 10 weight%, the excessive hardening | curing agent component may modify the composition of resin, and may cause the fall of reliability.

상기 그 외의 성분으로서는, 예를 들면, 조화면의 성분에 영향을 주지 않는무기화합물 혹은 수지 등의 필러를 들 수 있다. 상기 무기화합물로서는, 예를 들면, 실리카, 알루미나, 도로마이트 등을 들 수 있고, 상기 수지로서는, 예를 들면, 폴리이미드수지, 폴리아크릴수지, 폴리아미드이미드수지, 폴리페닐렌수지, 멜라닌수지, 오레핀계 수지 등을 들 수 있다. 이들의 필러를 함유시키는 것에 의해, 열팽창계수의 정합이나 내열성, 내약품성의 향상 등을 도모하고 다층프린트배선판의 성능을 향상시키는 일이 가능하다.As said other components, fillers, such as an inorganic compound or resin which do not affect the component of a roughening surface, are mentioned, for example. Examples of the inorganic compound include silica, alumina, and doromite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, Orefin-type resin etc. are mentioned. By including these fillers, the thermal expansion coefficient can be matched, the heat resistance, the chemical resistance can be improved, and the performance of the multilayer printed circuit board can be improved.

또, 상기 수지필름은, 용제를 함유하고 있어도 좋다. 상기 용제로서는, 예를 들면, 아세톤, 메틸에틸케톤, 시크로헥사논 등의 케톤류, 초산에틸, 초산부틸, 세로솔부아세테이트나 토루엔, 키시렌 등의 방향족 탄화수소 등을 들 수 있고, 이들은 단독으로 사용하여도 좋고, 2종 이상 병용하여도 좋다. 단, 이들의 층간수지절연층은, 350 ℃ 이상의 온도를 가하면 용해, 탄화를 하여 버린다.Moreover, the said resin film may contain the solvent. As said solvent, ketones, such as acetone, methyl ethyl ketone, a cyclohexanone, ethyl acetate, butyl acetate, aromatic hydrocarbons, such as a cersol butylacetate, toluene, and xylene, etc. are mentioned, for example, These are independently You may use and may use 2 or more types together. However, these interlayer resin insulating layers are melted and carbonized when a temperature of 350 ° C or higher is applied.

상기 수지필름을 늘여붙인 후, 레이저로 개구시키고, 층간수지절연층에 바이어홀을 개구시킨다. 그 후, 산 혹은 산화제를 침적시키고, 층간수지절연층에 조화층을 형성한다. 산으로서는, 유산, 인산, 염산, 의산 등의 강산을 사용할 수 있고, 산화제로서는, 산화제로서는 크롬산, 크롬유산, 과망간염산 등을 사용하는 것이 가능하다. 그로 인해, 가용성입자를 용해 혹은 탈락시키는 것에 의해 층간수지절연층의 표면에 조화층을 형성시킨다. 그 조화층이 형성된 층간수지절연층에, Pb 등의 촉매를 부여한 후, 무전해도금을 시술한다. 무전해도금막 상에 레지스트를 시공하고 노광, 현상을 거쳐 도금레지스트의 비형성부를 형성시킨다. 해 비형성부에 전해도금을 시공하고 레지스트를 박리, 에칭에 의해 층간수지절연층 상의 무전해도금막을 제거하고 바이어홀을 도체회로를 형성시켰다.After the resin film is stretched, the laser film is opened, and a via hole is opened in the interlayer resin insulating layer. Thereafter, an acid or an oxidant is deposited to form a roughened layer on the interlayer resin insulating layer. As an acid, strong acids, such as lactic acid, phosphoric acid, hydrochloric acid, and acid, can be used, and as an oxidizing agent, it is possible to use chromic acid, chromium lactic acid, permanganic acid, etc. as an oxidizing agent. Therefore, the roughening layer is formed on the surface of the interlayer resin insulating layer by dissolving or dropping the soluble particles. After applying a catalyst such as Pb to the interlayer resin insulating layer on which the roughened layer is formed, electroless plating is performed. A resist is formed on the electroless plating film, and the non-forming portion of the plating resist is formed through exposure and development. Electroplating was applied to the non-forming portion, and the resist was peeled off and etched to remove the electroless plating film on the interlayer resin insulating layer and to form a via hole in the conductor circuit.

도 8(A)는, 제 1 실시형태에 관계하는 다층프린트배선판(10)의 사시도이고, 도 8(B)는, 상기 다층프린트배선판(10)의 일부를 확대하여 도시하는 설명도이다. 제 1 실시형태의 다층프린트배선판(10)의 표면에는, 격자상의 형상으로 납땜범프(볼그리드어레이)(76)가 기판 전면에 배설되고 있다. 제 1 실시형태에서는, IC칩(20) 상에도 BGA(76)를 형성하는 것으로, IC칩(20)으로부터의 배선 길이를 단축하는 것이 가능하다.FIG. 8A is a perspective view of the multilayer printed circuit board 10 according to the first embodiment, and FIG. 8B is an explanatory view showing an enlarged portion of the multilayer printed circuit board 10. On the surface of the multilayer printed circuit board 10 of the first embodiment, solder bumps (ball grid arrays) 76 are disposed on the entire surface of the substrate in a lattice shape. In the first embodiment, the BGA 76 is also formed on the IC chip 20, so that the wiring length from the IC chip 20 can be shortened.

〔제 1 실시형태의 제 1 변형예〕[First Modification of First Embodiment]

도 9(A)는, 제 1 실시형태의 제 1 변형예에 관계하는 다층프린트배선판(10)의 사시도이며, 도 9(B)는, 상기 다층프린트배선판(10)의 일부를 확대하여 도시하는 설명도이다. 변형예의 다층프린트배선판(10)의 표면에는, 격자상의 형상으로 납땜(볼그리드어레이)(76)가 IC칩(20) 상을 제외하고 네 구석에 배설되고 있다. 이 변형예에는, IC칩(20) 상을 피하는 것으로, IC칩으로부터의 열적, 전자적 영향을 BGA(76)가 받기 어려운 잇점이 있다.FIG. 9A is a perspective view of a multilayer printed circuit board 10 according to the first modification of the first embodiment, and FIG. 9B is an enlarged view of a part of the multilayer printed circuit board 10. It is explanatory drawing. On the surface of the multilayer printed circuit board 10 of the modification, solder (ball grid array) 76 is disposed in four corners except for the IC chip 20 in a lattice shape. This modification has the advantage that the BGA 76 is less likely to receive thermal and electronic effects from the IC chip by avoiding the IC chip 20.

〔제 1 실시형태의 제 2 변형예〕[2nd modification of 1st Embodiment]

이어서, 제 1 실시형태의 제 2 변형예에 관계하는 다층프린트배선판에 대하여, 도 10을 참조하여 설명한다. 상술한 제 1 실시형태에선, BGA를 배설한 경우로 설명하였다. 제 2 변형예에서는, 제 1 실시형태와 거의 같지만, 도 10에서 도시하는 바와 같이, 도전성접속핀(96)을 개재하여 접속을 취하는 PGA방식으로 구성되고 있다.Next, a multilayer printed circuit board according to a second modification of the first embodiment will be described with reference to FIG. 10. In 1st Embodiment mentioned above, it demonstrated as the case where BGA was excreted. In the second modification, it is almost the same as in the first embodiment, but as shown in FIG. 10, the PGA system is configured to connect via the conductive connecting pin 96.

〔제 1 실시형태의 제 3 변형예〕[Third Modified Example of First Embodiment]

다음으로, 제 1 실시형태의 제 3 변형예에 관계하는 다층프린트배선판에 대하여 도 11을 참조하여 설명한다.Next, a multilayer printed circuit board according to a third modification of the first embodiment will be described with reference to FIG.

상술한 제 1 실시형태에서는, 코어기판(30)에 스폿페이싱으로 설치한 요부(32)에 IC칩을 수용하였다. 이에 대하여, 제 3변형예에서는, 코어기판(30)에 형성한 통공(32)에 IC칩(20)을 수용하고 있다. 이 제 3 변형예에서는, IC칩(20)의 이면 측에 히트싱크를 직접 취부시키는 일이 가능하기 때문에, IC칩(20)을 효과적으로 냉각할 수 있는 잇점이 있다.In the first embodiment described above, the IC chip is accommodated in the recess 32 provided by the spot facing on the core substrate 30. In the third modification, on the other hand, the IC chip 20 is accommodated in the through hole 32 formed in the core substrate 30. In this third modification, since the heat sink can be directly attached to the rear surface side of the IC chip 20, there is an advantage that the IC chip 20 can be cooled effectively.

〔제 1 실시형태의 제 4 변형예〕[Fourth modification of the first embodiment]

다음으로, 제 1 실시형태의 제 4 변형예에 관계하는 다층프린트배선판에 대하여 도 12를 참조하여 설명한다.Next, a multilayer printed circuit board according to a fourth modification of the first embodiment will be described with reference to FIG. 12.

상술한 제 1 실시형태에서는, 다층프린트배선판 내에 IC칩을 수용하였다. 이에 대하여, 제 4 변형예에서는, 다층프린트배선판 내에 IC칩(20)을 수용함과 동시에, 표면에 IC칩(120)을 재치하고 있다. 내장한 IC칩(20)으로서는, 발열량이 비교적 작은 캐쉬메모리가 사용되고, 표면의 IC칩(120)으로서는, 연산용의 CPU가 재치되고 있다.In the first embodiment described above, the IC chip is housed in the multilayer printed circuit board. In contrast, in the fourth modification, the IC chip 20 is accommodated in the multilayer printed circuit board and the IC chip 120 is placed on the surface. As the built-in IC chip 20, a cache memory having a relatively low heat generation is used, and as the IC chip 120 on the surface, a CPU for calculation is placed.

IC칩(20)의 다이패드(24)와, IC칩(120)의 다이패드(124)는, 트랜지션층(38)-바이어홀(60)-도체회로(58)-바이어홀(160)-도체회로(158)-BGA(76)(U)를 개재하여 접속되고 있다. 한편, IC칩(120)의 다이패드(124)와, 도터보드(90)의 패드(92)는, BGA(76U)-도체회로(158)-바이어홀(160)-도체회로(58)-바이어홀(60)-스루홀(136)-바이어홀(60)-도체회로(58)-바이어홀(160)-도체회로(158)-BGA(76U)를 개재하여 접속되고 있다.The die pad 24 of the IC chip 20 and the die pad 124 of the IC chip 120 include the transition layer 38-the via hole 60-the conductor circuit 58-the via hole 160- The conductor circuit 158 is connected via the BGA 76 (U). On the other hand, the die pad 124 of the IC chip 120 and the pad 92 of the daughter board 90 are composed of BGA 76U, conductor circuit 158, via hole 160, conductor circuit 58, and the like. The via hole 60, the through hole 136, the via hole 60, the conductor circuit 58, the via hole 160, the conductor circuit 158, and the BGA 76U are connected to each other.

제 4 변형예에서는, 저소비형의 캐쉬메모리(20)를 CPU용의 IC칩(120)과 별도로 제조하면서, IC칩(120)과 캐쉬메모리(20)를 근접하여 재치하는 것이 가능하게 되고, IC칩의 고속동작이 가능하게 된다. 이 제 4 변형예에서는 IC칩을 내장함과 동시에 표면에 재치하는 것으로, 각각의 기능이 다른 IC칩 등의 전자부품을 실장시키는 것이 가능하고, 보다 고기능인 다층프린트배선판을 얻는 것이 가능하다.In the fourth modification, the IC chip 120 and the cache memory 20 can be placed in close proximity while the low-use cache memory 20 is manufactured separately from the IC chip 120 for the CPU. High-speed operation is possible. In this fourth modification, by mounting the IC chip and placing it on the surface, it is possible to mount electronic components such as IC chips having different functions, and to obtain a higher-performance multilayer printed circuit board.

제 1 실시형태의 구조에 의해, 리드부품을 개재하지 않고, IC칩과 프린트배선판과의 접속을 취하는 것이 가능하다. 그 때문에, 수지봉지도 불필요하게 된다. 또, 리드부품이나 봉지수지에 기인하는 부정합이 일어나지 않기 때문에, 접속성이나 신뢰성이 향상한다. 또, IC칩의 다이패드와 프린트배선판의 도전층이 직접 접속되어 있기 때문에, 전기특성도 향상시키는 것이 가능하다.With the structure of the first embodiment, it is possible to make the connection between the IC chip and the printed wiring board without interposing the lead parts. Therefore, resin encapsulation is also unnecessary. In addition, since no mismatch caused by the lead component or the sealing resin occurs, the connectivity and the reliability are improved. In addition, since the die pad of the IC chip and the conductive layer of the printed wiring board are directly connected, the electrical characteristics can also be improved.

또, 종래의 IC칩의 실장방법과 비교하여, IC칩~기판~외부기판까지의 배선길이도 짧게 할 수 있고, 루프인덕턴스를 저감할 수 있는 효과도 있다.In addition, compared with the conventional IC chip mounting method, the wiring length from the IC chip to the external board can be shortened, and the loop inductance can be reduced.

〔제 2 실시형태〕[2nd Embodiment]

이어서, 본 발명의 제 2 실시형태에 관계하는 다층프린트배선판의 구성에 대하여, 다층프린트배선판(210)의 단면을 도시하는 도 18을 참조하여 설명한다.Next, the structure of the multilayer printed circuit board according to the second embodiment of the present invention will be described with reference to FIG. 18 showing a cross section of the multilayer printed circuit board 210.

도 18에 도시하는 바와 같이 다층프린트배선판(210)은, IC칩(220)을 수용하는 코어기판(230)과, 층간수지절연층(250), 층간수지절연층(350)으로 이루어진다. 층간수지절연층(250)에는, 바이어홀(260) 및 도체회로(258)이 형성되고, 층간수지절연층(350)에는, 바이어홀(360) 및 도체회로(358)이 형성되고 있다.As shown in FIG. 18, the multilayer printed circuit board 210 includes a core substrate 230 accommodating the IC chip 220, an interlayer resin insulating layer 250, and an interlayer resin insulating layer 350. The via hole 260 and the conductor circuit 258 are formed in the interlayer resin insulating layer 250, and the via hole 360 and the conductor circuit 358 are formed in the interlayer resin insulating layer 350.

IC칩(220)에는, 패시베이션막(224)이 피복되고, 상기 패시베인션막(224)의 개구 내에 입출력단자를 구성하는 다이패드(224), 및, 위치결정마크(223)가 배설되고 있다. 패드(224)의 상에는, 주로 동으로 이루어지는 트랜지션층(238)이 형성되고 있다.The passivation film 224 is covered with the IC chip 220, and a die pad 224 constituting an input / output terminal in the opening of the passivation film 224 and a positioning mark 223 are disposed. On the pad 224, a transition layer 238 mainly made of copper is formed.

층간수지절연층(350) 상에는, 솔더레지스트층(270)이 배설되고 있다. 솔더레지스트층(270)의 개구부(271) 하의 도체회로(358)에는, 도시하지 않은 도터보드, 마더보드 등의 외부기판과 접속하기 위한 BGA(276)가 설치되어 있다.On the interlayer resin insulating layer 350, a solder resist layer 270 is disposed. The conductor circuit 358 under the opening 271 of the solder resist layer 270 is provided with a BGA 276 for connecting to an external substrate such as a daughter board, a motherboard, and the like which is not shown.

제 2 실시형태의 다층프린트배선판(210)에서는, 코어기판(230)에 IC칩(220)을 미리 내장시켜, 상기 IC칩(220)의 패드(224)에는 트랜지션층(238)을 배설시키고 있다. 이 때문에, 리드부품이나 봉지수지를 사용하지 않고, IC칩과 다층프린트배선판(패키지기판)과의 전기적 접속을 취하는 것이 가능하다.In the multilayer printed circuit board 210 of the second embodiment, the IC chip 220 is embedded in the core substrate 230 in advance, and the transition layer 238 is disposed on the pad 224 of the IC chip 220. . For this reason, it is possible to make electrical connection with an IC chip and a multilayer printed wiring board (package substrate), without using a lead component or sealing resin.

또, 다이패드(224) 상에 동제의 트랜지션층(238)을 설치하는 것으로 패드(224) 상의 수지잔류를 방지하는 것이 가능하고, 또, 후공정 시에 산이나 산화제 혹은 에칭액에 침적시키거나, 가종 아닐공정을 거쳐도 패드(224)의 변색, 용해도 발생하지 않는다.Further, by providing a copper transition layer 238 on the die pad 224, it is possible to prevent resin residue on the pad 224, and to deposit it in an acid, an oxidizing agent, or an etchant during a later step, The discoloration and dissolution of the pad 224 does not occur even through an annealing process.

또, 후술하는 제조공정에 있어서, ICC칩(220)의 위치결정마크(223)를 기준으로 코어기판(230)에 위치결정마크(231)를 형성하고, 상기 위치결정마크(231)에 맞추어 바이어홀(260)을 형성한다. 이 때문에, IC칩(220)의 패드(224) 상에 바이어홀(260)을 정확하게 위치맞춤하게 되어, 패드(224)와 바이어홀(260)을 확실하게 접속시키는 것이 가능하다.In the manufacturing process to be described later, the positioning mark 231 is formed on the core substrate 230 based on the positioning mark 223 of the ICC chip 220, and the buyer is aligned with the positioning mark 231. The hole 260 is formed. For this reason, the via hole 260 can be correctly positioned on the pad 224 of the IC chip 220, and the pad 224 and the via hole 260 can be reliably connected.

이어서, 도 18을 참조하여 상술한 다층프린트배선판의 제조방법에 대하여, 도 13 ~ 도 17을 참조하여 설명한다.Next, the manufacturing method of the multilayer printed wiring board described above with reference to FIG. 18 will be described with reference to FIGS. 13 to 17.

(1) 우선, 글래스크로스 등의 심재에 에폭시 등의 수지를 함침시킨 프리프레그를 적층한 절연수지기판(코어기판)(230)을 출발재료로 한다(도 13(A)참조). 다음으로, 코어기판(230)의 한쪽 면에, 스폿페이싱가공으로 IC칩수용용의 요부(232)를 형성한다(도 13(B)참조).(1) First, an insulating resin substrate (core substrate) 230 in which a prepreg obtained by impregnating a resin such as epoxy in a core material such as glass cross is laminated is used as a starting material (see Fig. 13 (A)). Next, a recess 232 for accommodating the IC chip is formed on one surface of the core substrate 230 by spot facing processing (see Fig. 13 (B)).

(2) 그 후, 요부(232)에, 인쇄기를 사용하여 접착재료(234)를 도포한다. 이 때, 도포 이외에도, 폿팅 등을 하여도 좋다. 다음으로, IC칩(220)을 접착재료(234) 상에 재치한다(도 13(C)참조).(2) Then, the adhesive material 234 is apply | coated to the recessed part 232 using the printing machine. At this time, potting or the like may be performed in addition to the coating. Next, the IC chip 220 is placed on the adhesive material 234 (see Fig. 13C).

(3) 그리고, IC칩(220)의 상면을 누르거나 혹은 두드려 요부(232) 내에 완전하게 수용시킨다(도 13(D)참조). 도 13(D) 중에 도시하는 IC칩(220) 및 코어기판(230)의 평면도를 도 19(A)에 도시한다. 코어기판(230)의 요부(232)에 수용된 IC칩(220)은, 요부의 가공정도를 위하여, 또, 접착재료(234)를 개재시키기 위해, 정확하게 코어기판에 대하여 위치결정이 되어 있지 않다.(3) Then, the upper surface of the IC chip 220 is pressed or knocked to be completely accommodated in the recess 232 (see FIG. 13 (D)). 19A is a plan view of the IC chip 220 and the core substrate 230 shown in FIG. 13D. The IC chip 220 accommodated in the recessed portion 232 of the core substrate 230 is not correctly positioned with respect to the core substrate in order to process the recessed portion and to interpose the adhesive material 234.

(4) IC칩(220)의 네 모서리에 배설된 위치결정마크(223)을 카메라(280)로 촬영하고, 이 위치결정마크(223)을 기준으로, 코어기판(230)의 네 모서리에서 레이저로 위치결정마크용 요부(231a)를 천공설치한다(도 13(E)). 도 13(E) 중에서 도시하는 IC칩(220) 및 코어기판(230)의 평면도를 도 19(B)에 도시한다.(4) The positioning mark 223 disposed at the four corners of the IC chip 220 is photographed by the camera 280, and the laser is positioned at the four corners of the core substrate 230 based on the positioning mark 223. The recessed portion 231a for the positioning mark is drilled and installed (Fig. 13 (E)). A plan view of the IC chip 220 and the core substrate 230 shown in Fig. 13E is shown in Fig. 19B.

(5) 그 후, IC칩(220)을 수용시킨 코어기판(230)의 전면에 증착, 스패터링등의 물리적 증착을 행하고, 전면에 도전성의 금속막(233)을 형성시킨다(도 14(A)). 그 금속으로서는, 주석, 크롬, 티탄, 니켈, 아연, 코발트, 금, 동 등의 금속을 1종 이상으로 형성시킨다. 경우에 따라서는, 다른 금속을 2층 이상으로 형성시켜도 좋다. 두께로서는, 0.001 ~2.0 ㎛ 가 바람직하다. 특히, 0.01 ~1.0 ㎛ 가 바람직하다.(5) After that, physical deposition such as vapor deposition and sputtering is performed on the entire surface of the core substrate 230 in which the IC chip 220 is accommodated, and a conductive metal film 233 is formed on the entire surface (FIG. 14A). )). As this metal, metals, such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper, are formed in 1 or more types. In some cases, two or more different metals may be formed. As thickness, 0.001-2.0 micrometers is preferable. In particular, 0.01-1.0 micrometer is preferable.

금속막(233) 상에, 또 무전해도금, 전해도금, 또는 그들의 복합도금에 의해, 도금막(236)을 형성시켜도 좋다(도 14(B)). 형성되는 도금의 종류로서는 동, 니켈, 금, 은, 아연, 철 등이 있다. 전기특성, 경제성, 또, 후공정에서 형성되는 빌드업인 도체층이 주로 동이라는 점에서, 동을 사용하면 좋다. 그 두께는 0.01 ~ 5.0 ㎛ 의 범위에서 행하는 것이 좋다. 0.01 ㎛ 미만에서는, 전면에 도금막을 형성할 수 없고, 5.0 ㎛ 을 넘으면 에칭으로 제거하기 힘들어지거나, 위치결정마크가 묻혀버리고, 인식할 수 없다. 바람직한 범위는, 0.1 ~ 3.0 ㎛ 이다. 스패터, 증착으로 형성하는 것도 가능하다.On the metal film 233, the plating film 236 may be formed by electroless plating, electroplating, or their composite plating (Fig. 14 (B)). Types of plating to be formed include copper, nickel, gold, silver, zinc, iron and the like. Electrical properties, economics, and the conductor layer which is a buildup formed in a later step are mainly copper, so copper may be used. It is preferable to perform the thickness in the range of 0.01-5.0 micrometers. If it is less than 0.01 micrometer, a plating film cannot be formed in the whole surface, and when it exceeds 5.0 micrometers, it will become difficult to remove by etching, or a positioning mark will be buried and it cannot be recognized. The preferable range is 0.1-3.0 micrometers. It is also possible to form by spatter and vapor deposition.

(6) 그 후, 레지스트(235α)를 실시하고, 패드(224)에 대응하는 패턴(239α) 및 위치결정마크(239b)가 그려진 마스크(239)를 재치한다(도 14(C)). 이 마스크(235)의 위치결정은, 링 형상으로 그려진 위치결정마크(239b) 내에, 코어기판(230) 측의 위치결정마크용 통공(231a)이 들어가도록, 상방으로부터 빛을 주고, 카메라(289)에 의해 위치결정마크(231)으로부터의 반사광을 촬상하면서 행한다. 제 2 실시형태에서는, 위치결정마크(231) 위도 동도금막(236)이 형성되고 있기 때문에, 반사광이 레지스트(235α)를 투과하기 쉽고, 가판과 마스크의 위치맞춤을 용이하게 할 수 있다.(6) Then, a resist 235α is applied, and the mask 239 on which the pattern 239α and the positioning mark 239b corresponding to the pad 224 are drawn is placed (FIG. 14C). The positioning of the mask 235 gives light from above so that the positioning mark through hole 231a on the core substrate 230 side enters the positioning mark 239b drawn in a ring shape, and the camera 289 is positioned. Is performed while imaging the reflected light from the positioning mark 231. In the second embodiment, since the copper plating film 236 on the positioning mark 231 is formed, the reflected light can easily pass through the resist 235α, and the alignment of the substrate and the mask can be facilitated.

(7) 노광, 형상하여 IC칩의 패드(224)의 상부에 개구를 설치하도록 도금레지스트(235)를 형성하고, 전해도금를 실시하여 전해도금막(237)을 설치한다(도 14(D)). 도금레지스트(235)를 제거한 후, 도금레지스트(235) 하의 무전해도금막(236), 금속막(233)을 제거하는 것으로, IC칩의 패드(224) 상에 트랜지션층(238)을, 또, 요부(231a)에 위치결정마크(231)를 형성한다(도 14(E)).(7) A plating resist 235 is formed so as to expose and form an opening in the upper portion of the pad 224 of the IC chip, and electrolytic plating is performed to provide an electroplating film 237 (Fig. 14 (D)). . After removing the plating resist 235, the electroless plating film 236 and the metal film 233 under the plating resist 235 are removed to form the transition layer 238 on the pad 224 of the IC chip. The positioning mark 231 is formed in the recessed part 231a (FIG. 14 (E)).

(8) 다음으로, 기판에 에칭액을 스프레이로 뿌리고, 트랜지션층(238)의 표면을 에칭하는 것에 의해 조화면(238α)을 형성한다(도 15(A)참조). 무전해도금이나 산화환원처리를 사용하여 조화면을 형성하는 것도 가능하다.(8) Next, an etching solution is sprayed onto the substrate, and the rough surface 238 alpha is formed by etching the surface of the transition layer 238 (see Fig. 15 (A)). It is also possible to form a roughened surface using electroless plating or redox treatment.

(9) 상기 공정을 거친 기판에, 제 1 실시형태와 같은 열경화수지시트를 진공압착 라미네이트하고, 층간수지절연층(250)을 설치한다(도 15(B)참조).(9) A thermosetting resin sheet as in the first embodiment is vacuum-pressed laminated to the substrate subjected to the above step, and an interlayer resin insulating layer 250 is provided (see Fig. 15B).

(10) 다음으로, 층간수지절연층(250)을 통과시키고 카메라(280)에 의해 위치결정마크(231)를 촬상하는 것으로 위치결정을 행하고, 파장 10.4 ㎛ 의 CO2가스레이저로, 빔경 5mm, 펄스폭 5.0 마이크로 초, 마스크의 혈경 0.5 mm, 1쇼트의 조건으로, 층간수지절연층(250)에 직경 80 ㎛ 의 바이어홀 개구(248)를 설치한다(도 15(C)참조).(10) Next, positioning is performed by passing the interlayer resin insulating layer 250 and imaging the positioning mark 231 by the camera 280, and using a CO 2 gas laser having a wavelength of 10.4 µm, a beam diameter of 5 mm, A via hole opening 248 having a diameter of 80 µm is provided in the interlayer resin insulating layer 250 under the condition of a pulse width of 5.0 microseconds, a mask diameter of 0.5 mm, and one shot (see Fig. 15C).

(11) 다음으로, 층간수지절연층(250)의 표면을 조화하고, 조화면(250α)을 형성한다(도 15(E)참조).(11) Next, the surface of the interlayer resin insulating layer 250 is roughened to form a rough surface 250α (see Fig. 15E).

(12) 다음으로, 금속막(252)을 층간수지절연층(250)의 표면에 형성한다(도16(A)참조).(12) Next, a metal film 252 is formed on the surface of the interlayer resin insulating layer 250 (see Fig. 16A).

(13) 상기 처리를 끝낸 기판(230)에, 시판의 감광성 드라이필름(254α)을 붙이고, 패드에 대응하는 패턴(253b)이 그려진 포토마스크필름(253)을 재치한다. 포토마스필름(253) 재치 전의 코어기판(230)의 평면도를 도 20(A)에, 포토마스크필름(253)을 재치한 상태를 도 20(B)에 도시한다. 이 마스크(253)의 의치결정은, 링형상으로 그려진 위치결정마크(253b)에 코어기판(230) 측의 위치결정마크(231)가 들어가도록, 상방으로부터 빛을 주어, 카메라(289)에 의해 위치결정마크(231)으로부터의 반사광을 촬영하면서 행한다. 제 2 실시형태에서는, 위치결정마크(231) 상에 도금막(237)이 형성되고 있기 때문에, 반사광이 층간수지절연층(250) 및 필름(254α)을 통과하기 쉽고, 위치결정을 정확히 행할 수 있다. 또, 상술한 바와 같이 위치결정마크(231)를 구성하는 동도금막(237)에 대하여 조화처리를 실시하였지만, 표면의 반사율을 높이기 때문에, 이 조화처리를 행하지 않는 일도, 혹은, 조화처리를 행한 후, 약액, 레이저 등으로 표면의 평활화처리를 행하는 것도 가능하다.(13) A commercially available photosensitive dry film 254α is attached to the substrate 230 after the above processing, and the photomask film 253 on which the pattern 253b corresponding to the pad is drawn is placed. 20A shows a plan view of the core substrate 230 before the photomask film 253 is placed, and FIG. 20B shows the state where the photomask film 253 is placed. The denture determination of the mask 253 is made by the camera 289 by giving light from above so that the positioning mark 253 on the core substrate 230 side enters the positioning mark 253b drawn in a ring shape. This is performed while photographing the reflected light from the positioning mark 231. In the second embodiment, since the plating film 237 is formed on the positioning mark 231, the reflected light easily passes through the interlayer resin insulating layer 250 and the film 254α, and positioning can be performed accurately. have. In addition, although the roughening process was performed with respect to the copper plating film 237 which comprises the positioning mark 231 as mentioned above, since the reflectance of a surface is raised, this roughening process may not be performed or after roughening process is performed. It is also possible to perform the surface smoothing treatment with a chemical liquid, a laser or the like.

(14), 그 후, 100 mJ/㎠ 로 노광하고나서, 0.8 % 탄산나트륨으로 현상처리하고, 두께 15 ㎛ 의 도금레지스트(254)를 설치한다(도 16(C)).(14) Then, after exposing at 100 mJ / cm <2>, it develops with 0.8% sodium carbonate and installs the plating resist 254 of thickness 15micrometer (FIG. 16 (C)).

(15) 다음으로, 제 1 실시형태와 같은 조건으로 전해도금을 실시하고, 두께 15 ㎛ 의 전해도금막(256)을 형성한다(도 16(D)참조).(15) Next, electroplating is carried out under the same conditions as in the first embodiment, and an electroplated film 256 having a thickness of 15 µm is formed (see FIG. 16 (D)).

(16) 도금레지스트(254)를 5% NaOH 로 박리제거한 후, 그 도금레지스트 하의 금속층(252)을 에칭으로 용해제거하고, 금속층(252)과 용해도금막(256)으로 이루어지는 두께 16 ㎛ 의 도체회로(258) 및 바이어홀(260)을 형성하고, 에칭액에 의해, 조화면(258α,260α)을 형성한다(도 17(A)참조).(16) After the plating resist 254 is peeled off with 5% NaOH, the metal layer 252 under the plating resist is removed by etching, and a conductive circuit having a thickness of 16 µm consisting of the metal layer 252 and the soluble plating film 256 is obtained. 258 and the via hole 260 are formed, and roughened surfaces 258α and 260α are formed by the etching solution (see Fig. 17A).

(17) 이어서, 상기 (6) ~ (12)의 공정을, 반복하는 것에 의해, 또 상층의 층간수지절연층(350) 및 도체회로(358)(바이어홀(360)을 포함함)을 형성한다(도 17(B)참조).(17) Subsequently, the steps (6) to (12) are repeated to form an interlayer resin insulating layer 350 and a conductor circuit 358 (including the via hole 360) in the upper layer. (See FIG. 17 (B)).

(18)다음으로, 기판(230)에, 제 1 실시형태와 같은 솔더레지스트조성물을 20 ㎛ 의 두께로 도포하고, 건조처리를 행한 후, 포토마스크를 솔더레지스트층(270)에 필착시키고 노광하고, DMTG 용액으로 현상처리, 200 ㎛ 의 직경의 개구(271)를 형성한다(도 17(C)참조).(18) Next, the same solder resist composition as that of the first embodiment was applied to the substrate 230 to a thickness of 20 占 퐉, and after drying, the photomask was deposited on the solder resist layer 270 and exposed to light. And developing with DMTG solution to form an opening 271 of a diameter of 200 mu m (see Fig. 17 (C)).

(19) 다음으로, 솔더레지스트층(유기수지절연층(270))을 형성한 기판을 무전해니켈도금액에 침적하고, 개구부(271)에 두께 5 ㎛ 의 니켈도금층(272)을 형성한다. 또, 그 기판을, 무전해도금액에 침적하고, 니켈도금층(272) 상에 두께 0.03 ㎛ 의 금도금층(274)을 형성하는 것으로, 도체회로(358)에 납땜범프(275)를 형성한다(도 17(D)참조).(19) Next, the substrate on which the solder resist layer (organic resin insulating layer 270) is formed is deposited in an electroless nickel plating solution, and a nickel plating layer 272 having a thickness of 5 탆 is formed in the opening 271. Further, the substrate is dipped in an electroless plating solution to form a gold plated layer 274 having a thickness of 0.03 μm on the nickel plated layer 272, thereby forming a solder bump 275 in the conductor circuit 358 (Fig. 17 (D)).

(20) 그 후, 솔더레지스트(270)의 개구부(271)에, 납땜페이스트를 인쇄하고, 200 ℃ 로 리프로하는 것에 의해, BGA(276)를 형성한다. 이로 인해, IC칩(220)을 내장하고, BGA(276)를 가지는 다층프린트배선판(210)을 얻는 일이 가능하다(도 18 참조). BGA의 대신에 PGA(도전성접속핀)를 배설하여도 좋다.(20) After that, a solder paste is printed in the opening 271 of the solder resist 270 and leafed at 200 ° C to form the BGA 276. For this reason, it is possible to obtain the multilayered printed circuit board 210 incorporating the IC chip 220 and having the BGA 276 (see Fig. 18). Instead of the BGA, a PGA (conductive connecting pin) may be provided.

〔제 2 실시형태의 제 1 변형예〕[First Modified Example of Second Embodiment]

이어서, 본 발명의 제 2 실시형태의 제 1 변형예에 관계하는 다층프린트배선판에 대하여, 도 21을 참조하여 설명한다.Next, a multilayer printed circuit board according to a first modification of the second embodiment of the present invention will be described with reference to FIG. 21.

상술한 제 2 실시형태에서는, 다층프린트배선판 내에 IC칩을 수용하였다. 이에 대하여, 제 2 실시형태의 제 1 변형예에서는, 다층프린트배선판 내에서 IC칩(220)을 수용함과 동시에, 표면에 IC칩(320)을 재치하고 있다. 내장되는 IC칩(220)으로서는, 발열량이 비교적 작은 캐쉬메모리가 사용되고, 표층의 IC칩(320)으로서는, 연산용 CPU가 재치되고 있다.In the second embodiment described above, the IC chip is housed in the multilayer printed circuit board. In contrast, in the first modification of the second embodiment, the IC chip 220 is accommodated in the multilayer printed circuit board and the IC chip 320 is placed on the surface. As the built-in IC chip 220, a cache memory having a relatively low heat generation is used, and as the IC chip 320 at the surface layer, a CPU for calculation is placed.

이 제 2 실시형태의 제 1 변형예에 있어서는, 코어기판(230)의 스루홀(336)을 구성하는 관통공(335)이, 코어기판의 위치결정마크(231)를 기준으로 형성되고 있다.In the first modification of this second embodiment, the through hole 335 constituting the through hole 336 of the core substrate 230 is formed based on the positioning mark 231 of the core substrate.

〔제 3 실시형태〕[Third Embodiment]

이어서, 본 발명의 제 3 실시형태에 관계하는 다층프린트배선판의 구성에 대하여, 다층프린트배선판(410)의 단면을 도시하는 도 26을 참조하여 설명한다.Next, the structure of the multilayer printed circuit board according to the third embodiment of the present invention will be described with reference to FIG. 26 showing a cross section of the multilayer printed circuit board 410.

도 26에 도시하는 바와 같이 다층프린트배선판(410)은, IC칩(420)을 수용하는 코어기판(430)과, 층간수지절연층(450), 층간수지절연층(550)으로 이루어진다. 층간수지절연층(450)에는, 바이어홀(460) 및 도체회로(458)가 형성되고, 층간수지절연층(550)에는, 바이어홀(560) 및 도체회로(558)가 형성되고 있다.As shown in FIG. 26, the multilayer printed circuit board 410 includes a core substrate 430 accommodating the IC chip 420, an interlayer resin insulating layer 450, and an interlayer resin insulating layer 550. The via hole 460 and the conductor circuit 458 are formed in the interlayer resin insulating layer 450, and the via hole 560 and the conductor circuit 558 are formed in the interlayer resin insulating layer 550.

IC칩(420)에는, IC 보호막(패시베이션 + 폴리이미드)(422)이 피복되고, 해 IC보호막(422)의 개구 내에 입출력단자를 구성하는 알루미늄제 다이패드(424)가 배설되고 있다. 다이패드(424)의 표면에는, 산화피막(426)이 형성되고 있다. 다이패드(424) 상에는, 트랜지션층(438)이 형성되고, 다이패드(424)와 트랜지션층(438)과의 접촉면의 산화피막(426)은 제거되고 있다.The IC chip 420 is covered with an IC passivation film (passivation + polyimide) 422, and an aluminum die pad 424 constituting an input / output terminal is provided in the opening of the IC protection film 422. An oxide film 426 is formed on the surface of the die pad 424. The transition layer 438 is formed on the die pad 424, and the oxide film 426 on the contact surface between the die pad 424 and the transition layer 438 is removed.

층간수지절연층(550)의 상에는, 솔더레지스트층(470)이 배설되고 있다. 솔더레지스트층(470)의 개구부(471) 하의 도체회로(558)에는, 도시하지 않은 도터보드, 마더보드 등의 외부기판과 접속하기 위한 납땜범프(476), 또는, 도시하지 않은 도전성접속핀이 설치되고 있다.The solder resist layer 470 is disposed on the interlayer resin insulating layer 550. In the conductor circuit 558 under the opening 471 of the solder resist layer 470, a solder bump 476 for connecting to an external substrate such as a daughter board or a motherboard, not shown, or a conductive connecting pin (not shown) is provided. It is installed.

본 실시형태의 다층프린트배선판(410)에서는, 코어기판(430)이 IC칩(420)을 미리 내장시키고, IC칩(420)의 다이패드(424)에는 트랜지션층(438)을 배설시키고 있다. 이 때문에, 바이어홀을 형성할 때의 어레이먼트가 발생하기 쉽고, 다이패드피치 150 ㎛ 이하, 패드사이즈 20 ㎛ 이하에서도 빌드업층이 안정되게 형성할 수 있다. 트랜지션층을 형성시키지 않은 다이패드인 채로, 포토에칭에 의해 층간절연층의 바이어홀을 형성시키면, 바이어홀경이 다이패드경보다도 크면, 바이어홀 바닥 잔사제거, 층간수지절연층표면 조화처리로서 행하는 데스미어처리 시에 다이패드 표면의 확보층인 폴리이미드층을 용해, 손상한다. 한편, 레이저의 경우, 바이어홀경이 다아패드경보다도 클 때에는, 다이패드 및 패시베이션, 폴리이미드(IC의 보호막)가 레이저에 의해 파괴된다. 또, IC칩의 패드가 매우 작고, 바이어홀경이 다이패드경보다도 크게 되면, 포토에칭법으로도, 레이저법으로도 위치맞춤이 매우 곤란하고, 다이패드와 바이어홀과의 접속불량이 발생한다.In the multilayered printed circuit board 410 of the present embodiment, the core substrate 430 includes the IC chip 420 in advance, and the transition layer 438 is disposed on the die pad 424 of the IC chip 420. For this reason, the array at the time of forming a via hole is easy to generate | occur | produce, and even a die pad pitch of 150 micrometers or less and a pad size of 20 micrometers or less can build up a stably layer. When the via hole of the interlayer insulating layer is formed by photoetching with the die pad without forming the transition layer, if the via hole diameter is larger than the die pad diameter, the death performed as the via hole bottom residue removal and the interlayer resin insulating layer surface roughening treatment. During the mirror treatment, the polyimide layer, which is a layer secured on the die pad surface, is dissolved and damaged. On the other hand, in the case of a laser, when a via hole diameter is larger than a dapad diameter, a die pad, passivation, and polyimide (protective film of IC) are destroyed by a laser. In addition, when the pad of the IC chip is very small and the via hole diameter is larger than the die pad diameter, the alignment is very difficult by the photo etching method or the laser method, resulting in poor connection between the die pad and the via hole.

이에 대하여, 다이패드(424) 상에 트랜지션층(438)을 설치하는 것으로, 다이패드피치 150 ㎛ 이하, 패드사이즈 20 ㎛ 이하로 되어도 다이패드(424) 상에 바이어홀(460)을 확실하게 접속시키는 것이 가능하고, 패드(424)와 바이어홀(460)과의접속성이나 신뢰성을 향상시킨다. 또, IC칩의 패드 상에 보다 큰 지름의 트랜지션층을 개재시키는 것으로, 데스미어, 도금공정 등의 후공정 시에, 산이나 에칭액에 침적시키거나, 각종 아닐공정을 거쳐도, 다이패드 및 IC의 보호막(패시베이션, 폴리미드층)을 용해, 손상할 위험이 없어진다.On the other hand, by providing the transition layer 438 on the die pad 424, the via hole 460 is reliably connected on the die pad 424 even when the die pad pitch is 150 mu m or less and the pad size 20 mu m or less. It is possible to make it possible to improve the connectivity and reliability of the pad 424 and the via hole 460. In addition, by interposing a larger diameter transition layer on the pad of the IC chip, the die pad and the IC may be immersed in an acid or an etchant during a post-process such as a desmear or plating process or subjected to various annealing processes. There is no risk of dissolving and damaging the protective film (passivation, polyimide layer).

또, 알루미늄제의 다이패드(424)의 표면에 형성된 산화피막(426)이, 다이패드(424)와 트랜지션층(438)과의 접촉면에 있어서, 후술하는 산화피막제거처리에 의해 제거되고 있기 때문에, 다이패드(424)의 전기저항을 낮추고, 도전성을 높이는 것이 가능하게 된다.In addition, since the oxide film 426 formed on the surface of the aluminum die pad 424 is removed by the oxide film removal treatment described later on the contact surface between the die pad 424 and the transition layer 438. It is possible to lower the electrical resistance of the die pad 424 and to increase the conductivity.

이어서, 도 26을 참조하여 상술한 다층프린트배선판의 제조방법에 대하여, 도 22 ~ 도 27을 참조하여 설명한다.Next, the manufacturing method of the multilayer printed wiring board described above with reference to FIG. 26 will be described with reference to FIGS. 22 to 27.

(1) 우선, 글래스크로스 등의 심재에 에폭시 등의 수지를 함침시킨 프리프래그를 적층한 절연수지기판(코어기판)(430)을 출발재료로 한다(도 22(A)참조). 다음으로, 코어기판(430)의 한쪽 면에, 스폿페이싱가공으로 IC칩 수용부의 요부(432)를 형성한다.(도 22(B)참조).(1) First, an insulating resin substrate (core substrate) 430 having a prepreg obtained by impregnating a resin such as epoxy on a core material such as glass cross is used as a starting material (see Fig. 22 (A)). Next, a recess 432 of the IC chip accommodating portion is formed on one surface of the core substrate 430 by spot facing processing (see Fig. 22B).

(2) 그 후, 요부(432)에, 인쇄기를 사용하여 접착재료(434)를 도포한다. 이 때, 도포 이외에도, 폿팅 등을 하여도 좋다. 다음으로, IC칩(420)을 접착재료(434)상에 적재한다. IC칩(420)에는, IC 보호막(패시베이션 + 폴리이미드)(422)이 피복되고, IC보호막(422)의 개구 내에 입출력단자를 구성하는 다이패드(424)가 배설되고 있다. 또, 다이패드(424)의 표면에는, 산화피막(426)이 피복되어 있다(도 22(C)참조). 여기서, IC칩(420)의 다이패드(424)부분을 확대한 설명도를 도 27(A)에 도시한다.(2) Then, the recessed part 432 is apply | coated the adhesive material 434 using a printing machine. At this time, potting or the like may be performed in addition to the coating. Next, the IC chip 420 is mounted on the adhesive material 434. The IC chip 420 is covered with an IC passivation film (passivation + polyimide) 422, and a die pad 424 constituting an input / output terminal in the opening of the IC protection film 422 is disposed. The oxide film 426 is coated on the surface of the die pad 424 (see Fig. 22C). Here, explanatory drawing which expanded the die pad 424 part of IC chip 420 is shown to FIG. 27 (A).

(3) 그리고, IC칩(420)의 상면을 누르거나 혹은 두드려서 요부(432) 내에 완전히 수용시킨다(도 22(D)참조). 이로 인해, 코어기판(430)을 평활하게 하는 것이 가능하다.(3) Then, the upper surface of the IC chip 420 is pressed or knocked to be completely accommodated in the recessed portion 432 (see Fig. 22D). As a result, it is possible to smooth the core substrate 430.

(4) 다음으로, IC칩(420)을 수용시킨 코어기판(430)을 진공상태로 한 스패터링 장치 내에 넣고, 스패터링가스로서 불활성가스인 아르곤을 사용하며, 다이패드(424) 표면의 노출하고 있는 산화피막(426)을 제거시킨다(도 23(A)참조). 여기서, IC칩(420)의 다이패드(424) 부분을 확대한 설명도를 도 27(B)에 도시한다. 이로 인해 다이패드(424)의 전기저항을 낮추고, 도전성을 높이는 것이 가능하게 되고, 또 트랜지션층과의 밀착성이 향상한다. 여기서는, 산화피막제거처리로서 역스패터를 사용하고 있지만, 역스패터 이외에도 플라즈마처리를 행하는 것도 가능하다. 플래즈마처리로 행하는 경우는, 기판을 진공상태로 한 장치 내에 넣어, 산소, 혹은, 질소, 탄산가스, 사불화탄소 중에서 플래즈마를 방출시키고, 다이패드 표면의 산화피막을 제거시킨다. 또, 역스패터, 플래즈마처리 이외에도, 다이패드 표면을 산에 의해 처리하고, 산화피막을 제거하는 것도 가능하다. 산화피막제거처리에는, 인산을 사용하는 것이 적합하다. 여기서는 산화피막을 제거하고 있는데, 다이패드에 녹방지용의 질화막 등의 피막이 형성되고 있는 때에도, 전기도전성을 높이기 위해 제거처리를 행하는 것이 좋다.(4) Next, the core substrate 430 containing the IC chip 420 is placed in a vacuum sputtering apparatus, and argon, an inert gas, is used as the sputtering gas, and the surface of the die pad 424 is exposed. The oxide film 426 is removed (see Fig. 23A). Here, explanatory drawing which expanded the die pad 424 part of IC chip 420 is shown to FIG. 27 (B). As a result, the electrical resistance of the die pad 424 can be lowered, the conductivity can be increased, and the adhesion to the transition layer is improved. In this case, the reverse spatter is used as the oxide film removal treatment, but the plasma treatment can be performed in addition to the reverse spatter. In the case of performing the plasma treatment, the substrate is placed in a vacuum apparatus, and the plasma is released from oxygen, nitrogen, carbon dioxide, and carbon tetrafluoride to remove the oxide film on the surface of the die pad. In addition to the reverse spatter and plasma treatment, the die pad surface can be treated with an acid to remove the oxide film. For the oxide film removal treatment, it is suitable to use phosphoric acid. In this case, the oxide film is removed. Even when a film such as a nitride film for preventing rust is formed on the die pad, it is preferable to perform the removal treatment to increase the electrical conductivity.

(5) 그 후, 연속적으로 같은 장치를 사용하여, IC칩을 산소분위기에 바래이는 일이 없고, 코어기판(430)의 전면에 Cr 및 Cu를 타겟으로 한 스패터링을 행하고, 전면에 도전성의 금속막(433)을 형성시킨다(도 23(B)참조).(5) After that, using the same device continuously, the IC chip is not displaced to the oxygen atmosphere, and sputtering targeting Cr and Cu on the front surface of the core substrate 430 is performed. A metal film 433 is formed (see Fig. 23B).

금속막(433)으로서는, 주석, 크롬, 티탄, 니켈, 아연, 코발트, 금, 동 등의 금속을 1종 이상으로 형성시키는 것이 좋다. 두께로서는, 0.001 ~ 2.0 ㎛ 의 사이로 형성시키는 것이 좋다. 특히 0.01 ~ 1.0 ㎛ 가 바람직하다. 크롬의 두께는, 스패터층에 크랙이 들어가지 않고, 또 동스패터층과의 밀착이 충분히 취해지는 두께로 한다. 제 3 실시형태에서는, 피막제거와, 트랜지션층의 최하층(금속막)(433)의 형성을, 동일의 장치로 연속하여 비산소 분위기에서 행하기 때문에, 패드표면에 산화피막이 다시 형성되는 일이 없고, IC칩의 다이패드(424)와 트랜지션층(438)과의 도전성을 높이는 것이 가능하게 된다.As the metal film 433, at least one metal such as tin, chromium, titanium, nickel, zinc, cobalt, gold, or copper may be formed. As thickness, it is good to form between 0.001-2.0 micrometers. 0.01-1.0 micrometer is especially preferable. The thickness of the chromium is such that crack does not enter the spatter layer, and the thickness of the chromium is sufficiently brought into close contact with the copper spatter layer. In the third embodiment, since the removal of the film and the formation of the lowest layer (metal film) 433 of the transition layer are performed continuously in the non-oxygen atmosphere with the same apparatus, the oxide film is not formed on the pad surface again. The conductivity between the die pad 424 and the transition layer 438 of the IC chip can be improved.

금속막(433) 상에, 무전해도금, 전해도금, 또는, 그들의 복합도금에 의해, 도금막(436)을 형성시켜도 좋다(제 23도(C)). 형성되는 도금의 종류로서는 동, 니켈, 금, 은, 아연, 철 등이 있다. 전기특성, 경제성, 또, 후정에서 형성되는 빌드업인 도체층은 주로 동인 것으로부터, 동을 사용하면 좋다. 그 두께는 0.01 ~ 5 ㎛ 의 범위에서 행하는 것이 좋다. 특히 0.1 ~ 3.0 ㎛ 가 바람직하다. 스패터, 증착으로 형성하는 것도 가능하다. 또, 바람직한 제 1 박막층과 제 2 박막층과의 조합은, 크롬-동, 크롬-니켈, 티탄-동, 티탄-니켈 등이다. 금속과의 신뢰성이나 전기전달성이라는 점에서 다른 조합보다도 뛰어나다.On the metal film 433, the plating film 436 may be formed by electroless plating, electroplating, or their composite plating (FIG. 23C). Types of plating to be formed include copper, nickel, gold, silver, zinc, iron and the like. Electrical properties, economical efficiency, and the conductor layer which is a buildup formed from a back well are mainly copper, and copper may be used. It is good to perform the thickness in the range of 0.01-5 micrometers. 0.1-3.0 micrometers is especially preferable. It is also possible to form by spatter and vapor deposition. Moreover, the combination of a preferable 1st thin film layer and a 2nd thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel etc. It is superior to other combinations in terms of reliability and electrical conductivity with metals.

(6) 그 후, 레지스트를 도포하고, 혹은, 감광성필름을 라미네이트하여, 노광, 현상하여 IC칩(420)의 다이패드의 상부에 개구를 설치하도록 도금레지스트(435)를 설치하고, 전해도금막(437)을 설치한다(도 23(D)참조).(6) Then, a resist is applied or the photosensitive film is laminated, exposed and developed to provide a plating resist 435 so as to provide an opening in the upper portion of the die pad of the IC chip 420, and an electroplating film 437 is provided (see FIG. 23 (D)).

전해도금막(437)의 두께는 1 ~ 20 ㎛ 정도가 좋다. 도금레지스트(435)를 제거한 후, 도금레지스트(435) 하의 무전해도금막(436), 금속막(433)을 에칭으로 제거하는 것으로, IC칩의 패드(424) 상에 트랜지션층(438)을 형성한다.(도 24(A)참조). 또, IC칩(420)의 다이패드(424) 부분을 확대한 설명도를 도 27(C)에 도시한다.The thickness of the electroplated film 437 may be about 1 to 20 μm. After removing the plating resist 435, the electroless plating film 436 and the metal film 433 under the plating resist 435 are removed by etching to form the transition layer 438 on the pad 424 of the IC chip. (See FIG. 24 (A)). In addition, explanatory drawing which expanded the die pad 424 part of IC chip 420 is shown to FIG. 27 (C).

여기서는, 도금레지스트에 의해 트랜지션층(438)을 형성하였지만, 무전해도금막(436)의 상에 전해도금막(437)을 균일하게 형성한 후, 에칭레지스트를 형성하고, 노광, 현상하여 트랜지션층 이외의 부분의 금속을 노출시켜 에칭을 행하고, IC칩(420)의 다이패드(424) 상에 트랜지션층(438)을 형성시키는 것도 가능하다. 이 경우, 전해도금막(437)의 두께는 1 ~ 20 ㎛ 의 범위가 좋다. 그보다 두꺼워지면, 에칭 시에 언더컷이 발생해버려서, 형성되는 트랜지션층과 바이어홀과 계면에 틈이 발생하기 때문이다.Here, although the transition layer 438 is formed of a plating resist, the electroplating film 437 is uniformly formed on the electroless plating film 436, and then an etching resist is formed, exposed and developed to produce a transition layer other than the transition layer. It is also possible to expose the metal of the portion of the portion to perform etching, and to form the transition layer 438 on the die pad 424 of the IC chip 420. In this case, the thickness of the electroplated film 437 is preferably in the range of 1 to 20 µm. If thicker than that, undercut occurs during etching, and a gap is generated between the transition layer, the via hole, and the interface formed.

(7) 다음으로, 기판에 에칭액을 스프레이로 뿌리고, 트랜지션층(438)의 표면을 에칭하는 것에 의해 조화면(438α)을 형성한다(도 24(B)참조). 무전해도금이나 산화환원처리를 사용하여 조화면을 형성하는 것도 가능하다.(7) Next, an etching solution is sprayed onto the substrate, and the rough surface 438 alpha is formed by etching the surface of the transition layer 438 (see FIG. 24 (B)). It is also possible to form a roughened surface using electroless plating or redox treatment.

(8) 상기 공정을 거친 기판에, 제 1 실시형태와 같은 열경화수지시트를 진공압착 라미네이트하고, 층간수지절연층(450)을 설치한다(도 24(C)참조).(8) On the board | substrate which passed the said process, the thermosetting resin sheet like the 1st Embodiment is vacuum-pressed laminated, and the interlayer resin insulating layer 450 is provided (refer FIG. 24 (C)).

(9) 다음으로, CO2가스레이저로 층간수지절연층(450)에 바이어홀용 개구(448)을 설치한다(도 24(D)참조). 그 후, 크롬산, 과망간산 등의 산화제를 사용하여 개구(448) 내의 수지잔재를 제거하여도 좋다. 다이패드(424) 상에 동제의 트랜지션층(438)을 설치하는 것으로, 바이어홀을 형성하는 때의 언더컷을 발생하기 쉽게 하고, 다이패드(424) 상에 바이어홀을 확실하게 접속시켜, 패드와 바이어홀과의 접속성이나 신뢰성을 향상시킨다. 이로 인해, 빌드업층이 안정하여 형성할 수 있다. IC칩의 패드 상에 보다 큰 지름의 트랜지션층을 개재시키는 것으로, 바이어홀 바닥 잔사제거, 층간수지절연층표면 조화처리로서 행하는 데스미어처리 시, 도금공정 등의 후공정 시에, 산이나 에칭액에 침적시키거나, 각종 아닐공정을 거쳐도, 다이패드(424) 및 IC의 보호막(패시베이션, 폴리미드층)(422)을 용해, 손상할 위험이 없어진다. 또, 여기서는, 과망간산을 사용하여 수지잔류를 제거하였지만, 산소플래즈마를 사용하여 데스미어처리를 행하는 것도 가능하다.(9) Next, a via hole opening 448 is provided in the interlayer resin insulating layer 450 with a CO 2 gas laser (see FIG. 24 (D)). Thereafter, the resin residue in the opening 448 may be removed using an oxidizing agent such as chromic acid or permanganic acid. By providing a copper transition layer 438 on the die pad 424, it is easy to generate an undercut when forming the via hole, and securely connects the via hole on the die pad 424, Improves the connection and reliability with the via hole. For this reason, a buildup layer can be formed stably. By interposing a larger diameter transition layer on the pad of the IC chip, the desmear treatment performed as a via hole bottom residue removal and interfacial resin insulating layer surface roughening treatment, and the acid or etching solution during the post-process such as plating process. Even if it deposits or goes through various annealing processes, there exists no risk of melt | dissolving and damaging the die pad 424 and the protective film (passivation, polyimide layer) 422 of IC. In addition, although the resin residue was removed using permanganic acid here, it is also possible to perform desmear treatment using oxygen plasma.

(10) 다음으로, 층간수지절연층(450)의 표면을 조화하고, 조화면(450α)을 형성한다(제 25도(A)참조). 또, 이 조화공정은 생략하는 것도 가능하다.(10) Next, the surface of the interlayer resin insulating layer 450 is roughened to form a rough surface 450α (see FIG. 25 (A)). In addition, this roughening process can also be abbreviate | omitted.

(11) 다음으로, 층간수지절연층(450)의 표면에 팔라디움 촉매를 부여한 후, 무전해도금액에 기판을 침적하고, 무전해도금막(452)을 층간수지절연층(450)의 표면에 형성한다(도 25(B)참조).(11) Next, after applying a palladium catalyst to the surface of the interlayer resin insulating layer 450, a substrate is deposited in the electroless plating solution, and an electroless plated film 452 is formed on the surface of the interlayer resin insulating layer 450. (See FIG. 25 (B)).

(12) 상기 처리를 끝낸 기판(430)에, 시판의 감광성 드라이필름을 붙이고, 크롬글래스 마스크를 적재하고, 40 mJ/㎠ 로 노광한 후, 0.8 % 탄산나트륨으로 현상처리하고, 두께 25 ㎛ 의 도금레지스트(454)를 설치한다. 다음으로, 제 1 실시형태와 같은 조건에서 전해도금을 실시하고, 두께 18 ㎛ 의 전해도금막(456)을 형성한다(도 25(C)참조).(12) A commercially available photosensitive dry film was attached to the finished substrate 430, a chromium glass mask was loaded, exposed at 40 mJ / cm 2, then developed with 0.8% sodium carbonate, and plated with a thickness of 25 μm. The resist 454 is provided. Next, electroplating is performed under the same conditions as in the first embodiment, and an electroplated film 456 having a thickness of 18 µm is formed (see Fig. 25C).

(13) 도금레지스트(454)를 5% NaOH 로 박리제거한 후, 그 도금레지스트 하의 금속층(452)을 에칭으로 용해제거하고, 무전해도금막(452)과 전해도금막(456)으로 이루어지는 두께 16 ㎛ 의 도체회로(458) 및 바이어홀(460)을 형성하고, 에칭액에 의해, 조화면(458α,460α)을 형성한다(도 25(D)참조). 이하의 공정은, 상술한 제 1 실시형태의 (13) ~ (17)과 동일하기 때문에 설명을 생략한다.(13) After the plating resist 454 is stripped off with 5% NaOH, the metal layer 452 under the plating resist is removed by etching, and the thickness of the electroless plated film 452 and the electroplated film 456 is 16 mu m. The conductor circuit 458 and the via hole 460 are formed, and roughened surfaces 458α and 460α are formed by etching solution (see FIG. 25 (D)). Since the following processes are the same as (13)-(17) of 1st Embodiment mentioned above, description is abbreviate | omitted.

〔제 3 실시형태의 제 1 변형예〕[First Modification of Third Embodiment]

이어서, 제 3 실시형태의 제 1 변형예에 관계하는 다층프린트배선판에 대하여, 도 28 및 도 29를 참조하여 설명한다. 도 28은, 다층프린트배선판(510)의 단면을 도시하고, 도 29는, 다이패드(424)부분을 확대하여 도시하는 도이며, 도 29(A)는, 산화피막제거처리되기 전의 상태를 도시하는 도면, 도 29(B)는, 산화막제거처리 후의 상태를 도시하는 도면, 도 29(C)는, 다이패드(424) 상에 트랜지션층(438)을 형성한 후를 도시하는 도면이다.Next, a multilayer printed circuit board according to a first modification of the third embodiment will be described with reference to FIGS. 28 and 29. FIG. 28 shows a cross section of the multilayer printed circuit board 510, FIG. 29 is an enlarged view of a portion of the die pad 424, and FIG. 29 (A) shows a state before the oxide film removing process is performed. FIG. 29B is a diagram showing a state after the oxide film removal treatment, and FIG. 29C is a diagram showing the formation of the transition layer 438 on the die pad 424.

상술한 제 3 실시형태에선, BGA를 배설한 경우로 설명하였다. 제 3 실시형태의 제 1 변형예에서는, 제 3 실시형태와 거의 같지만, 도 28에서 도시하는 바와 같이 도전성접속핀(496)을 개재하여 접속을 취하는 PGA방식으로 구성되고 있다.In 3rd Embodiment mentioned above, it demonstrated as the case where BGA was excreted. In the first modification of the third embodiment, it is almost the same as in the third embodiment, but is constituted by a PGA system which connects via the conductive connecting pins 496 as shown in FIG.

제 3 실시형태의 제 1 변형예의 제조방법으로는, 도 29(B)에 도시하는 바와 같이 다이패드(424)의 산화피막(426)의 일부분을 역스패터, 플래즈마처리, 산처리의 어느 한 산화막제거처리를 실시하여 제거한다. 그 후, 도 29(C)에 도시하는 바와 같이 다이패드(424) 상에, 금속막(433) 및 무전해도금막(436), 전해도금막(437)으로 이루어지는 트랜지션층(438)을 형성시킨다. 이로 인해, 제 3 실시형태와 같은다이패드(426)의 전기저항을 낮추고, 도전성을 높이는 것이 가능하게 된다.As a manufacturing method of the first modification of the third embodiment, as shown in Fig. 29B, a part of the oxide film 426 of the die pad 424 is subjected to any of reverse spattering, plasma treatment, and acid treatment. An oxide film removing treatment is performed to remove it. After that, as shown in FIG. 29C, a transition layer 438 including a metal film 433, an electroless plating film 436, and an electroplating film 437 is formed on the die pad 424. . For this reason, it becomes possible to lower the electrical resistance of the die pad 426 like 3rd Embodiment, and to raise electroconductivity.

〔비교예〕[Comparative Example]

피막제거를 행하지 않는 이외는, 제 3 실시형태와 같이 트랜지션층을 형성하여 다층프린트배선판을 얻었다.Except not removing the film, a transition layer was formed as in the third embodiment to obtain a multilayer printed wiring board.

실험결과Experiment result

제 3 실시형태와 비교예의 다층프린트배선판을 1)단면상태, 2)저항측정, 3)신뢰성시험 후의 단면상태, 4)저항측정치의 계 4항목에 대하여 평가를 행한 결과를 도 30 중의 도표에 도시한다.The results of evaluating the multilayered printed circuit boards of the third embodiment and the comparative example with respect to 4 items of 1) cross-sectional state, 2) resistance measurement, 3) cross-sectional state after reliability test, and 4) resistance measurement values are shown in the chart in FIG. do.

1)단면상태1) Cross section state

트랜지션층을 형성한 후, 단면을 절단하여, 패드 상의 산화막의 유무에 대하여 현미경(×100)으로 관찰하였다.After forming the transition layer, the cross section was cut and observed with a microscope (x100) for the presence or absence of an oxide film on the pad.

2)저항측정치2) resistance measurement

트랜지션층 형성 후에, 접속저항을 측정하였다. 측정한 수치는, 20개소를 측정한 평균이다.After the formation of the transition layer, the connection resistance was measured. The measured numerical value is the average which measured 20 places.

3)신뢰성실험 후의 단면상태3) Cross-sectional state after reliability test

다층프린트배선판 형성 후에, 히트사이클시험((130℃/3분) + (-60℃/3분)을 1 사이클로 하여 1000 사이클 실시하였다) 종료 후에, 단면을 절단하여, 패드 상의 산화피막의 유무, 및 트랜지션층의 박리의 유무에 대하여, 현미경(×100)으로 관찰하였다.After the formation of the multilayer printed wiring board, after the end of the heat cycle test ((130 DEG C / 3 minutes) + (-60 DEG C / 3 minutes) was performed for 1000 cycles), the cross section was cut and the presence or absence of an oxide film on the pad, And it observed with the microscope (* 100) about the presence or absence of peeling of a transition layer.

4)신뢰성시험 후의 저항측정치4) Resistance measurement after reliability test

다층프린트배선판 형성 후에, 히트사이클시험((130℃/3분) + (-60℃/3분)을 1 사이클로 하여 1000 사이클 실시하였다) 종료 후에, 접속저항을 측정한다. 측정한 수치는, 20개소를 측정한 평균이다.After the multilayer printed circuit board was formed, the connection resistance was measured after the end of the heat cycle test ((130 ° C./3 minutes) + (−60 ° C./3 minutes) was performed for 1 cycle). The measured numerical value is the average which measured 20 places.

도 30 중의 도표에 도시하는 바와 같이, 제 3 실시형태의 다층프린트배선판은, 산화막도 없고, 접속저항치도 작기 때문에, 전기적인 접속에 문제를 발생하는 일이 없었다. 또, 신뢰성시험 후도 열등해짐이 적었다. 덧붙여, 히트사이클시험을 2000 사이클 반복한 후에도, 그리 저항치의 증가는 발견되지 않았다.As shown in the diagram in Fig. 30, the multilayer printed circuit board of the third embodiment has no oxide film and has a small connection resistance, so that no problem occurs in electrical connection. Moreover, there was little inferiority even after the reliability test. In addition, even after repeated 2000 cycles of the heat cycle test, no increase in resistance was found.

비교예는, 산화막이 남고, 접속저항치도 크다. 경우에 따라서는 전혀 전기적 접속이 취해지지 않는 곳도 발견되었다. 신뢰성시험 후에 다시 그 경향이 현저하게 나타났다.In the comparative example, the oxide film remained and the connection resistance value was also large. In some cases, no electrical connection was found. The trend was remarkable again after the reliability test.

다층프린트배선판은, 코어기판(30)에 IC칩(20)을 미리 내장시키고, 해 IC칩(20)의 패드(24)에는 트랜지션층(38)을 배설시키고 있다.In the multilayer printed circuit board, the IC chip 20 is embedded in the core substrate 30 in advance, and the transition layer 38 is disposed on the pad 24 of the IC chip 20.

이 때문에, 리드부품이나 봉지수지를 사용하지 않고, IC칩과 다층프린트배선판과의 전기적 접속을 취하는 것이 가능하다. 또, 다이패드(24) 상에 동제의 트랜지션층(38)을 설치하는 것으로, 패드(24) 상의 수지잔재를 방지할 수 있어, 패드(24)와 바이어홀(60)과의 접속성이나 신뢰성을 향상시킨다.For this reason, it is possible to make electrical connection with an IC chip and a multilayer printed wiring board, without using a lead component or sealing resin. Moreover, by providing the copper transition layer 38 on the die pad 24, the resin residue on the pad 24 can be prevented, and the connection and reliability of the pad 24 and the via hole 60 can be prevented. To improve.

Claims (20)

기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀이 형성되며, 상기 바이어홀을 개재하여 전기적 접속되는 다층프린트배선판에 있어서,In a multilayer printed circuit board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, and via holes are formed in the interlayer insulating layer, and are electrically connected through the via holes. 상기 기판에는, 전자부품이 내장되고 있는 것을 특징으로 하는 다층프린트배선판.An electronic component is embedded in the substrate, the multilayer printed circuit board. 제 1 항에 있어서, 표면에 전자부품이 실장되어 있는 것을 특징으로 하는 다층프린트배선판The multilayer printed wiring board according to claim 1, wherein an electronic component is mounted on the surface. 제 1 항 또는 2 항에 있어서, 상기 기판에는, 외부기판과 접속하는 단자가 배설되어 있는 것을 특징으로 하는 다층프린트배선판.The multilayer printed wiring board according to claim 1 or 2, wherein said substrate is provided with terminals connected to an external substrate. 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀이 형성되고, 상기 바이어홀을 개재하여 전기적 접속되는 다층프린트배선판에 있어서,In a multilayer printed circuit board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, a via hole is formed in the interlayer insulating layer, and is electrically connected through the via hole. 상기 기판에는, 전자부품이 내장되고,In the substrate, an electronic component is embedded, 상기 전자부품의 패드부분에는, 최하층의 층간절연층의 바이어홀과 접속하기 위한 트랜지션층이 형성되어 있는 것을 특징으로 하는 다층프린트배선판.And a transition layer for connecting with the via hole of the lowest interlayer insulating layer in the pad portion of the electronic component. 제 1 항 내지 4 항 기재의 어느 한 항에 있어서, 상기 기판은, 패키지기판인 것을 특징으로 하는 다층프린트배선판.The multilayer printed wiring board according to any one of claims 1 to 4, wherein the substrate is a package substrate. 전자부품이 내장된 기판 상에 층간수지절연층과 도체층이 반복하여 형성된 다층프린트배선판에 있어서,In a multilayer printed circuit board in which an interlayer resin insulating layer and a conductor layer are repeatedly formed on a substrate having an electronic component embedded therein, 상기 전자부품의 패드부분에는, 최하층의 층간수지절연층의 바이어홀과 접속하기 위한 트랜지션층이 적어도 2층으로 형성되고 있는 것을 특징으로 하는 다층프린트배선판.And a transition layer for connecting with the via hole of the lowermost interlayer resin insulating layer is formed in at least two layers in the pad portion of the electronic component. 제 6 항에 있어서, 상기 트랜지션층의 폭은, 패드의 폭의 1.0 ~ 30 배인 것을 특징으로 하는 다층프린트배선판.The multilayer printed wiring board according to claim 6, wherein the width of the transition layer is 1.0 to 30 times the width of the pad. 전자부품이 내장된 기판 상에 층간수지절연층과 도체층이 반복하여 형성된 다층프린트배선판에 있어서,In a multilayer printed circuit board in which an interlayer resin insulating layer and a conductor layer are repeatedly formed on a substrate having an electronic component embedded therein, 상기 전자부품의 패드부분에는, 최하층의 층간수지절연층의 바이어홀과 접속하기 위한 트랜지션층이 적어도 제 1 박막층, 제 2 박막층, 후부층으로 형성되어 있는 것을 특징으로 하는 다층프린트배선판.And a transition layer for connecting to a via hole of a lowermost interlayer resin insulating layer is formed of at least a first thin film layer, a second thin film layer, and a rear layer in the pad portion of the electronic component. 제 8 항에 있어서, 상기 제 1 박막층은, 주석, 크롬, 티탄, 니켈, 아연, 코발트, 금, 동 가운데서 선택되어지는 1 종류 이상인 것을 특징으로 하는 다층프린트배선판.The multilayer printed wiring board according to claim 8, wherein the first thin film layer is at least one selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper. 제 8 항에 있어서, 상기 제 2 박막층은, 니켈, 동, 금, 은 가운데서 선택되어지는 1 종류 이상인 것을 특징으로 하는다층프린트배선판.The multilayer printed wiring board according to claim 8, wherein the second thin film layer is at least one selected from nickel, copper, gold and silver. 전자부품이 내장된 기판 상에 층간수지절연층과 도체층이 반복하여 형성된 다층프린트배선판에 있어서,In a multilayer printed circuit board in which an interlayer resin insulating layer and a conductor layer are repeatedly formed on a substrate having an electronic component embedded therein, (a) 상기 전자부품이 매입된 기판의 전체면에 제 1 박막층, 제 2 박막층을 형성하는 공정,(a) forming a first thin film layer and a second thin film layer on the entire surface of the substrate on which the electronic component is embedded; (b) 상기 박막층 상에 레지스트를 실시하고, 레지스트의 비형성부에 후부층을 형성하는 공정.(b) Process of performing resist on the said thin film layer and forming a back layer in the non-form part of a resist. (c) 에칭에 의해 박막층을 제거하는 공정.(c) A step of removing the thin film layer by etching. 을 적어도 경유하여 전자부품 상에 트랜지션층을 형성시키는 것을 특징으로 하는 다층프린트배선판의 제조방법.A transition layer is formed on an electronic component via at least a method of manufacturing the multilayer printed circuit board. 제 11 항에 있어서, 상기 제 1 박막층은, 스패터, 증착의 어느 하나로 행하여지는 것을 특징으로 하는 다층프린트배선판의 제조방법.12. The method of manufacturing a multilayer printed circuit board according to claim 11, wherein said first thin film layer is formed by one of sputtering and vapor deposition. 제 11 항에 있어서, 상기 제 2 박막층은, 스패터, 증착, 무전해도금의 어느하나로 행하여지는 것을 특징으로 하는 다층프린트배선판의 제조방법.12. The method of manufacturing a multilayer printed circuit board according to claim 11, wherein said second thin film layer is formed by one of sputtering, vapor deposition, and electroless plating. 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀이 형성되며, 상기 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서,In the method of manufacturing a multilayer printed circuit board, wherein an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, and via holes are formed in the interlayer insulating layer, and electrically connected through the via holes. (a) 상기 기판에 전자부품을 수용하는 공정 ;(a) accommodating an electronic component in the substrate; (b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 레이저로 형성하는 공정 ;(b) forming a positioning mark on the substrate with a laser based on the positioning mark of the electronic component; (c) 상기 기판의 위치결정마크에 기초하여 가공 혹은 형성을 행하는 공정(c) process of forming or forming based on positioning mark of said substrate 을 적어도 구비하는 것을 특징으로 하는 다층프린트배선판의 제조방법.At least a manufacturing method of a multilayer printed circuit board characterized in that it comprises. 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀을 형성하고, 상기 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서,In the method of manufacturing a multilayer printed circuit board, wherein an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, and via holes are formed in the interlayer insulating layer and electrically connected through the via holes. (a) 상기 기판에 전자부품을 수용하는 공정 ;(a) accommodating an electronic component in the substrate; (b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 레이저로 형성하는 공정 ;(b) forming a positioning mark on the substrate with a laser based on the positioning mark of the electronic component; (c) 상기 기판의 위치결정마크에 금속막을 형성하는 공정 ;(c) forming a metal film on the positioning mark of the substrate; (d) 상기 기판의 위치결정마크에 기초하여 가공 혹은 형성을 행하는 공정(d) processing or forming based on the positioning marks of the substrate 을 적어도 구비하는 것을 특징으로 하는 다층프린트배선판의 제조방법 :.Method for producing a multi-layer printed circuit board, characterized in that it comprises at least. 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀을 형성하고, 상기 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서,In the method of manufacturing a multilayer printed circuit board, wherein an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, and via holes are formed in the interlayer insulating layer and electrically connected through the via holes. (a) 상기 기판에 전자부품을 수용하는 공정 ;(a) accommodating an electronic component in the substrate; (b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 레이저로 형성하는 공정 ;(b) forming a positioning mark on the substrate with a laser based on the positioning mark of the electronic component; (c) 상기 기판의 위치결정마크에 금속막을 형성하는 공정;(c) forming a metal film on the positioning mark of the substrate; (d) 상기 기판에 층간절연층을 형성하는 공정 ;(d) forming an interlayer insulating layer on the substrate; (e) 상기 기판의 위치결정마크에 기초하여 상기 층간절연층에 바이어홀용 개구를 가공 혹은 형성을 행하는 공정;(e) processing or forming the via hole opening in the interlayer insulating layer based on the positioning mark of the substrate; 을 적어도 구비하는 것을 특징으로 하는 다층프린트배선판의 제조방법.At least a manufacturing method of a multilayer printed circuit board characterized in that it comprises. 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀을 형성하고, 상기 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서,In the method of manufacturing a multilayer printed circuit board, wherein an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, and via holes are formed in the interlayer insulating layer and electrically connected through the via holes. (a) 상기 기판에 전자부품을 수용하는 공정 ;(a) accommodating an electronic component in the substrate; (b) 상기 전자부품의 다이패드의 표면의 피막을 제거하는 공정 ;(b) removing the coating on the surface of the die pad of the electronic component; (c) 상기 다이패드 상의, 최하층의 층간절연층의 바이어홀과 접속시키기 위한 트랜지션층을 형성하는 공정.(c) forming a transition layer on the die pad to connect with the via hole of the lowest interlayer insulating layer. (d) 상기 기판 상에, 층간절연층을 형성하는 공정 ;(d) forming an interlayer insulating layer on the substrate; (e) 상기 층간절연층에, 도체회로 및 트랜지션층에 접속하는 바이어홀을 형성하는 공정;(e) forming a via hole in said interlayer insulating layer, said via hole connecting to a conductor circuit and a transition layer; 적어도 구비하는 것을 특징으로 하는 다층프린트배선판의 제조방법.A method of manufacturing a multilayer printed circuit board, characterized in that it comprises at least. 제 17 항에 있어서, 상기 산화피막제거를 역스패터, 플래즈마처리의 어느 하나로 행하는 것을 특징으로 하는 다층프린트배선판의 제조방법.18. The method of manufacturing a multilayer printed wiring board according to claim 17, wherein said oxide film is removed by either reverse spattering or plasma treatment. 제 18 항에 있어서, 상기 피막제거와, 트랜지션층의 최하층의 형성을, 비산소분위기 중에서 행하는 것을 특징으로 하는다층프린트배선판의 제조방법.19. The method of manufacturing a multilayer printed wiring board according to claim 18, wherein the film removal and the formation of the lowermost layer of the transition layer are performed in a non-oxygen atmosphere. 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀이 형성되고, 상기 바이어홀을 개재하여 전기적 접속되는 다층프린트배선판에 있어서,In a multilayer printed circuit board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, a via hole is formed in the interlayer insulating layer, and is electrically connected through the via hole. 상기 기판에는, 전자부품이 내장되고,In the substrate, an electronic component is embedded, 상기 전자부품의 패드부분에는, 최하층의 층간절연층의 바이어홀과 접속하기 위한 트랜지션층이 형성되고,In the pad portion of the electronic component, a transition layer for connecting with the via hole of the lowest interlayer insulating layer is formed, 상기 다이패드의 표면의 피복이 제거되어 있는 것을 특징으로 하는 다층프린트배선판.The multilayer printed wiring board, wherein the coating on the surface of the die pad is removed.
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