KR20020096650A - arbitration apparatus for memory access in video processor and method of the same - Google Patents

Abstract

PURPOSE: A device and a method for mediating memory access of a video processor are provided to disperse requests by changing the priority according to the state of FIFOs, thereby more efficiently using bandwidth to a memory. CONSTITUTION: A device for mediating memory access of a video processor includes a memory(40) storing data required for image processing, a plurality of function blocks processing images by reading and writing the data stored at the memory according to the preliminarily set priority, a plurality of FIFOs temporarily storing the data to be read and written at the plurality of function blocks, and a mediator controller(30) changing the priority preliminarily set at the plurality of function blocks according to the amount of the data stored at the plurality of FIFOs.

Description

Arbitration apparatus for memory access in video processor and method of the same

The present invention relates to a memory arbitration method of an image processor, and more particularly, to an apparatus and method for memory access arbitration of an image processor for efficiently using a memory by adjusting an priority according to a state of a FIFO.

Standards for processing images vary depending on the image processor (MPEG-2 decoder, TS / PS decoder, format converter), but the data for image processing is accessed by using the data required by each block in one memory. .

In this way, in serving the data required by each block in memory, the memory serves only one block of data at a time.

Therefore, in the related art, priorities are predefined for each block according to the service frequency and quantity of each block through the arbitration control unit, and services are provided to each block according to the priority.

In this case, data can be serviced more efficiently in each block according to how the priority is set in each block, and the bandwidth of the memory can be maximized. Therefore, research on this is ongoing.

Among the most commonly used methods, when a data request is input from each block to memory, the arbitration control section has the highest priority for requests that are frequently requested in consideration of the interval, minimum, and maximum number of words in each block request. Value, and low priority for requests that do not.

However, when the arbitrator controller is designed in this manner, the following problem occurs.

First, when one first block requests data from the memory a lot during the memory bandwidth, that is, the minimum latency to read / write data into the memory, the efficiency of the memory bandwidth may be increased. However, when a request of another second block having a high priority occurs in the middle, a case in which the first block cannot read / write the requested data into the memory during a time required for data read / write may occur.

For example, suppose that when a request of a first block requests data from the memory at n time intervals, a second block having a higher priority value than the first block requests data from the memory at n time points.

Then, the first block cannot receive the necessary data from the time when the second block requests data from the memory. Accordingly, the first block uses the past data as it is, so that the image converter cannot correctly process the image. As a result, the image processed by the image converter is broken.

Second, if the memory bandwidth is reduced for the first reason, the first problem is solved, but the problem of wasteing the memory bandwidth occurs.

Third, when one first block requests data from the memory for minimum latency to read / write data into the memory, a plurality of high-priority blocks consecutively request data from the memory. In this case, the first block may be pushed to a priority level so that it may not read / write the requested data.

For example, a minimum latency required for data read / write of the first block is 10 and a time taken to read / write necessary data is 3. The time taken for the second block to read / write the data is 5, and the time taken for the third block to read / write the data is 4.

At this time, when the first block requests data at time 0, the second block having a higher priority has a data request at time 2, and if the third block having a higher priority has a data request at time 7, the first block has a request for data. One block leaves the time 1 to read / write the data and is pushed to priority so that the data cannot be read / written within the required minimum latency.

Accordingly, the present invention has been made to solve the above problems, in the case of processing a plurality of requests, low priority requests are pushed by high priority requests do not satisfy the minimum latency (minimum latency) An object of the present invention is to provide a memory access arbitration method of an image processor.

Another object of the present invention is to efficiently use each data service within the entire required time to maximize the memory bandwidth.

1 is a diagram illustrating a structure for reading data in a memory according to the present invention.

2 is a diagram illustrating a structure for writing data in a memory according to the present invention;

3 is a view showing a description of the entire control signal for the case of data read or write according to the present invention

4A is a timing diagram illustrating a method of converting priorities in an arbiter controller according to the present invention.

4b is a timing diagram for another embodiment showing a method of converting priority in an arbiter controller according to the present invention;

* Explanation of symbols for main parts of the drawings

10: function block unit 20: FIFO control unit

30: arbiter control unit 40: memory

The memory access arbitration apparatus of the image processor according to the present invention for achieving the above object is a memory for storing data necessary for image processing, and the data stored in the memory in accordance with a predetermined priority to read / write the image A plurality of function blocks for processing a plurality of functions, a plurality of FIFOs temporarily storing data read / written in the plurality of function blocks, and a priority set in the plurality of function blocks according to the amount of data stored in the plurality of FIFOs. It is configured to include an arbiter control unit for changing the.

The memory access arbitration method of the image processor according to the present invention for achieving the above object is a first step of detecting a plurality of functional blocks requested by receiving a data request signal requested in each functional block, and the request Transmitting a permission signal according to the requested data request signal to the FIFO control unit, receiving a quantity of data stored in each FIFO, and changing a priority of the plurality of FIFOs; and a memory according to the changed priority of the plurality of FIFOs. A third step of storing the data stored in the FIFO and a fourth step of retrieving the amount of data stored in the FIFO, and transferring the data to the corresponding function block when the data is filled in the FIFO. There is this.

At this time, the second step is to change the priority value in the order of full <(half full = half empty) <empty according to the amount of data stored in each FIFO. There are other features.

Another aspect of the memory access arbitration method of the image processor according to the present invention for achieving the above object is a first step of storing the data to be written to the memory in each function block in the FIFO, and the data in the FIFO A second step of transmitting a data write request signal and the amount of data stored in each FIFO when the predetermined area is filled; changing the priority according to the amount of data stored in each FIFO, and storing the data in the memory according to the changed priority. And a third step of storing.

At this time, the third step is to change the priority value in the order of full> (half full = half empty)> amplifier according to the amount of data stored in each FIFO There is another feature.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

A preferred embodiment of the memory access arbitration method of the image processor according to the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating a structure for reading data in a memory according to the present invention, and FIG. 2 is a diagram illustrating a structure for writing data in a memory according to the present invention.

1 and 2, a memory 40 for storing data necessary for image processing and a plurality of functional blocks for processing an image by reading / writing data stored in the memory 40 according to a predetermined priority ( 10) and a plurality of FIFOs 20 which temporarily store data read / written to the plurality of functional blocks 10 and the plurality of functional blocks according to the amount of data stored in the plurality of FIFOs 20. It consists of an arbiter control unit 30 for changing the preset priority.

In this case, the arbiter controller 30 divides each of the functional blocks into full, half full, half empty, and empty according to the amount of data.

The memory access arbitration method of the image processor configured as described above will be described in detail with reference to the accompanying drawings.

First, a case of reading data from a memory into a functional block will be described with reference to FIG. 1.

The functional block unit 10 sends a data request signal to the arbiter controller 30 in order to fetch data required by the memory 40 from the memory 40. Then, the arbiter controller 30 transmits the permission signal according to the request signal to the FIFO controller 20, and then the FIFO controller 20 notifies the arbiter controller 30 of the amount of data stored in each FIFO. .

The arbiter controller 30 selects an appropriate one according to the amount of data stored in the FIFO among the plurality of requests requested by the function block unit 10 and sends a data control signal to the memory 40 to access data in a specific region. send.

The memory 40 then transmits the corresponding data to the FIFO control unit, and simultaneously sends a response signal according to the data control signal to the arbiter control unit.

The FIFO control unit 20 then stores the data transferred from the memory 40 in the corresponding FIFO.

At this time, the arbiter control unit 30 retrieves the amount of data stored in the FIFO, and when the data is filled to some extent in the FIFO, it notifies the functional block unit 10 that there is data to be delivered. .

The arbiter controller 30 transmits a data transfer signal to the FIFO controller 20 to transfer the data stored in the FIFO to the corresponding block of the functional block unit 10 through the data bus.

Next, a case in which the functional block writes data to the memory will be described with reference to FIG. 2.

First, the functional block unit 10 sends data to be written to the memory 40 to the FIFO control unit 20 to sequentially store the data in the FIFO.

When the data is filled up to a certain level in the FIFO, the FIFO control unit 20 transmits a request signal to the arbiter control unit 30 to write data to the memory and the amount of data currently stored in each FIFO.

The arbiter controller 30 then sends a request signal to the memory 40 indicating that there is data to be written in a specific area of the memory, and the memory 40 sends a response signal according to the request signal to the arbiter controller 30.

Subsequently, when the response signal is transmitted from the memory 40, the arbiter control unit 30 determines the priority according to the amount of data stored in each FIFO of the FIFO control unit 20, and the FIFO control unit 20 stores the corresponding data in the memory 40. To be transferred via the data bus.

The description of the entire control signal for the case of reading or writing data to the memory as described above will be described in detail with reference to FIG. 3.

First, a memory read that reads data from the memory 40 and transfers the data to the functional block unit 10 will be described.

When the function block unit 10 reads a specific area of the memory 40, the function block unit 10 transmits a read request signal Read_ready to the arbiter controller 30, and then the arbiter controller 30. The function block unit 10 sends a read permission signal (Read_grant) to the FIFO control unit 20 to inform that the read request has come.

Then, the FIFO control unit 20 knows that there is data coming from the memory 40 side, and the FIFO control unit 20 transmits the amount of data stored in each FIFO to the arbiter control unit 30 through the Fstatus_x [1: 0] signal. do.

The Fstate_X [1: 0] is a signal representing the state of each FIFO, "00" represents an amplifier, "01" represents a half empty / full, and "10". Represents full.

At this time, the arbiter control unit 30 sends a (x, y) coordinate value to a block for converting a logical address into a physical address for a specific part of the memory 40. convert to column, bank.

The arbiter control unit 30 determines the priority of each FIFO according to the amount of data stored in the FIFO, and sends a control signal Mcmd_req to request the corresponding data of the high priority FIFO to the memory 40.

Then, the memory 40 sends a response signal (mcmd_ack) that receives the request signal of the block back to the arbiter controller 30, and simultaneously transmits the corresponding data to the FIFO controller 20.

At this time, when the response signal mcmd_ack is transmitted, the arbiter controller 30 sends the function block unit 10 a read start signal Read_ready to prepare for the next request.

The FIFO control unit 20 fills the memory data with each FIFO, and then provides the function block unit 10 with a read_valid signal to inform the FIFO that data is ready and delivers the data to the function block unit.

Next, a memory write for transferring data from the functional block unit 10 to the memory 40 will be described.

The functional block unit 10 writes data to a plurality of FIFOs through a data bus connected to the FIFO control unit 20, in which the data is written to the FIFO in synchronization with write_valid of FIG. 3.

When data is filled in the plurality of FIFOs as described above, the write request signal write_request is transmitted to the arbiter controller 30 to inform that the data is to be written to the memory.

At this time, the FIFO control unit 20 transmits the amount of data stored in each FIFO to the arbiter control unit 30 through the Fstatus_x [1: 0] signal.

The Fstate_X [1: 0] is a signal representing the state of each FIFO, "00" represents an amplifier, "01" represents a half empty / full, and "10". Represents full.

Subsequently, when the write request signal write_request is input, the arbiter control unit 30 transmits a request signal mcmd_A_req indicating that there is data to be input to the memory 40. The response signal mcmd_A_ack is transmitted to the arbiter controller 30.

Then, the arbiter controller 30 transmits an approval signal (write_grant) according to the write to the FIFO controller 20 to inform that the memory 40 is ready to receive data.

Subsequently, the FIFO controller transfers data to the memory 40 to perform writing.

The arbiter controller 30 notifies the function block unit 10 of the write_ready signal so that the next request can be prepared.

As such, the arbiter controller 30 is a block for processing a request for reading and writing data from various functional blocks into a memory, and is a block for determining which block is to be processed and given data at the present time.

An operation when the arbiter controller 30 receives several requests simultaneously will be described with reference to the following embodiments.

4A is a timing diagram illustrating a method of converting priorities in an arbiter controller according to the present invention.

Referring to FIG. 4A, three requests for leads and two requests for lights are indicated, and the priority becomes smaller from the top to the bottom.

First, in the time point (0) of FIG. 4A, all requests are requested together, all the FIFO states for the read request are empty, and all the FIFO states for the write request are half empty. to be.

Therefore, the first thing that needs to be serviced is to fill data into Req_A_read, Req_B_read, and Req_C_read which have an empty state. In this case, the service is provided according to a predetermined priority value.

Therefore, the service having the highest priority Req_A_read at the time point (0) of FIG. 4A is serviced first, and the next request is determined at the time point (1) of FIG. 4A.

At this point, looking at which requests are high and the state of each FIFO,

1) Red_B_read, Req_C_read is high, FIFO state is Empty,

2) Red_D_write and Req_E_write are high and FIFO state is Half Empty.

Therefore, the following services are provided in order of priority, so you can provide Req_B_read.

As seen from the time point (2) of Fig. 4A,

1) Req_C_read is high, FIFO state is Empty,

2) Red_D_write and Req_E_write are high and FIFO state is Half Empty.

Therefore, the following services should be provided to Req_C_read in order of priority.

Then, at the time point (3) of Fig. 4A,

1) Req_D_write and Req_E_write are high and FIFO state is Half Empty.

Therefore, service Req_D_Write according to priority.

Then, at the time point (4) of Fig. 4A,

1) Req_A_read high, FIFO status is Half Full,

2) Req_E_write High, FIFO state is Half Empty.

Therefore, service Req_A_read according to priority.

After that, the FIFO state of Req_A_read becomes Full, so it is changed to the lowest priority.

Looking at the time (5) of FIG. 4A,

1) Req_C_read high, FIFO status is Half Full,

2) Req_E_write High, FIFO state is Half Empty.

Therefore, Req_C_read is serviced according to the priority, and Req_C_read is changed to the lowest priority because the FIFO state becomes Full.

Looking at the time (6) of FIG. 4A,

1) Req_B_read high, FIFO status is Half Full,

2) Req_D_write high, FIFO status is Full,

3) Req_E_write High, FIFO state is Half Empty.

In this case, the service should be given priority to the request with the light FIFO status of Full instead of the priority service. Therefore, Req_D_write is serviced first.

If the service is provided with priority, the data in the FIFO of Req_D_write cannot be written to the memory, and the data is broken by overwriting with new data.

Of course, when indicating the FIFO Full state, a free space of a certain amount of time that can be written to the memory is made in the FIFO. In the present invention, a pointer register is made to control the free space externally.

Looking at the time (7) of Fig. 4A,

1) Req_B_read high, FIFO status is Half Full,

2) Req_E_write High, FIFO state is Full.

Therefore, in this case as well, the service should be preferentially serviced with the request whose light FIFO status is Full, rather than the priority service as in (6). Therefore, Req_E_write is serviced first.

Next, as seen from the point (8) of FIG. 4A,

1) Req_A_read high, FIFO status is Full,

2) Req_B_read high, FIFO state is Half Full.

Therefore, the service should not be provided because the FIFO state of Req_A_read is Full. Service should be provided for Req_B_read.

After that, the FIFO state of Req_B_read is also Full.

Next, as seen from the point (9) of Fig. 4A,

1) Req_A_read / Req_C_read high, FIFO status is Full,

2) Req_E_write High, FIFO is Half Empty.

At this time, since the FIFO state of the read request is Full, it is the lowest priority. Therefore, you can service Req_E_write.

Next, as seen from the point of view (10) of FIG. 4A,

1) Req_A_read high, FIFO status is Half Full,

2) Req_C_read High, FIFO is Half Full.

Therefore, you can service Req_A_read because you can provide services according to priority.

Next, as seen from the point (11) of Fig. 4A,

1) Req_B_read high, FIFO status is Half Full,

2) Red_C_read High, FIFO is Half Full.

Therefore, service Req_B_read according to priority.

Next, at the time (12) of FIG. 4A,

1) Req_C_read high, FIFO status is Half Full,

2) Req_D_Write High, FIFO is Half Empty.

Therefore, you can service Req_C_read according to priority.

Next, as seen from (13) of FIG. 4A,

1) Req_D_write High, FIFO is Half Empty.

Therefore, it is necessary to provide a service for this.

Next, as viewed at (14) in FIG. 4A,

1) Req_C_read High, FIFO is Full.

At this time, only one request is made, but if the service is performed because the state of the FIFO is Full, the service in the FIFO is updated with new data, so the service cannot be performed.

Next, as viewed from (15) of Fig. 4a,

1) Req_C_read high, FIFO status is Full,

2) Req_D_write High, FIFO is Half Empty.

Therefore, the service cannot be provided because the state of the FIFO of Req_C_read is Full, and a service can be provided for Req_D_write.

The write_waiting_D and write_waiting_E signals synchronized with Req_D_write and Req_E_write of FIG. 4A will be described below.

Req_D_write or Req_E_write Once the data in the FIFO is full, it sends these signals to the function block so that no more data can be written to the FIFO. Once the FIFO is half empty, the data in the FIFO is kept in memory. To make it safe to use.

4b is a timing diagram of another embodiment showing a method of converting priority in an arbiter control unit according to the present invention. The criterion of service for a request is that a service of a request having an empty FIFO state is provided and all half empty or In the case of Half Full, this is a diagram explaining the priority service of a write request.

FIG. 4B is the same operation as that of FIG. 4A, and thus only a time point characterized by the above-described feature will be described.

First, as seen from the point (1) of FIG. 4B,

1) Req_C_read high, FIFO state is Empty,

2) Req_D_write high, FIFO state is Half Empty,

3) Req_E_write High, FIFO state is Half Empty.

Therefore, first, service the Req_C_read, which has no data in the FIFO.

Next, look at the point (3) of Fig. 4b,

1) Req_A_read high, FIFO status is Half Full,

2) Req_E_write High, FIFO state is Half Empty.

In this case, Req_D_write is serviced in order to give priority to the write request.

Looking at the time (7) of Fig. 4b,

1) Req_A_read high, FIFO status is Half Full,

2) Req_B_read high, FIFO state is Empty,

3) Req_E_write High, FIFO state is Half Empty.

Therefore, the FIFO must first service an empty request, so it provides a service to Req_B_read.

Thus, as shown in the two embodiments of Fig. 4a, 4b, by comparing the priority value of the request and the respective FIFO state to determine which one to serve first, simply by serving according to the priority value Solve the problem, and can effectively use the bandwidth of the memory.

Memory access arbitration method of the image processor according to the present invention as described above by changing the order of the service to the requests according to the FIFO state with a simple priority value, by distributing the crowded requests to serve more The bandwidth for the memory can be efficiently used, and the service of the priority value simply eliminates the service from being broken due to the low priority service being pushed to the request having the high priority value.

In addition, it can be applied to the development of HDTV chip that requires several functional blocks in one memory to change the priority value of each mode.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (4)

A memory for storing data necessary for image processing; A plurality of functional blocks for processing an image by reading / writing data stored in the memory according to a preset priority; A plurality of FIFOs for temporarily storing data read / written in the plurality of functional blocks; And an arbiter control unit for changing a priority order set in the plurality of functional blocks according to the amount of data stored in the plurality of FIFOs. The method of claim 1, The arbiter control unit divides each functional block into full, half full, half empty, and empty according to the amount of data. Memory access mediation device of the image processor. A first step of receiving a data request signal requested in each functional block and detecting a plurality of functional blocks requested; Transmitting a permission signal according to the requested data request signal to a FIFO control unit, receiving a quantity of data stored in each FIFO, and changing a priority of the plurality of FIFOs; A third step of storing data stored in a memory in a corresponding FIFO according to a changed priority of the plurality of FIFOs; And retrieving the amount of data stored in the FIFO, and transferring the data to the corresponding function block when the data is filled in the FIFO. A first step of storing data in a corresponding FIFO for data to be written to memory in each function block; A second step of transmitting a data write request signal and an amount of data stored in each FIFO when data is filled in a predetermined area of the FIFO; And changing a priority in accordance with the amount of data stored in each of the FIFOs, and storing the data in a memory according to the changed priority.