KR20020058364A - Router for Packet Dual Process - Google Patents

Abstract

PURPOSE: A router for dual packet processing is provided to prevent the performance of a system from being lowered by making a main processor process an error packet or a packet a network processor cannot process so that the network processor can smoothly process packets. CONSTITUTION: A router for dual packet processing is comprised of an Ethernet interface(11), a network processor(12), a switch interface(13), a transmitting queue buffer(14), a receiving queue buffer(15), a message pool memory(16), a routing table storage part(17), a main processor(18), and a bridge circuit(20). The Ethernet interface(11), interfacing an Ethernet, transfers the packets supplied from the Ethernet to the network processor(12). The network processor(12) executes forwarding for the packets inputted and output between the Ethernet interface(11) and the switch interface(13). The switch interface(13), interfacing a switch board, transfers the packets supplied from the network processor(12) to the switch board. The transmitting queue buffer(14) temporarily stores transmitting packets in case that the network processor(12) executes forwarding for the packets. The receiving queue buffer(15) temporarily stores received packets in case that the network processor(12) executes forwarding for the packets. The routing table storage part(17) provides routing information to the network processor(12) when the network processor(12) executes packet forwarding. The bridge circuit(20) enables the network processor(12) to access the message pool memory(16) and to store packets that the network processor(12) cannot process in the message pool memory(16). Also the bridge circuit(20) enables the main processor(18) to access the message pool memory(16) and to read the packets stored in the message pool memory(16).

Description

Router for Packet Dualization {Router for Packet Dual Process}

The present invention relates to a router. In particular, the present invention relates to a router in which a packet that cannot be processed by the network processor or an error-prone packet is received during forwarding of the received packet by the network processor. The present invention relates to a router for packet dualization processing that allows a network processor to process a corresponding received packet that cannot be received by the main processor, thereby preventing system performance degradation.

In general, a router performs a function of relaying a packet to another local area network (LAN), and forwards the received packet to relay to another LAN.

In a conventional router, a received packet is forwarded to a switch board by a network processor, and a packet that cannot be processed or an error occurs such as a packet having a variable length while the network processor is forwarding a received packet. Even in the case of receiving a received packet, the received packet is processed by the network processor, which makes it difficult to process the packet in the network processor, thereby degrading system performance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to receive a packet that cannot be processed by the network processor or receive an error-prone packet while forwarding the received packet by the network processor. In this case, it is possible to provide a router for packet dualization processing that enables the network processor to smoothly process packets by allowing the network processor to process a corresponding received packet that cannot be processed by the network processor.

1 is a block diagram of a router for packet dualization processing according to the present invention;

FIG. 2 is a diagram showing the configuration of the bridge circuit shown in FIG.

3 is a diagram illustrating timing of reading a packet stored in a message pool memory.

4 illustrates timing of storing packets in the message pool memory.

Explanation of symbols on the main parts of the drawings

11: Ethernet interface 12: network processor

13 switch interface 14 transmit queue buffer

15: Receive queue buffer 16: Message pool memory

17: routing table storage unit 18: the main processor

20: bridge circuit

A feature of the present invention for achieving the above object is a message pool memory for storing a packet; A main processor for reading and processing the packet stored in the message pool memory; And a bridge circuit for storing an unprocessed packet applied from a network processor for forwarding a packet to the message pool memory side and delivering the packet stored in the message pool memory to the main processor.

On the other hand, the bridge circuit includes: a bus arbiter for arbitrating use of a shared bus for accessing the message pool memory to the network processor and the main processor; A bus interface unit for matching the common bus; And a memory controller configured to control the storage / read operation of the packet with respect to the message pool memory to input and output packets between the bus interface unit and the message pool memory.

And, the main processor is characterized in that for managing the storage / reading of the packet to the message pool memory.

In addition, the network processor stores a packet in the message pool memory with permission from the main processor through a bridge circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The router for packet dualization processing according to the present invention includes an Ethernet interface 11, a network processor 12, a switch interface 13, a transmit queue buffer 14, a receive queue buffer 15, Message pool memory 16, routing table storage 17, main processor 18, and bridge circuit 20; The Ethernet interface 11 matches the Ethernet, delivers the packet applied from the Ethernet to the network processor 12, and delivers the packet applied from the network processor 12 to the Ethernet side. The network processor 12 performs a function of forwarding a packet input / output between the Ethernet interface 11 and the switch interface 13. The network processor 12 transmits a packet applied through the Ethernet interface 11 to the switch interface 13. The packet applied through the switch interface 13 is transmitted to the Ethernet interface 11 side. The switch interface 13 matches the switch board, transfers the packet applied from the network processor 12 to the switch board side, and delivers the packet applied from the switch board to the network processor 12 side. In addition, the transmission queue buffer 14 performs a function of temporarily storing the transmission packet when the network processor 12 forwards the packet, and the reception queue buffer 15 forwards the packet at the network processor 12. In this case, the function temporarily stores the received packet. The routing table storage unit 17 provides the routing information to the network processor 12 when the network processor 12 forwards the packet. The bridge circuit 20 is connected to the network processor 12 and the main processor 18 via a shared bus and directly to the message pool memory 16 to the network processor 12 and the main processor 18. It allows access to the message pool memory 16, which allows the network processor 12 to access the message pool memory 16 to store packets that it cannot process in the message pool memory 16, and to the main processor. In (18), the message pool memory 16 is accessed so that packets stored in the message pool memory 16 can be read.

In the router of the present invention as described above, when the network processor 12 receives a packet that cannot be processed by the network processor 12 or receives an errored packet while forwarding the packet, the router cannot process the received packet. When the packet is stored in the message pool memory 16 via the bridge circuit 20, the main processor 18 reads the packet stored in the message pool memory 16 and processes the packet. Facilitate forwarding functions.

Meanwhile, as shown in FIG. 2, the bridge circuit 20 includes a bus arbitration unit 21, a bus interface unit 22, and a memory control unit 23. The bus arbiter 21 transmits the bus use request to the main processor 18 when there is a request for use of the public bus from the network processor 12, and transmits a permission signal from the main processor 18 to the network processor 12. By forwarding to the side, the use of the shared bus is arbitrated to the network processor 12, and if there is no bus use request from the network processor 12, the main processor 18 uses the shared bus. The bus interface unit 22 matches the shared bus, transmits a signal for access to the message pool memory 16 applied through the shared bus to the memory controller 23, and transmits a packet transmitted and received on the shared bus. do. The memory control unit 23 controls the writing and reading of packets to the message pool memory 16 in accordance with a signal for accessing the message pool memory 16 applied from the common bus via the bus interface unit 22.

The operation of the router according to the present invention configured as described above will now be described with reference to the timing diagrams of FIGS. 3 and 4.

First, the network processor 12 receives a packet that cannot be processed by the network processor 12 or receives an error-produced packet while the network processor 12 performs a forwarding process for a packet transmitted and received between the Ethernet interface 11 and the switch interface 13. When received, the bus arbiter 21 requests the bus arbiter 21 of the bridge circuit 20 to use the shared bus in order to store the packet in the message pool memory 16. Is transmitted to the main processor 18, whereby the main processor 18 authorizes the bus arbiter 21 to permit the use of the shared bus, and the bus arbiter 21 supplies the network processor 12. ) To permit the use of the bus. In addition, the main processor 18 outputs various control signals for controlling access to the message pool memory 16 to the common bus. The low level chip select signal NPCS * is output as shown in FIG. In addition to applying to the common bus and applying the low level address strobe signal NPADS * and the low level write enable signal NPWE *, the network processor 12 transmits the address ADDR through the common bus. After applying to the memory control unit 23 via the bus interface unit 22, the main processor 18 transmits a low level preparation signal NPHOSTRDY * indicating the packet transmission through the common bus. ) Outputs a low level preparation signal NPDEVRDY * indicating that the packet is transmitted to the shared bus and transmits the packet data DATA to the bus interface 22 of the bridge circuit 20 to the memory controller 23.It is. Accordingly, the memory controller 23 receives the address ADDR and the packet data DATA from the network processor 12 and stores the packet in the message pool memory 16.

On the other hand, when there is no request to use a common bus from the network processor 12, the main processor 18 accesses the message pool memory 16 to process packets stored in the message pool memory 16. The operation is done as follows.

First, as shown in FIG. 3, the main processor 18 applies the low level burst signal NPHostburst * to the common bus, and also applies the low level chip select signal NPCS *, and simultaneously writes the same. After applying the enable signal NPWE * to the high level, applying the low-level address strobe signal NPADS * and applying the address ADDR to the common bus, the low-level signal indicating that the packet data is ready to be received. When the ready signal NPHOSTRDY * is applied, the packet data read from the message pool memory 16 by the memory control unit 23 of the bridge circuit 20 based on the address ADDR received through the bus interface unit 22. DATA is transmitted to the main processor 18 via the bus interface 22 and the common bus, and the network processor 12 transmits the low-level ready signal NPDEVRDY * at the transmission timing of the packet data DATA. Outputs

As described above, in the present invention, when the network processor 12 receives a packet that cannot be processed by the network processor 12 or receives an error packet while forwarding the packet, the received packet that cannot be processed can be processed. Is stored in the message pool memory 16 via the bridge circuit 20, the main processor 18 reads and processes the packets stored in the message pool memory 16, thereby inherently forwarding in the network processor 12. It makes the function smooth.

As described above, according to the present invention, when a received packet is forwarded by a network processor, a packet that cannot be processed by the network processor is received or a corresponding reception that cannot be processed by the network processor when an error packet is received. The packet is processed by the main processor, which allows the network processor to handle packet forwarding smoothly, thus preventing system performance degradation.

Claims (4)

A message pool memory for storing packets; A main processor for reading and processing the packet stored in the message pool memory; And further comprising a bridge circuit for storing an unprocessed packet applied from a network processor for forwarding the packet to the message pool memory side, and transferring the packet stored in the message pool memory to the main processor. Router for processing. 2. The system of claim 1, wherein the bridge circuit further comprises: a bus arbiter for arbitrating use of a shared bus for accessing the message pool memory to the network processor and the main processor; A bus interface unit for matching the common bus; And a memory controller configured to control the storage / read operation of the packet with respect to the message pool memory to input and output the packet between the bus interface unit and the message pool memory. 2. The router of claim 1, wherein the main processor manages storage / reading of packets to and from message pool memory. 2. The router of claim 1, wherein the network processor stores a packet in the message pool memory with permission from the main processor through a bridge circuit.