KR20020002574A - Method for forming contact plug in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact plug of a semiconductor device is provided to increase polishing uniformity of a chemical mechanical polishing(CMP) process of the second interlayer dielectric by separating the second contact plug by an etch-back process before the second interlayer dielectric is formed, and to reduce the thickness of an oxide layer evaporated as a bitline hard mask by guaranteeing a process margin of a CMP process of the second interlayer dielectric and a subsequent diffusion barrier layer. CONSTITUTION: The first contact plug(39) is formed on a semiconductor substrate(31). A plurality of bitlines of a stacked structure including a hard mask layer are formed on the first contact plug. Polysilicon for a plug is evaporated on the resultant structure, and is selectively patterned to be filled between the bitlines and to be protruded. The patterned polysilicon for the plug is etched back to the upper portion of the bitline to form the second contact plug(41a). An interlayer dielectric is formed on the second contact plug, and is chemically and mechanically polished to the upper portion of the second contact plug by using ceria-based slurry having high polishing selectivity of the second contact plug to the interlayer dielectric.

Description

Method for forming contact plug of semiconductor device {METHOD FOR FORMING CONTACT PLUG IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of separating a device to form a contact plug and forming a subsequent metal diffusion barrier film.

Hereinafter, a method of forming a contact plug and a storage node according to the related art will be described with reference to FIGS. 1 and 2A to 2F.

FIG. 1 is a layout diagram illustrating a semiconductor device formed according to the prior art, in which a word line pattern 16 and a bit line pattern 21 are formed to cross each other, and the first line between the word line patterns 16 is formed. A second contact plug 22a is formed on the contact plug (not shown). Here, the second interlayer insulating film 23 is deposited on the plug polysilicon deposited between the bit line patterns 21, and then the second polylayer insulating film 23 is chemically mechanically polished to form the plug polysilicon. To form a second contact plug 22a. At this time, when the second contact plug 22a is formed, the voids 24 generated when the second interlayer insulating layer 23 is deposited are exposed, so that parasitic capacitance is increased when forming the subsequent storage node.

FIG. 2 is a cross-sectional view of the semiconductor device taken along line AA ′ of FIG. 1, and illustrates a step before performing a chemical mechanical polishing process of the second interlayer insulating film, and FIGS. 3A to 3B are B-B of FIG. 1. 4 is a cross-sectional view of the semiconductor device taken along the line C-C of FIG. 1.

As shown in FIG. 2, after the device isolation film (not shown) is formed on the semiconductor substrate 11, the gate oxide film 12, the polysilicon 13, and the tungsten silicide 14 are disposed on the semiconductor substrate 11. After the deposition of the mask oxide layer 15, the mask oxide layer 15, the tungsten silicide 14, the polysilicon 13, and the gate oxide layer 12 are etched to form a word line pattern 16. Subsequently, an oxide film for sidewalls is deposited on the entire surface including the wordline pattern 16 and then etched to form sidewall spacers 17 which are in contact with the sidewall of the wordline pattern 16. Next, the source / drain regions 18 are formed by implanting impurity ions using the word line pattern 16 and the sidewall spacers 17 as masks.

Subsequently, a first interlayer insulating layer 19 is deposited on the entire surface including the word line pattern 16. Then, the first interlayer insulating layer is selectively etched to form a contact hole, and the contact hole is embedded in the source / drain. A first contact plug 20 is formed which is connected to the region 18.

Subsequently, a bit line pattern 21 is formed to be electrically connected to the source / drain region 18 through the first contact plug 20, and the bit line pattern 21 may be formed of the word line pattern 16. The bit line pattern 21 has a stacked structure of Ti / TiN 21a, tungsten 21b, and an oxide film 21c for hard mask, and sidewall spacers 21d are formed on the side surfaces thereof. do.

Subsequently, after the bit line pattern 21 is formed, the second plug polysilicon 22 is deposited on the entire surface, and then only the portion where the contact plug is to be formed is patterned, and then the second plug polysilicon 22 is included. A high density plasma oxide film is formed on the entire surface as the second interlayer insulating film 23.

Here, reference numeral 24 denotes a polishing target for chemical mechanical polishing of the second interlayer dielectric layer 23 for separating the second plug polysilicon 22, and when the second interlayer dielectric layer 23 is deposited. A void 25 is generated between the bit line patterns 21, and when the chemical mechanical polishing process is performed on the polishing target 24, the void 25 is exposed.

As shown in FIG. 3A, the second plug polysilicon 22 deposited between the bit line patterns 21 is deposited to sufficiently cover the bit line pattern 21 and the polysilicon for the second plug. Reference numeral 22 is selectively patterned to protrude above the bit line pattern 21 and to bury the gap therebetween.

As shown in FIG. 3B, the second interlayer insulating film 23 is chemically polished to the polishing target 24 using an oxide film slurry to form a second contact plug 22a. Subsequently, Ti / TiN is deposited on the entire surface including the second contact plug 22a as the metal diffusion barrier 26 for the storage node. In this case, reference numeral 27 denotes a polishing target of the metal diffusion barrier 26.

As shown in FIG. 4A, when the high density plasma oxide film is deposited as the second interlayer insulating film 23 on the second plug polysilicon 22, the bit line pattern 21 may be formed due to the deposition characteristics of the high density plasma oxide film. Void 25 is formed between the ().

As shown in FIG. 4B, the second interlayer insulating film 23 is chemically mechanically polished by a polishing target '24' to form a second contact plug 22a (FIG. 3B), but the second interlayer insulating film ( 23) The voids 25 generated during deposition are exposed. Subsequently, the metal diffusion barrier layer 26 for the storage node is deposited on the entire surface including the exposed void 25.

However, the prior art as described above is the first deposited between the bit line pattern 21 due to the deposition characteristics of the high density plasma oxide film used as the second interlayer insulating film 23 and the etching profile characteristics of the second contact plug 22a. The voids 25 are generated in the two interlayer insulating film 23. When the position of the void 25 is present above the polishing target 24 of the chemical mechanical polishing process of the second interlayer insulating film 23 to proceed for the separation of the subsequent contact plug, the second interlayer insulating film 23 After chemical mechanical polishing, the voids 25 are exposed to the surface. As a result, the metal diffusion barrier 26 is filled in the voids 25 during the subsequent recess process of the second contact plug polysilicon 22 and the deposition of the metal diffusion barrier, and the metal diffusion barrier ( 26) has a problem in that an operation error of the device is generated as a bridge between the storage nodes is formed when forming a subsequent storage node (SN).

In addition, the second contact plug 22a is separated by performing a chemical mechanical polishing process of the second interlayer insulating film 23 using an oxide film slurry, and the second interlayer insulating film 23 is chemically mechanically used using the oxide film slurry. When polishing, there is almost no polishing selection ratio of oxide rod polysilicon, so there is no polishing stop film of chemical mechanical polishing process, so it is very difficult to determine the end point of polishing, which reduces the margin of chemical mechanical polishing process and increases the loss of oxide film for hard mask. There is a problem.

The present invention has been made to solve the above problems of the prior art, a semiconductor suitable for securing the process margin of the chemical mechanical polishing process for separating contact plugs, and to reduce the parasitic capacitance due to the void of the interlayer insulating film between the bit line Its purpose is to provide a method for manufacturing a device.

1 is a plan view showing a method of manufacturing a semiconductor device according to the prior art,

FIG. 2 is a cross-sectional view of the semiconductor device taken along line AA ′ of FIG. 1;

3A through 3B are cross-sectional views of a semiconductor device taken along line BB ′ of FIG. 1;

4A through 4B are cross-sectional views of a semiconductor device taken along line CC ′ in FIG. 1;

5A through 5D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

6A to 6C are cross-sectional views illustrating a manufacturing process of a semiconductor device taken along line I-I of FIG. 5C;

* Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 37: source / drain region

38: first interlayer insulating film 39: first contact plug

40a: Ti / TiN 40b: tungsten

40c: Oxide film for hard mask 41: Polysilicon for second contact plug

41a: second contact plug 42: second interlayer insulating film

A semiconductor device manufacturing method of the present invention for achieving the above object comprises a first step of forming a first contact plug on a semiconductor substrate having a predetermined process; Forming a plurality of bit lines of a stacked structure including a hard mask layer on the first contact plugs; A third step of depositing polysilicon for plug on the resultant of the second step and selectively patterning the polysilicon for plug so as to be embedded and projected between the bit lines; A fourth step of forming a second contact plug separated from each other by front-etching back the patterned plug polysilicon to an upper portion of the bit line; And forming an interlayer insulating film on the second contact plug, and then chemically mechanically polishing the interlayer insulating film to an upper portion of the second contact plug by using a ceria-based slurry having a high polishing selectivity of the second contact plug. It is characterized by comprising a fifth step.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

The present invention is a method of mixing and applying a chemical mechanical polishing process and an etch back process of polysilicon to separate a contact plug. The process of separating a contact plug without a polishing stop film having a polishing selectivity such as a nitride film at the bottom should be performed. Applicable if

5A to 5D illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention, which illustrates a method of forming a second contact plug on a first contact plug between word lines.

As shown in FIG. 5A, after the device isolation layer (not shown) is formed on the semiconductor substrate 31, the gate oxide layer 32, the polysilicon 33, and the tungsten silicide 34 are disposed on the semiconductor substrate 31. After sequentially depositing the mask oxide layer 35, the mask oxide layer 35, the tungsten silicide 34, the polysilicon 33, and the gate oxide layer 32 are etched to form a word line pattern. Subsequently, an oxide film for sidewalls is deposited on the entire surface including the wordline patterns, and then etched to form sidewall spacers 36 in contact with the sidewalls of the wordline patterns. Next, the source / drain regions 37 are formed by implanting impurity ions using the word line pattern and the sidewall spacers as masks.

Subsequently, a first interlayer insulating layer 38 is deposited on the entire surface including the word line pattern, and then the first interlayer insulating layer 38 is selectively etched to form a plug contact hole, and the plug is buried in the contact hole. The first contact plug 39 connected to the / drain region 37 is formed.

6A, a bit line pattern electrically connected to the source / drain region 37 is formed through the first contact plug 39, and the bit line pattern is perpendicular to the word line pattern. The bit line pattern has a stacked structure of Ti / TiN 40a, tungsten 40b, and an oxide film 40c for hard mask, and sidewall spacers 40d are formed on the side surfaces thereof.

Subsequently, after the bit line pattern including the sidewall spacers 40d is formed, the second contact plug polysilicon 41 is deposited on the entire surface, and then only the portion where the second contact plug is to be formed is patterned, but between the bit line patterns. Is patterned into a shape that sufficiently covers and protrudes above it.

As shown in FIG. 5B, a blanket etchback process is used on the front surface, that is, polysilicon for the second contact plug protruding to the upper portion of the bit line pattern using '43' of FIG. 5A as an etching target. Only the 41 is removed to form the second contact plugs 41a separated from each other. In this case, the etching recipe for removing the polysilicon may include a selectivity ratio of 10: 1 to 15: 1 to the hard mask oxide layer 40c of the bit line pattern. The loss of the hard mask oxide film 40c is minimized.

Subsequently, a high density plasma oxide film is deposited on the entire structure of the second interlayer insulating film 42.

As shown in FIG. 5C, the polishing process of the second interlayer insulating layer 42 is performed until the surface of the second contact plug 41a is exposed, and the upper portion of the second contact plug 41a is removed during the polishing process. The second interlayer insulating film 42 is polished using the polishing target 43 (42a). At this time, when the second interlayer insulating film 42 is deposited, since the polysilicon existing on the hard mask oxide film 40c of the bit line pattern is removed, the deposition thickness of the second interlayer insulating film 42 is reduced. To prevent the formation of voids and to reduce the burden of subsequent chemical mechanical polishing processes.

The polishing contact ratio of the second contact plug 41a to the second interlayer insulating film 42 is stopped by using a ceria-based slurry having a polishing selectivity of 100: 1 or more for the second contact plug 41a. By using it as a film, the process margin of a polishing process is ensured and the dishing of the 2nd contact plug 41a which exists at the time of the grinding | polishing of the 2nd interlayer insulation film 42 is prevented from occurring. Reference numeral 42a denotes a polished second interlayer insulating film.

As shown in FIG. 5D, the second contact plug 41a between the bit line patterns is recessed back to a predetermined depth to form a portion where a subsequent diffusion barrier layer is to be formed on the second contact plug 41a. Remove it. At this time, the etching contact back of the second contact plug 41a is performed using an etching gas having a sufficient selectivity of 10: 1 or more with respect to the hard mask oxide film 40c and the second interlayer insulating film 42a. do.

Subsequently, a metal layer is deposited as a diffusion barrier on the recessed second contact plug 41a and then chemically mechanically polished to separate the diffusion barrier 44.

6A to 6C illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention, which illustrates a method of forming a second contact plug between bit lines along the line II ′ of FIG. 5D.

As shown in FIG. 6A, after forming a word line pattern, a first interlayer insulating film 38 is formed on the entire surface including the word line pattern. Subsequently, the first interlayer insulating layer 38 is selectively etched to form a contact hole, and then a first contact plug 39 is buried in the contact hole to contact the source / drain region 37. Subsequently, a bit line pattern having a stacked structure of Ti / TiN 40a, tungsten 40b, and an oxide film 40c for hard mask on the first contact plug 39, and having sidewall spacers 40d connected to the side surfaces thereof. To form.

Subsequently, after the bit line pattern is formed, the second contact plug polysilicon 41 is deposited on the entire surface, and then only the portion where the second contact plug is to be formed is patterned, but covers sufficiently between the bit line patterns and protrudes therefrom. Patterned to the shape that becomes.

As shown in FIG. 6B, a blanket etch back process is performed on the entire surface of the hard mask oxide film 40c to the upper portion 43 so as to remove only polysilicon protruding from the upper portion of the bit line pattern, thereby separating the second silicon. The contact plug 41a is formed. In this case, the etching recipe for removing the polysilicon may include an oxide film for hard mask back etching using an etching gas having a selectivity of 10: 1 or more to the hard mask oxide film 40c of the bit line pattern. Minimize the loss of 40c.

Subsequently, a high density plasma oxide film is deposited on the entire structure of the second interlayer insulating film 42.

As shown in FIG. 6C, the chemical mechanical polishing process of the second interlayer dielectric layer 42 is performed until the surface of the second contact plug 41a is exposed, and the second interlayer dielectric layer 42 is polished during the polishing process. And the second interlayer insulating film 42 using the ceria-based slurry having the polishing selectivity of the second contact plug 41a of 100: 1 or more as the polishing target 43 as the upper surface of the second contact plug 41a. Polish At this time, when the second interlayer insulating film 42 is deposited, since the polysilicon existing on the hard mask oxide film 40c of the bit line pattern is removed, the deposition thickness of the second interlayer insulating film 42 is reduced. To prevent the formation of voids and to reduce the burden of subsequent chemical mechanical polishing processes.

The polishing contact ratio of the second contact plug 41a to the second interlayer insulating film 42 is stopped by using a ceria-based slurry having a polishing selectivity of 100: 1 or more for the second contact plug 41a. By using it as a film, the process margin of a polishing process is ensured and the dishing of the 2nd contact plug 41a which exists at the time of the grinding | polishing of the 2nd interlayer insulation film 42 is prevented from occurring.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The above-described method for manufacturing a semiconductor device of the present invention can improve the polishing uniformity of the subsequent chemical mechanical polishing process of the second interlayer insulating film by separating the second contact plug by the front etch back process before forming the second interlayer insulating film. Therefore, the thickness of the oxide layer deposited on the hard mask of the bit line can be reduced by securing the process margin of the chemical mechanical polishing process of the second interlayer dielectric layer and the subsequent diffusion barrier layer.

In addition, by reducing the deposition thickness of the oxide film for the hard mask to reduce the void generated during the deposition of the second interlayer insulating film, it is possible to prevent the bridge between the subsequent capacitors to improve the electrical characteristics of the device.

Claims (6)

In the manufacturing method of a semiconductor device, A first step of forming a first contact plug on a semiconductor substrate on which a predetermined process is completed; Forming a plurality of bit lines of a stacked structure including a hard mask layer on the first contact plugs; A third step of depositing polysilicon for plug on the resultant of the second step and selectively patterning the polysilicon for plug so as to be embedded and projected between the bit lines; A fourth step of forming a second contact plug separated from each other by front-etching back the patterned plug polysilicon to an upper portion of the bit line; And After the interlayer insulating film is formed on the second contact plug, the interlayer insulating film is chemically mechanically polished to the upper portion of the second contact plug by using a ceria-based slurry having a large polishing selectivity of the second contact plug. 5th step Method for manufacturing a semiconductor device comprising the. The method of claim 1, The fourth step, A method of manufacturing a semiconductor device, characterized in that the selectivity of the bit line with respect to the hard mask layer is achieved by using an etching gas with sufficient amount. The method of claim 1, After the fifth step, And recess-etching back the second contact plug by a predetermined depth for the subsequent diffusion barrier layer. The method of claim 3, wherein The recess etch back of the second contact plug is made of a slurry having a polishing selectivity of 10: 1 to 15: 1 between the interlayer insulating film and the plug polysilicon. The method of claim 1, The interlayer insulating film is a semiconductor device manufacturing method, characterized in that using a high density plasma oxide film. The method of claim 1, And the bit line comprises a spacer connected to a sidewall of a stacked structure of an oxide film for Ti / TiN, tungsten and a hard mask.