KR20010109645A - Clock control buffer circuit of rambus dram - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control buffer circuit for a Rambus DRAM, comprising: memory means comprising a memory top region portion and a memory bottom region portion, and pipeline top region means and pipes for selectively operating the memory top region portion and the memory bottom region portion, respectively. Inputting the first clock signal toggled by a line bottom area means, a signal for controlling to output data stored in the memory means to the outside during a read command, and write data input externally during the write command to the memory means. A delay lock loop means for generating a second clock signal toggled by a control signal, and a bank selection signal and a data output for selecting a top or bottom bank, the first clock signal and the second clock signal being input; Access to top or bottom bank selected by signal to stabilize shift And a control signal generating means for outputting a signal for controlling only a desired clock path to be operated to the pipeline top region means and the pipeline bottom region means, so that only a clock path of an access portion of the top or bottom bank is accessed. Operation reduces power consumption and reduces the RC load by varying the clock path for each part, thereby reducing the driver size of the output stage.

Description

CLOCK CONTROL BUFFER CIRCUIT OF RAMBUS DRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control buffer circuit of a Rambus DRAM. In particular, only a clock path of an access portion of a top or bottom bank is operated. The present invention relates to a clock control buffer circuit of Rambus DRAM which reduces power consumption and reduces the RC load by changing the clock path for each part.

In general, a rambus DRAM is a packet-driven memory device that transmits a packet-type data and control signal, and a plurality of rambus DRAMs are connected on a rambus channel. Each of these Rambus DRAMs is controlled by one Rambus memory controller through the Rambus channel. Rambus DRAM is largely divided into DRAM core area, Rambus Interface logic area, Delay Locked Loop (DLL) and analog area of power supply.

In Rambus DRAM, the DRAM core must go through the Rambus channel interface (a protocol machine) to communicate data with external devices. Therefore, interface logic is needed to connect the DRAM core to the Rambus channel interface. The interface logic generates various signals for controlling the DRAM core, has an address line input from outside, and exchanges data with external devices via a data bus.

1 is a block diagram of a sclk and tclk path circuit according to the prior art, which includes an I standard region portion 2, a C custom region portion 3, a C pipeline top region portion 5, and a C pipeline bottom region portion ( 6) a memory top region portion 7 and a memory bottom region portion 8; The C custom region portion 3 includes a DLL circuit portion 1, a sclk, and a tclk buffer portion 4.

The C custom area unit 3 includes circuits such as a bonding pad, a data output buffer, a data input buffer, a control output buffer, a control input buffer, a DLL, a clock driver, and a current control logic circuit. It consists.

The I standard area section 2 includes state machine logic, timing control, registers, and the like.

Here, the tclk signal is a clock signal for externally outputting internal read data when a read command is applied, and the sclk signal is a clock signal for internally inputting write data input externally when a write command is applied.

As shown in FIG. 1, the conventional clock control buffer circuit buffers the etclk and esclk signals generated by the DLL circuit unit 1 in the tclk and sclk buffer units 4 so as to buffer the C custom region unit 3 and the C pipeline. It is comprised so that it may be used together as the clock signal of the top region part 5 and the C pipeline bottom region part 6. As shown in FIG.

FIG. 2 is a circuit diagram of the tclk and sclk buffer units 4 used in the conventional clock control buffer circuit, and the tclk and sclk signals buffered by inputting the etclk and esclk signals generated by the DLL circuit unit 1, respectively. It consists of two INV circuits connected in series for output.

However, in the conventional rambus DRAM clock control buffer circuit configured as described above, the C custom region portion 3 and the C pipeline top that commonly input the tclk and sclk signals, which are output signals of the tclk and sclk buffer portions 4, are used. Many elements inside the region 5 and the C pipeline bottom region 6 are connected together with the clock signal clk, causing a significant RC load. Since the tclk and sclk signals operate together at the top region 5 and the C pipeline bottom region 6, power consumption is unnecessary.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to reduce power consumption by operating only a clock path of an access part of a top or bottom bank, The purpose is to provide a clock control buffer circuit of Rambus DRAM that reduces the RC load and reduces the driver size of the output stage by changing the clock path for each part.

1 is a block diagram showing a tclk, sclk path of the Rambus DRAM according to the prior art

FIG. 2 is a circuit diagram illustrating a tclk and sclk buffer unit shown in FIG. 1.

3 is a block diagram illustrating a clock control buffer circuit and a tclk and sclk path of a Rambus DRAM according to the present invention.

4 is a circuit diagram of a sclk control buffer unit used in the present invention.

5A to 5B are waveform diagrams of the sclk control buffer unit used in the present invention.

6 is a circuit diagram of a tclk control buffer unit used in the present invention.

7A to 7E are waveform diagrams of the tclk control buffer unit used in the present invention.

8 is another circuit diagram of a tclk control buffer unit used in the present invention.

Explanation of symbols on the main parts of the drawings

1: DLL circuit part 2: I standard area part

3: C custom area part 4, 14: tclk, sclk control buffer part

5: C pipeline top region portion 6: C pipeline bottom region portion

7: memory top region portion 8: memory bottom region portion

In order to achieve the above object, the clock control buffer circuit of the Rambus DRAM of the present invention,

Memory means comprising a memory top region portion and a memory bottom region portion;

Pipeline top region means and pipeline bottom region means for selectively operating the memory top region portion and the memory bottom region portion, respectively;

Toggle by a first clock signal toggled by a signal that controls to output data stored in the memory means to the outside during a read command, and by a signal that controls input of externally written write data to the memory means during a write command. Delay lock loop means for generating a second ringed clock signal, respectively;

The first clock signal and the second clock signal are input to control only a clock path to access the top or bottom bank selected by a bank selection signal for selecting a top or bottom bank and a signal for stabilizing a data output shift unit. And control signal generating means for outputting a signal to the pipeline top region means and the pipeline bottom region means, respectively.

According to an embodiment of the present invention, the control signal generating means applies the second clock signal to the selected top bank when the bank selection signal selects the top bank during the write operation, and the bank selection signal selects the bottom bank. And logic to apply the second clock signal to the selected bottom bank.

The control signal generating means applies the first clock signal to the selected top bank when the bank selection signal selects the top bank during the read operation, and when the bank selection signal selects the bottom bank to the selected bottom bank. And logic configured to apply the first clock signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

3 is a block diagram of the sclk and tclk path circuits according to the present invention, which includes an I standard region portion 2, a C custom region portion 3, a C pipeline top region portion 5, and a C pipeline bottom region portion ( 6), a memory top region portion 7 and a memory bottom region portion 8 are provided. The C custom region unit 3 includes a DLL circuit unit 1, a sclk and a tclk control buffer unit 14.

The sclk and tclk control buffers 14 are esclk signals toggled by the sclk enable signal and etclk signals toggled by the tclk enable signal and the C custom region unit 3 by the DLL circuit unit 1. Inputs the signal CB <4> for selecting the top or bottom bank and the 'tclk_src_b' signal from the I standard region unit 2 so as to operate only the corresponding clock path according to the top or bottom bank. The controlling 'tclk_top' signal and the 'sclk_top' signal are output to the C pipeline top region 5 and the C pipeline bottom region 6, respectively.

The present invention is composed of the tclk and the sclk control buffer unit 14 instead of the tclk and the sclk buffer unit 4 of the existing tclk and the sclk path (FIG. 1), and the configuration of the tclk and sclk control buffer unit 14 is as follows. 4, 6, and 8 to be described in the configuration.

First, FIG. 4 is a circuit diagram of the sclk control buffer unit of the tclk and sclk control buffer unit 14 shown in FIG. 3. The first circuit outputs a NAND operation signal by inputting a CB <4> signal and an esclk signal. NOR operation was performed by inputting the NAND gate NA1, the fifth inverter INV5 which inverts the output signal of the first NAND gate NA1 to output the sclk_top signal, and the CB <4> signal and the esclk signal as inputs. A first NOR gate NR1 for outputting a signal, a sixth inverter INV6 for outputting a sclk_bot signal by inverting an output signal of the first NOR gate NR1, and a delay after a predetermined time by inputting the esclk signal and the seventh and eighth inverters INV7 and INV8 connected in series for outputting a sclk signal.

Next, the operation of the present invention will be described with the sclk signal and the tclk signal with reference to FIGS. 5A to 5E.

As shown in Fig. 5A, the esclk signal is toggled by the sclk enable signal in the DLL circuit unit 1, and a signal for selecting the top or bottom bank in the portion (a) of the rclk signal (hereinafter, 'CB <4'). > Signal ') is latched.

If the CB <4> signal is 'high' as the top bank selection command, only sclk_top receives esclk. If the CB <4> is 'low' as the bottom bank selection command, only sclk_bot operates in synchronization with esclk.

5B illustrates the case where the top bank is continuously selected (CB <4> signal = 'high' state), and FIG. 5C illustrates the case where the bottom bank is continuously selected (CB <4> signal = 'low' state). FIG. 5D illustrates a case in which the signal is changed from the bottom to the top (the CB <4> signal is transitioned from the 'low' state to the 'high' state), and FIG. 5E illustrates the case in which the signal is changed from the top to the bottom (CB <4> The state transitioned from the "high" state to the "low" state.

FIG. 6 shows a circuit diagram of the tclk control buffer unit of the tclk and sclk control buffer unit 14 shown in FIG. 3.

As shown in the drawing, the tclk control buffer unit outputs a NAND operation signal by inputting a ninth inverter INV9 for inverting the CB <4> signal, an output signal of the ninth inverter INV9, and a tclk_src_b signal. A second NAND gate NA2, a third NAND gate NA3 for outputting a NAND operation signal by inputting the output signal of the second NAND gate NA2 and the etclk signal, and the CB <4> signal; A fourth NAND gate NA4 for outputting a NAND operation signal by inputting the tclk_src_b signal, and an output signal for NAND operation by outputting the output signal of the fourth NAND gate NA4 and the etclk signal as an input; 5th NAND gate NA5, the 10th inverter INV10 which inverts the output signal of the 3rd NAND gate NA3, and outputs the tclk_top signal, and the tclk_bot by inverting the output signal of the 5th NAND gate NA5 An eleventh inverter INV11 for outputting a signal, and the e It is composed of serially connected twelfth and thirteenth inverters INV12 and INV13 which input a tclk signal and output a tclk signal after a predetermined time delay.

The tclk signal is enabled as 'low' when the CB <4> signal selecting the top or bottom bank and the device ID match. During this period, the C pipeline top region 5 and the C pipeline bottom region portion ( Using the 'tclk_src_b' signal to stabilize the data output shift block inside 6), only the tclk path of the part to be accessed is operated.

When the device ID is matched, the 'tclk_src_b' signal enabled as 'low' should operate tclk_top and tclk_bot between (a) and (c) of the rclk signals of FIGS. 7A to 7E regardless of the CB <4> signal. After latching the CB <4> signal in (b) of the rclk signal, 'tclk_top' depending on whether the CB <4> signal is 'high' or 'low' after the period (c) in which the 'tclk_src_b' signal is disabled. Toggles only the signal or the 'tclk_bot' signal in synchronization with the etclk signal.

8 shows another circuit diagram of the tclk control buffer unit of the tclk and sclk control buffer unit 14 shown in FIG. It is used.

As shown in the drawing, the tclk control buffer unit outputs a second NOR gate NR2 for outputting a NOR operation by inputting a CB <4> signal and a tclk_src signal, and an output signal of the second NOR gate NR2. A sixteenth inverter INV14 for inverting and outputting the sixth NAND gate NA6 for outputting a NAND operation signal by inputting the output signal of the fourteenth inverter INV14 and the etclk signal, and the CB <4>; A seventh NAND gate NA7 for outputting a NAND operation signal by inputting an output signal of the sixteenth inverter INV16 that inverts the signal and the tclk_src signal and outputs the output signal of the seventh NAND gate NA7; And an eighth NAND gate NA8 for outputting a NAND operation signal by inputting the etclk signal, and a fifteenth inverter INV15 for outputting a tclk_top signal by inverting an output signal of the sixth NAND gate NA6; Half the output signal of the eighth NAND gate NA8; And a seventeenth inverter (INV17) for transmitting the tclk_bot signal and a series connected eighteenth and nineteenth inverters (INV18, INV19) for inputting the etclk signal and outputting the tclk signal after a predetermined time delay.

As described above, according to the clock control buffer circuit of the Rambus DRAM according to the present invention, the size of the driver stage is reduced by reducing the RC load by changing the clock path for each block, and only the corresponding clock path operates according to the top or bottom bank. This minimizes power consumption.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (6)

For Rambus DRAM, Memory means comprising a memory top region portion and a memory bottom region portion; Pipeline top region means and pipeline bottom region means for selectively operating the memory top region portion and the memory bottom region portion, respectively; Toggle by a first clock signal toggled by a signal that controls to output data stored in the memory means to the outside during a read command, and by a signal that controls input of externally written write data to the memory means during a write command. Delay lock loop means for generating a second ringed clock signal, respectively; The first clock signal and the second clock signal are input to control only a clock path to access the top or bottom bank selected by a bank selection signal for selecting a top or bottom bank and a signal for stabilizing a data output shift unit. And a control signal generating means for outputting a signal to said pipeline top region means and said pipeline bottom region means, respectively. The method of claim 1, The control signal generating means, In the write operation, when the bank selection signal selects the top bank, the second clock signal is applied to the selected top bank, and when the bank selection signal selects the bottom bank, the second clock signal is applied to the selected bottom bank. The clock control buffer circuit of Rambus DRAM, characterized in that the logic configuration. The method of claim 2, The control signal generating means, A first NAND gate NA1 for outputting a NAND operation signal by inputting a CB <4> signal and an esclk signal, and a fifth inverter for inverting an output signal of the first NAND gate NA1 to output a sclk_top signal (INV5), the first NOR gate NR1 for outputting the NOR operation signal by inputting the CB <4> signal and the esclk signal, and the sclk_bot signal by inverting the output signal of the first NOR gate NR1. The sixth inverter (INV6) for outputting the clock of Rambus DRAM, characterized in that consisting of the seventh and eighth inverters (INV7, INV8) connected in series to output the sclk signal after a predetermined time delay by inputting the esclk signal Control buffer circuit. The method of claim 1, The control signal generating means, During the read operation, when the bank selection signal selects the top bank, the first clock signal is applied to the selected top bank, and when the bank selection signal selects the bottom bank, the first clock signal is applied to the selected bottom bank. The clock control buffer circuit of Rambus DRAM, characterized in that the logic configuration. The method of claim 4, wherein The control signal generating means, A ninth inverter INV9 for inverting the CB <4> signal, a second NAND gate NA2 for outputting a NAND operation signal by inputting the output signal of the ninth inverter INV9 and the tclk_src_b signal, and the A third NAND gate NA3 for outputting a NAND calculation signal by inputting the output signal of the second NAND gate NA2 and the etclk signal, and the CB <4> signal and the tclk_src_b signal as inputs. A fourth NAND gate NA4 for outputting a signal; a fifth NAND gate NA5 for outputting a signal obtained by NAND operation with the output signal of the fourth NAND gate NA4 and the etclk signal as input; A tenth inverter INV10 that inverts the output signal of the NAND gate NA3 to output the tclk_top signal, and an eleventh inverter INV11 that outputs the tclk_bot signal by inverting the output signal of the fifth NAND gate NA5. Tclk after a certain time delay by inputting the etclk signal. A clock control buffer circuit for a Rambus DRAM, comprising: a twelfth and thirteenth inverters INV12 and INV13 connected in series for outputting a signal. The method of claim 4, wherein The control signal generating means, A second NOR gate NR2 for outputting a NOR operation signal by inputting a CB <4> signal and a tclk_src signal, and a fourteenth inverter INV14 for inverting and outputting an output signal of the second NOR gate NR2. And a sixth NAND gate NA6 for outputting a NAND operation signal by inputting the output signal of the fourteenth inverter INV14 and the etclk signal, and inverting and outputting the CB <4> signal and the tclk_src signal. A seventh NAND gate NA7 for outputting a NAND operation signal by inputting the output signal of the sixteenth inverter INV16, an output signal of the seventh NAND gate NA7, and the etclk signal as inputs; Of the eighth NAND gate NA8 for outputting one signal, the fifteenth inverter INV15 for inverting the output signal of the sixth NAND gate NA6, and outputting the tclk_top signal, and the eighth NAND gate NA8. 17th inverter for inverting output signal to output tclk_bot signal And an INV17 and serially connected eighteenth and nineteenth inverters (INV18 and INV19) for inputting the etclk signal and outputting a tclk signal after a predetermined time delay.