KR20010109621A - Method for forming metal wire of semiconductor device - Google Patents
Method for forming metal wire of semiconductor device Download PDFInfo
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- KR20010109621A KR20010109621A KR1020000029684A KR20000029684A KR20010109621A KR 20010109621 A KR20010109621 A KR 20010109621A KR 1020000029684 A KR1020000029684 A KR 1020000029684A KR 20000029684 A KR20000029684 A KR 20000029684A KR 20010109621 A KR20010109621 A KR 20010109621A
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- film
- semiconductor device
- metal
- lower metal
- dielectric film
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- 239000002184 metal Substances 0.000 title claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 229920000642 polymer Polymers 0.000 claims abstract description 28
- 239000007789 gas Substances 0.000 claims abstract description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000004544 sputter deposition Methods 0.000 claims abstract description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 9
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- 229910052786 argon Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 abstract description 9
- 238000010943 off-gassing Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000003746 surface roughness Effects 0.000 abstract description 3
- 239000011368 organic material Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 6
- 238000009832 plasma treatment Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000001552 radio frequency sputter deposition Methods 0.000 description 4
- 239000005416 organic matter Substances 0.000 description 3
- 238000010924 continuous production Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- -1 CHN compound Chemical class 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 비아 형성 과정에서 비아 측벽의 표면 거칠기 증가를 방지하여 비아 내에 금속막을 효과적으로 매립할 수 있고, 고온에서 실시되는 금속막 증착과정에서 비아측벽의 폴리머 저유전체막 또는 실리콘산화막계 유전체막으로부터 유기물 또는 수분이 아웃개싱 되는 것을 효과적으로 억제할 수 있는 금속배선 형성 방법에 관한 것으로, 유전체막을 식각하여 하부금속배선을 노출시키는 비아를 형성한 후 하부금속배선 표면의 금속산화막층을 제거하기 위한 스퍼터링 과정에서 Ar 가스에 N2또는 NH3등과 같이 질소가 포함된 가스를 혼합함으로써 비아측벽에 드러난 유전체막 표면에 보호막을 형성하는데 그 특징이 있다.The present invention can effectively fill the metal film in the via by preventing the surface roughness of the via sidewall during the via formation process, and the organic material from the polymer low dielectric film or silicon oxide based dielectric film of the via side wall during the metal film deposition process performed at a high temperature. Alternatively, the present invention relates to a method for forming a metal wiring that can effectively suppress outgassing of moisture, and after forming a via to expose a lower metal wiring by etching a dielectric film, in a sputtering process for removing a metal oxide layer on the surface of the lower metal wiring. It is characteristic to form a protective film on the surface of the dielectric film exposed on the sidewall of the via by mixing a gas containing nitrogen such as N 2 or NH 3 with Ar gas.
Description
본 발명은 반도체 소자 제조 분야에 관한 것으로, 특히 반도체 소자의 금속배선 형성을 위한 비아 형성 과정에서 비아 측벽이 손상됨에 따라 비아 내에 금속막이 불량하게 매립되는 것을 방지할 수 있으며 비아 내부로 유기물 또는 수분 등이 아웃개싱되는 것을 효과적으로 억제할 수 있는 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of manufacturing semiconductor devices, and in particular, as the sidewalls of the vias are damaged during the formation of the vias for forming the metal wires of the semiconductor devices, the metal film may be prevented from being poorly embedded in the vias. The present invention relates to a method for forming metal wirings in a semiconductor device that can effectively suppress outgassing.
반도체 소자의 고집적화에 따른 RC 시간 지연 및 상호 신호간섭에 의한 반도체 소자 특성 저하 등이 큰 문제로 지적되면서 저유전체막 및 저저항 금속배선의 집적 공정 기술 개발에 대한 많은 연구가 진행중이다.As RC time delay due to high integration of semiconductor devices and deterioration of semiconductor device characteristics due to mutual signal interference have been pointed out as a big problem, many researches on the development of integrated process technology of low dielectric film and low resistance metal wiring have been conducted.
저유전체막으로는 폴리머 재료에 대한 연구 개발이 이루어지고 있으며 금속 배선인 Al과의 집적 공정에 대한 연구가 심도있게 진행되고 있다. 폴리머 저유전체는 탄소와 수소의 화합물에 약간의 산소가 첨가되어 성긴 구조를 갖는 물질이다. 이러한 폴리머 저유전체로 금속배선간 절연막(inter metal dielectric)을 형성하고, 금속배선간 절연막 내에 형성된 비아(via)를 통하여 하부 금속배선과 상부 금속배선이 연결된다.As a low dielectric film, research and development on polymer materials are being conducted, and research on the integration process with Al, which is a metal wiring, is being conducted in depth. A polymer low dielectric material is a substance having a sparse structure by adding some oxygen to a compound of carbon and hydrogen. An intermetal dielectric is formed of the polymer low dielectric material, and the lower metal interconnection and the upper metal interconnection are connected through vias formed in the intermetal interconnection.
하부 금속배선과 비아 내에 매립되는 금속이 전기적으로 연결되도록 하기 위해서는 하부 금속막 표면에 형성된 금속산화막층을 제거하여야 한다. 따라서 Al 등의 금속물질을 비아 내에 매립하기 전에 비아 바닥에 노출된 금속산화막층을 제거하기 위하여 Ar 가스로 스퍼터링(sputtering) 식각을 진행한다. 스퍼터링 과정에서 운동에너지를 갖고 기판으로 향하는 Ar 이온은 비아 상부 및 측벽까지 함께 식각함에 따라 스퍼터링 식각 과정에서 비아 측벽에 노출된 폴리머 저유전체막이 손상되어 비아 측벽의 표면 거칠기가 증가한다.In order to electrically connect the metal buried in the lower metal wiring and the via, the metal oxide layer formed on the surface of the lower metal film must be removed. Therefore, sputtering etching is performed with Ar gas to remove the metal oxide layer exposed on the bottom of the via before the metal material such as Al is buried in the via. Ar ions having kinetic energy toward the substrate in the sputtering process are etched together to the top and the sidewall of the via, thereby damaging the polymer low-k dielectric film exposed to the via sidewall during the sputtering etching, thereby increasing the surface roughness of the via sidewall.
이와 같이 손상된 폴리머 저유전체막 상에 Ti막(wetting Ti막)을 증착할 경우 그 표면이 거칠어질 뿐만 아니라 Ti막 상에 형성되는 Al막 역시 하부 폴리머 표면층의 영향을 받아 거칠어진다.When the Ti film (wetting Ti film) is deposited on the damaged polymer low-k dielectric film as described above, the surface is not only roughened, but the Al film formed on the Ti film is also roughened by the influence of the lower polymer surface layer.
첨부된 도면 도1a 및 도1b를 참조하여 종래 기술에 따른 반도체 소자의 금속배선 형성 방법의 문제점을 보다 상세하게 설명한다.Referring to the accompanying drawings, FIGS. 1A and 1B, the problem of the method for forming a metal wiring of a semiconductor device according to the prior art will be described in more detail.
도1a는 Al 하부금속 배선(11) 형성이 완료된 반도체 기판(도시하지 않음) 상에 폴리머 저유전체막(12) 및 실리콘산화막(13)을 차례로 증착하고, 실리콘산화막(13)과 폴리머 저유전체막(12)을 선택적으로 식각하여 하부금속배선(11)을 노출시키는 비아를 형성한 다음, Al 하부 금속배선(11) 표면의 AlOx막(14)을 제거하기 위하여 Ar 스퍼터링 공정을 실시하는 과정에서 폴리머 저유전체막(12)으로 이루어지는 비아 측벽이 거칠어지는 것(D)을 보이고 있다.FIG. 1A sequentially deposits a polymer low dielectric film 12 and a silicon oxide film 13 on a semiconductor substrate (not shown) on which the Al lower metal wiring 11 is formed, and then deposits a silicon oxide film 13 and a polymer low dielectric film. (12) is selectively etched to form vias exposing the lower metallization 11, and then in the process of performing an Ar sputtering process to remove the AlO x film 14 on the Al lower metallization 11 surface. The via sidewall made of the polymer low dielectric film 12 is roughened (D).
상기와 같은 Ar 스퍼터링으로 Al 하부 금속배선(11) 표면의 AlOx막(14)을 제거한 후, 도1b와 같이 상부 금속배선을 형성하기 위한 Al막(15) 증착공정을 진행할 경우 비아 측벽의 거칠기에 따라 비아 내부에 Al막(15)이 양호하게 매립되지 못하고 불연속적이고 불균일하게 매립되어 공공(void)이 발생하게 된다.After removing the AlO x film 14 on the surface of the lower Al metal wiring 11 by Ar sputtering as described above, roughness of the via sidewall when the Al film 15 deposition process is performed to form the upper metal wiring as shown in FIG. As a result, the Al film 15 may not be well buried in the via, and thus voids may be generated by being discontinuously and unevenly embedded.
특히 소자의 양호한 전기적 특성을 얻기 위해서는, 비아 내에 Al막을 매립할 때 균일하고 연속된 Al막을 초기에 형성하여 후속 Al막 증착시 매립이 양호하게 이루어지도록 하여야 하는데, 전술한 바와 같이 폴리머 저유전체막의 표면 및 비아내부 표면이 거칠어질 경우에는 초기 증착되는 Al층이 불연속적으로 증착되어 Al 매립 공정이 어려워지는 문제를 초래하게 된다.In particular, in order to obtain good electrical characteristics of the device, a uniform and continuous Al film should be initially formed when the Al film is buried in the via, so that the buried is satisfactory during subsequent Al film deposition. As described above, the surface of the polymer low dielectric film When the via inner surface becomes rough, the Al layer deposited initially is discontinuously deposited, which causes a problem in that the Al filling process becomes difficult.
또한, 비아 측벽에 폴리머 저유전체막이 노출될 경우 고온에서 실시되는 금속막 증착 과정에서 유기물이 아웃 개싱(out gassing)되고, 흡습성을 갖는 실리콘산화막계 유전체막이 노출될 경우에는 금속막 증착시 비아 측벽으로부터 수분이 아웃 개싱되는 문제점이 있다.In addition, when the polymer low dielectric film is exposed to the via sidewall, organic matter is outgassed during the metal film deposition process performed at a high temperature, and when the silicon oxide film dielectric layer having hygroscopicity is exposed, the metal side film is deposited from the via sidewall during deposition. There is a problem that moisture is out-gassed.
상기와 같은 문제점을 해결하기 위한 본 발명은 비아 형성 과정에서 비아 측벽의 표면 거칠기 증가를 방지하여 비아 내에 금속막을 효과적으로 매립할 수 있고, 고온에서 실시되는 금속막 증착과정에서 비아측벽의 저유전체막 또는 실리콘 산화막계 유전체막으로부터 유기물 또는 수분이 아웃개싱되는 것을 효과적으로 억제할 수 있는 금속배선 형성 방법을 제공하는데 그 목적이 있다.The present invention for solving the above problems is to prevent the increase of the surface roughness of the via sidewalls in the via formation process to effectively fill the metal film in the vias, the low dielectric film of the via sidewall in the metal film deposition process carried out at high temperature or SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming metal wirings which can effectively suppress the outgassing of organic substances or moisture from silicon oxide based dielectric films.
도1a 및 도1b는 종래 기술에 따른 반도체 소자의 금속배선 형성 공정 단면도,1A and 1B are cross-sectional views of a metal wiring forming process of a semiconductor device according to the prior art;
도2a 내지 도2d는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성 공정 단면도.2A to 2D are cross-sectional views of a metal wiring forming process of a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
21: Al 하부금속 배선 22: 폴리머 저유전체막21: Al lower metal wiring 22: polymer low dielectric film
23: 실리콘산화막 24: AlOx막23: silicon oxide film 24: AlO x film
25: 보호막 26: Ti막25: protective film 26: Ti film
27: Al막27: Al film
상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 형성된 하부 금속배선을 덮는 폴리머 유전체막을 선택적으로 식각하여 상기 하부 금속배선을 노출시키는 비아를 형성하는 제1 단계; 아르곤 및 질소 혼합 가스를 이용한 스퍼터링을 실시하여 상기 하부 금속배선 표면의 금속산화막을 제거하면서 상기 비아 측벽에 노출된 상기 폴리머 유전체막 표면에 C-H-N 화합물로 이루어지는 보호막을 형성하는 제2 단계; 및 상기 비아 내에 금속막을 매립하는 제3 단계를 포함하는 반도체 소자 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a semiconductor device including a first step of selectively etching a polymer dielectric layer covering a lower metal interconnection formed on a semiconductor substrate to form a via exposing the lower metal interconnection; A second step of forming a protective film made of a C-H-N compound on the surface of the polymer dielectric film exposed to the sidewall of the via while removing the metal oxide film on the surface of the lower metal wiring by sputtering using a mixture of argon and nitrogen; And a third step of embedding a metal film in the via.
또한 상기 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 형성된 하부 금속배선을 덮는 실리콘산화막을 선택적으로 식각하여 상기 하부 금속배선을 노출시키는 비아를 형성하는 제1 단계; 아르곤 및 질소 혼합 가스를 이용한 스퍼터링을 실시하여 상기 하부 금속배선 표면의 금속산화막을 제거하면서 상기 비아 측벽에 노출된 상기 실리콘산화막 표면에 SiON 보호막을 형성하는 제2 단계; 및 상기 비아 내에 금속막을 매립하는 제3 단계를 포함하는 반도체 소자 제조 방법을 제공한다.In addition, the present invention for achieving the above object, the first step of forming a via to expose the lower metal wiring by selectively etching the silicon oxide film covering the lower metal wiring formed on the semiconductor substrate; A second step of forming a SiON protective film on the silicon oxide film surface exposed to the sidewall of the via while removing the metal oxide film on the lower metal wiring surface by sputtering using a mixture of argon and nitrogen; And a third step of embedding a metal film in the via.
본 발명은 유전체막을 식각하여 하부금속배선을 노출시키는 비아를 형성한 후 Ar 가스에 N2또는 NH3등과 같이 질소가 포함된 가스를 혼합하여 하부금속배선 표면의 금속산화막층을 식각하기 위한 스퍼터링을 실시함으로써 비아측벽에 드러난 유전체막 표면을 처리하는데 특징이 있다. 이와 같이 본 발명은 비아 형성 후 Ar에 N2또는 NH3등과 같이 질소가 포함된 가스를 혼합하여 스퍼터링을 실시함으로써 플라즈마 처리 효과에 의해 비아 측벽에 노출된 저유전체막 표면을 개질하여 보호막을 형성함으로써 비아 내에 증착되는 Ti막 및 Al막의 매립특성을 향상시킬 수 있으며, 고온에서 실시되는 금속막 증착 공정에서 유전체막 내의 유기물 또는 수분 등이 비아쪽으로 아웃-개싱(out gassing)되는 것을 효과적으로 방지할 수 있다.The present invention forms a via to expose the lower metal wiring by etching the dielectric film, and then sputtering for etching the metal oxide layer on the surface of the lower metal wiring by mixing a gas containing nitrogen such as N 2 or NH 3 with Ar gas. This method is characterized by treating the surface of the dielectric film exposed on the via side wall. As described above, the present invention performs sputtering by mixing a gas containing nitrogen such as N 2 or NH 3 to Ar after forming vias to form a protective film by modifying the surface of the low dielectric film exposed to the sidewalls of the vias by the plasma treatment effect. The buried characteristics of the Ti film and the Al film deposited in the via can be improved, and in the metal film deposition process performed at a high temperature, organic matter or moisture in the dielectric film can be effectively prevented from out-gassing to the via. .
이하, 첨부된 도면 도2a 내지 도2d를 참조하여 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성 방법을 상세하게 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings of FIGS. 2A to 2D.
먼저 도2a에 도시한 바와 같이 Al 하부금속 배선(21) 형성이 완료된 반도체 기판(도시하지 않음) 상에 유전율이 2 내지 3인 폴리머 저유전체막(22) 및 실리콘산화막(23)을 차례로 증착하고, 실리콘산화막(23)을 선택적으로 식각하여 그 하부의 폴리머 저유전체막(22)을 노출시키고, 실리콘산화막(23)을 식각마스크로 상기 폴리머 저유전체막(22)을 식각해서 하부금속배선(21)을 노출시키는 비아를 형성한 다음, Ar에 N2또는 NH3가스가 혼합된 가스를 이용하여 RF 스퍼터링을 실시함으로써 Al 하부 금속배선(21) 표면의 AlOx막(24)을 제거한다. 이때, 스퍼터링 식각과 플라즈마 처리 효과가 최적으로 진행되도록 하기 위해서 소오스(source) 및 바이어스(bias) 파워를 조절하는 DFE(Dual Frequency Etch) 방식을 이용하고, Ar과 N2또는 NH3가스의 혼합가스에서 N2또는 NH3가스의 부피비는 1 % 내지 20 %가 되도록 한다.First, as shown in FIG. 2A, a polymer low dielectric film 22 having a dielectric constant of 2 to 3 and a silicon oxide film 23 are sequentially deposited on a semiconductor substrate (not shown) on which the Al lower metal wiring 21 is formed. The silicon oxide film 23 is selectively etched to expose the polymer low dielectric film 22 below the silicon oxide film 23, and the polymer low dielectric film 22 is etched using the silicon oxide film 23 as an etch mask. ), Vias are formed, and then RF sputtering is performed using a gas in which N 2 or NH 3 gas is mixed with Ar, thereby removing the AlO x film 24 on the surface of the lower Al metal wiring 21. In this case, in order to optimize the sputtering etching and plasma treatment effects, a mixed gas of Ar and N 2 or NH 3 gas is used, using a DFE (Dual Frequency Etch) method that adjusts source and bias power. Wherein the volume ratio of N 2 or NH 3 gas is from 1% to 20%.
이와 같은 스퍼터링으로 AlOx막(24)이 제거되면서 플라즈마 처리 효과에 의해 도2b에 도시한 바와 같이 비아 측벽의 폴리머 저유전체막(22)에 보호막(25)이 형성된다. 즉, N2또는 NH3가스의 N 원자가 폴리머 저유전체막(22) 표면의 C-H 화합물 구조에 결합하여 C-H-N 화합물로 이루어지는 보호막(25)이 형성된다.As a result of the sputtering, the AlO x film 24 is removed and a protective film 25 is formed on the polymer low dielectric film 22 on the sidewalls of the via as shown in FIG. 2B due to the plasma treatment effect. That is, the N film of the N 2 or NH 3 gas is bonded to the CH compound structure on the surface of the polymer low dielectric film 22 to form a protective film 25 made of the CHN compound.
한편, 상기와 같이 N2또는 NH3가스가 혼합된 상태에서 RF 스퍼터링을 진행할 경우 AlOx막(24) 제거 후 노출된 Al 하부금속배선(21)과 N2또는 NH3의 N이 결합하여 부도체 특성을 가진 AlN이 형성될 가능성이 있다. 따라서, RF 스퍼터링으로AlOx막(24)을 제거한 후 Ar 가스만을 이용한 RF 스퍼터링을 실시하여 Al 하부금속배선(21) 표면의 AlN막을 제거하는 공정이 추가될 수도 있다.On the other hand, when RF sputtering is performed in a state where N 2 or NH 3 gas is mixed as described above, after the AlO x film 24 is removed, the exposed Al lower metal wiring 21 and N of N 2 or NH 3 are bonded to each other. There is a possibility that AlN having characteristics is formed. Therefore, after the AlO x film 24 is removed by RF sputtering, RF sputtering using only Ar gas may be performed to remove the AlN film on the Al lower metal wiring 21 surface.
다음으로 도2c에 도시한 바와 같이 전체 구조 상에 Ti막(wetting Ti막, 26) 및 균일한 Al막(27)을 차례로 형성한다.Next, as shown in FIG. 2C, a Ti film (wetting Ti film) 26 and a uniform Al film 27 are sequentially formed on the entire structure.
이어서 도2d에 도시한 바와 같이 연이은 고온 Al막(27) 증착으로 비아를 완전하게 매립한다. 상기 Al막은 물리기상증착(physical vapor deposition) 또는 화학기상증착법(chemical vapor deposition)으로 형성한다.Subsequently, as shown in FIG. 2D, vias are completely filled by subsequent high temperature Al film 27 deposition. The Al film is formed by physical vapor deposition or chemical vapor deposition.
상기 폴리머 저유전체막(22)을 대신하여 실리콘 산화막계 유전체막을 형성한 경우에도 본 발명을 적용할 수 있다. 즉, Ar과 N2또는 NH3혼합가스를 이용한 스퍼터링 과정에서 비아 측벽에 노출된 실리콘 산화막 표면을 개질시킬 수도 있다.The present invention can also be applied when a silicon oxide based dielectric film is formed in place of the polymer low dielectric film 22. That is, the silicon oxide film surface exposed to the sidewalls of the via may be modified during the sputtering process using Ar and N 2 or NH 3 mixed gas.
이와 같이 하부금속배선 표면의 금속산화막을 제거하기 위한 스퍼터링 과정에서 비아 측벽에 드러난 폴리머 저유전체막 또는 실리콘산화막을 N2또는 NH3가스의 플라즈마로 처리함에 따라 다음과 같은 효과를 얻을 수 있다.As described above, the polymer low dielectric film or silicon oxide film exposed on the sidewalls of the via may be treated with plasma of N 2 or NH 3 gas in the sputtering process for removing the metal oxide film on the lower metal wiring surface.
먼저, 폴리머 저유전체막의 경우는 폴리머막의 C-H 결합을 갖는 표면을 C-H-N 등의 결합을 갖는 표면으로 개질하여 비아 측벽에 얇은 보호막을 형성함으로써 이후 실시되는 스퍼터링 식각시 비아 측벽의 손상을 크게 감소시켜 비아 내에 매립되는 Ti 또는 Al을 균일하게 증착할 수 있고, 연이어 증착되는 고온 Al막을 양호하게 매립할 수 있다. 또한, 전술한 바와 같이 비아 측벽에 얇은 보호막을 형성함으로써 고온에서 실시되는 금속막 증착 과정에서 폴리머 저유전체막 내의 유기물 또는 수분 등이 비아쪽으로 아웃-개싱(out gassing)되는 것을 방지할 수 있다.First, in the case of a polymer low dielectric film, a surface having CH bonds of the polymer film is modified to a surface having CHN or the like bond to form a thin protective film on the sidewall of the via, thereby greatly reducing damage to the sidewall of the via during sputter etching. Ti or Al to be embedded can be uniformly deposited, and the hot Al film subsequently deposited can be well buried. In addition, as described above, by forming a thin protective film on the sidewall of the via, it is possible to prevent the outgassing of organic matter or moisture in the polymer low-k dielectric film toward the via during the metal film deposition process performed at a high temperature.
그리고, 실리콘산화막계 유전체막의 경우는 비아 측벽에 노출된 SiOx가 N과 반응하여 막질이 치밀한 SiON막이 형성됨으로써 고온에서 실시되는 금속막 증착 과정에서 저유전체막 내부의 수분 등이 비아 쪽으로 아웃개싱되는 것을 방지하여 고온 금속막 증착 공정시 매립 불량이 발생하는 것을 방지할 수 있다.In the case of the silicon oxide-based dielectric film, SiO x exposed on the sidewall of the via reacts with N to form a dense SiON film, which causes moisture inside the low dielectric film to be outgassed toward the via during the deposition of the metal film at a high temperature. It is possible to prevent the occurrence of landfill defects during the high temperature metal film deposition process.
또한, 스퍼터링 식각시의 플라즈마 처리는 금속배선 형성 공정중 금속막 매립 공정전에 인시튜(in-situ)로 진행 가능하게 함으로써 일련적이고 연속적인 공정으로 금속배선 공정을 가능하게 할 수 있다.In addition, the plasma treatment during the sputtering etching may be performed in-situ before the metal film embedding process in the metal wiring forming process, thereby enabling the metal wiring process in a serial and continuous process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 비아 내에 금속막을 재현성있고 안정되게 증착하여 반도체 소자의 신뢰성을 향상시킬 수 있다. 특히 비아 측벽에 노출된 폴리머 계열의 저유전체막 표면을 플라즈마 처리 효과에 의해 개질하여 C-H-N 보호막을 형성함으로써 스퍼터링 식각에 따른 비아 측벽의 손상을 방지하여 금속막의 매립 특성을 향상시킬 수 있으며 고온에서 실시되는 금속막 증착 과정에서 폴리머 계열의 저유전체막으로부터 비아 쪽으로 유기물이 외확산되는 것을 방지할 수 있다.또한, 비아 측벽에 실리콘 산화막이 노출될 경우에도 비아 측벽에 보호막을 형성함으로써 고온에서 실시되는 금속막 증착 공정에서 수분 등이 비아 쪽으로 외확산되는 것을 효과적으로 억제할 수 있다. 그리고 전술한 플라즈마 처리 효과는 금속막 매립 공정 전에 인-시튜로 진행할 수 있으며 일련적이고 연속적인 공정으로 제조 공정의 수율을 향상시킬 수 있다.According to the present invention, the metal film is reproducibly and stably deposited in the via, thereby improving the reliability of the semiconductor device. In particular, the surface of the polymer-based low dielectric film exposed to the via sidewall is modified by the plasma treatment effect to form a CHN protective film, thereby preventing damage to the via sidewall due to the sputter etching, thereby improving the embedding characteristics of the metal film and being performed at high temperature. In the deposition process of the metal film, organic diffusion of the organic material from the low dielectric film of the polymer series can be prevented from being diffused to the via. In addition, even when the silicon oxide film is exposed on the sidewall of the via, a protective film is formed on the sidewall of the via to form a protective film on a high temperature. In the deposition process, it is possible to effectively suppress the diffusion of moisture and the like toward the vias. In addition, the above-described plasma treatment effect may be performed in-situ before the metal film embedding process, and the yield of the manufacturing process may be improved by a serial and continuous process.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100780680B1 (en) * | 2001-12-20 | 2007-11-30 | 매그나칩 반도체 유한회사 | Method for forming metal wiring of semiconductor device |
| KR100780766B1 (en) * | 2005-12-29 | 2007-11-30 | 주식회사 하이닉스반도체 | Method for fabricating contact in semiconductor device |
| KR100855622B1 (en) | 2007-08-29 | 2008-09-03 | 삼성전기주식회사 | Plugging method of via hole |
| KR101027337B1 (en) * | 2004-06-30 | 2011-04-11 | 주식회사 하이닉스반도체 | Method for fabrication of conduction pattern of semiconductor device having tungsten layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980055903A (en) * | 1996-12-28 | 1998-09-25 | 김영환 | Via hole formation method of semiconductor device |
| KR100445411B1 (en) * | 1997-06-30 | 2004-11-06 | 주식회사 하이닉스반도체 | Method of forming metal line of semiconductor device for reducing contact resistance and improving leakage current characteristic |
| KR100258875B1 (en) * | 1998-01-15 | 2000-06-15 | 김영환 | Method of forming via for multilayer wiring |
| KR20000003454A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Method of fabricating semiconductor device using high density plasma oxide film as interfacial insulation film |
| KR100564415B1 (en) * | 1998-10-29 | 2006-06-21 | 주식회사 하이닉스반도체 | Contact hole formation method of semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100780680B1 (en) * | 2001-12-20 | 2007-11-30 | 매그나칩 반도체 유한회사 | Method for forming metal wiring of semiconductor device |
| KR101027337B1 (en) * | 2004-06-30 | 2011-04-11 | 주식회사 하이닉스반도체 | Method for fabrication of conduction pattern of semiconductor device having tungsten layer |
| KR100780766B1 (en) * | 2005-12-29 | 2007-11-30 | 주식회사 하이닉스반도체 | Method for fabricating contact in semiconductor device |
| US7741209B2 (en) | 2005-12-29 | 2010-06-22 | Hynix Semiconductor Inc. | Contact structure of semiconductor device and method for fabricating the same |
| US8084351B2 (en) | 2005-12-29 | 2011-12-27 | Hynix Semiconductor Inc. | Contact structure of a semiconductor device |
| KR100855622B1 (en) | 2007-08-29 | 2008-09-03 | 삼성전기주식회사 | Plugging method of via hole |
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