KR20010101360A - Method and apparatus for trunking multiple ports in a network switch - Google Patents

Abstract

The present invention relates to a network switch adapted to switch data packets between multiple port usages and address tables to generate transmission information. The decision execution engine examines the frame transmission information to determine if the frame is transmitted on a port that is part of the trunk. When the frame is output on the trunk port, the decision making engine determines the port on which the frame is sent.

Description

METHOD AND APPARATUS FOR TRUNKING MULTIPLE PORTS IN A NETWORK SWITCH}

In a computer network, multiple network stations are connected to each other via a communication medium. For example, Ethernet is a commonly used local area network technology in which multiple stations are connected to a single shared serial data path. Such stations often communicate with switches located between the shared data path and the stations connected to the path. Typically, a switch controls the communication of data packets on the network.

The network switch includes switching logic to receive the frames and send them to the appropriate destinations. One arrangement for generating frame transmission decisions uses a direct addressing technique, where the network switch includes a fixed address table that stores the switching logic for the destination addresses. For example, a frame may be received by a network switch with header information indicating the source address and destination address of the frame. The switching logic finds the appropriate frame transfer information by searching for a fixed address using the source address and destination address as lookups. The switch uses this information to send the frame to the appropriate port (s).

When all stations coupled to the network are operating at the same time, the packet traffic on the shared serial path becomes large due to the small time between packets. In addition, due to network throughput requirements, it has become increasingly important to increase the speed at which data is sent to its destination.

One arrangement for increasing the speed of transferring data between stations is "trunking," also referred to as link aggregation, which combines multiple links to form a trunk between two stations. For example, suppose that two separate ports on the switch are each configured to support a data rate of 100 Mb / s. Trunking technology links two ports together and transmits / receives data through these two ports, resulting in a 200Mb / s link between the two stations.

The disadvantage of this trunking technique is that the address table must store the appropriate trunking information, including the specific trunk port to which the data will be sent. That is, the address table should not only store information indicating whether a particular port is part of a trunk, but also store information indicating a port of a trunk to which data is transmitted when data transmission information indicates that an output port is part of a trunk. Storing this trunking information in the address table not only significantly increases the physical size of the address table, but also significantly increases the switching logic, thereby increasing the time it takes to transmit the frame transfer information.

In addition, when a change to the stored trunking information is required, that is, when the network configuration is changed, the address table must also be changed correspondingly to indicate a new trunking configuration. This reconfiguration of the address table is time consuming and costly, which may cause network downtime.

There is a need for a switch device that supports trunking without storing trunking information in an address table.

It also supports trunking and allows you to change trunking without reprogramming the address table.

The present invention relates to network communications, and more particularly to trunking of multiple ports in a network switch that provides high speed network links.

1 is a block diagram of a packet switched network including multiple port switches in accordance with an embodiment of the present invention.

FIG. 2 is a block diagram of multiple port switches of FIG. 1.

3 is a detailed block diagram illustrating the switching subsystem of FIG. 2.

4 is a block diagram of a system including the internal rule checker of FIG. 2 in accordance with an embodiment of the present invention.

FIG. 5 shows a configuration of the IRC address table of FIG. 4.

6 illustrates the format of an IRC address table entry of the IRC address table of FIG. 5.

7 shows linked list chains that identify table entries for a selected bin.

FIG. 8 shows a hash function circuit with the internal rule checker of FIG. 2.

9 illustrates a composition of a transmission descriptor according to an embodiment of the present invention.

10 illustrates trunk member combinations in accordance with an embodiment of the present invention.

11 is a flowchart illustrating a method of generating frame transmission information in connection with trunking according to an embodiment of the present invention.

12 is a block diagram illustrating trunk mapping logic in accordance with an embodiment of the present invention.

These and other objects are met by the present invention, wherein the multiport switch includes an address table that stores address entries used by a decision making engine to make frame transmission decisions. The decision performing engine includes a trunking function so that the frame transmission information is checked to determine whether the frame is to be transmitted through an output port that is part of the trunk. When the output port is part of a trunk, the decision execution engine performs a trunk mapping function that determines which port to send the frame.

According to one aspect of the invention, a network switch is configured to control the communication of data frames between stations and to support trunking. The switch includes a table that stores address information and data transfer information. The switch also includes a decision execution engine configured to search the table and generate data transfer information for the data frame. The decision making engine is also configured to determine whether the data frame is to be sent through a port that is part of the trunk, and when the port is part of the trunk, determine which transmission port to send the data frame to.

Another aspect of the present invention provides a method for generating data transmission information in a multiport switch that controls communication of data frames between stations. The method includes receiving information from a data frame and searching an address table for data transmission information based on the received information. The method also includes determining if the data frame will be sent over a port that is part of a trunk. The method also includes generating a value indicating a transmission port to which to transmit the data frame when the frame is transmitted through a port that is part of a trunk.

Other advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description, which is described with reference to the accompanying drawings. The illustrated and described embodiments present the best mode for carrying out the invention. The present invention can be changed in various and obvious aspects without departing from the scope of the invention.

The invention will now be described taking as an example a switch in a packet switched network such as an Ethernet (IEEE 802.3) network. However, the present invention is also applicable to other packet switching systems as well as other types of systems in general, as described in detail below.

Switch structure overview

1 is a block diagram of an exemplary system in which the present invention may be employed. Exemplary system 10 is a packet switched network, such as, for example, an Ethernet (IEEE 802.3) network. The packet switched network includes integrated multiport switches (IMS) 12 that enable communication of data packets between network stations. The network may be configured in other configurations, for example, 12 10 Mb / s or 100 Mb / s network stations 14 (hereinafter 10/100 Mb / s) for transmitting and receiving data at a network data rate of 10 Mb / s or 100 Mb / s, and It may also include network stations having a 1000 Mb / s (ie 1 Gb / s) network node 22 that transmits and receives data packets at a network speed of 1 Gb / s. Gigabit node 22 may be a server or a gateway to a high speed backbone network. Accordingly, the multiport switches 12 selectively transmit data packets received from network nodes 14 or 22 to the appropriate destination based on the Ethernet protocol.

Each multiport switch 12 includes a medium access control (MAC) module 20, which is 10/100 Mb / over each reduced medium independent interfaces (RMII) 18 according to the IEEE 802.3u protocol. s Send data packets to or receive data packets from the physical layer (PHY) transceivers 16. Each multiport switch 12 also includes a gigabit MAC 24 that sends and receives data packets to and from the gigabit PHY 26 for transmission to the gigabyte node 22 via the high speed network medium 28.

Each 10/100 Mb / s network station 14 transmits and receives data packets with the corresponding multiport switch 12 over medium 17 according to a half- or full-duplex Ethernet protocol. The Ethernet protocol ISO / IEC 8802-3 (ANSI / IEEE Std. 802.3 1993 Ed.) Defines a half-duplex medium access mechanism that allows all stations 14 to access the network channel equally. Traffic in the half duplex environment is not distinguished on the medium 17. Rather, each half-duplex station 14 uses an Ethernet interface card that uses carrier detection multiple access / collision detection function (CSMA / CD) to listen to traffic on the medium. The absence of network traffic is detected by detecting the deassertion of the receiving carrier on the medium. All stations 14 with data to transmit will want to access the channel after waiting for a predetermined time, known as the interpacket gap interval (IPG), after the decision of the receiving carrier on the medium. If multiple stations 14 have data to transmit on the network, each station would like to transmit in response to the sensed decision of the receiving carrier on the medium and may cause a collision after the IPC interval. Accordingly, the transmitting station will monitor the medium and determine if there is a collision due to another station transmitting data at the same time. If a collision is detected, the two stations stop transmitting, wait some time and then retry the transmission.

10/100 Mb / s network stations 14 operating in full duplex mode transmit and receive data packets according to the Ethernet standard IEEE 802.3u. Full-duplex environment is a bi-directional, point-to-point method that enables simultaneous transmission and reception of data packets between each link partner, that is, a 10/100 Mb / s network station 14 and the corresponding multiport switch 12. Provide a link.

Each multiport switch 12 is a 10/100 physical layer (PHY) transceiver 16 configured to transmit and receive data packets with the corresponding multiport switch 12 via a corresponding reduced medium independent interface (RMII) 18. Is coupled to. In particular, each 10/100 PHY transceiver 16 is configured to send and receive data packets between the multiport switch 12 and up to four network stations 14 via the RMII 18. Magnetic transformer 19 provides AC coupling between PHY transceiver 16 and corresponding network station media 17. Accordingly, the RMII 18 operates at a data rate sufficient to simultaneously send and receive data packets by the respective network stations 14 to the corresponding PHY transceiver 16 by means of the data packets.

Each multiport switch 12 also includes an expansion port 30 for transferring data between other switches in accordance with a defined protocol. Each expansion port 30 allows multiple multiport switches 12 to be cascaded together as separate backbone networks.

2 is a block diagram of the multiport switch 12. The multiport switch 12 includes a decision performing engine 40 for performing a frame transmission decision, a switching subsystem 42 for transmitting frame data in accordance with the frame transmission decision, an external memory interface 44, and a handling information base. (MIB) MAC (Media Connection) that supports routing of data packets between counters 48a and 48b, collectively 48, and Ethernet (IEEE 802.3) protocols acting on network stations 14 and gigabit nodes 22 Control) protocol interfaces 20 and 24. The MIB counters 48 provide statistical network information in the form of a handling information base (MIB) to an external handling entity controlled by the host CPU 32, as described below.

The external memory interface 44 enables external storage of packet data in the external memory 36, for example synchronous static random access memory (SSRAM), thereby minimizing the chip size of the multiport switch 12. In particular, the multiport switch 12 utilizes an external memory 36 for storing received frame data and memory structures. The external memory 36 is preferably a zero bus turnaround ^TM (ZBT) -SSRAM having a burst or 64 bit sized data path and a 17 bit sized address path constructed from a joint electron device engineering council (JEDEC) pipeline. The external memory 36 is addressable as upper and lower banks of 128K in 64-bit words. The size of the external memory 36 is preferably at least 1 Mbytes, allowing data transmission for all clock periods through the pipeline. In addition, the external memory interface clock operates at at least 66 MHz, and preferably at 100 MHz and higher clock frequencies.

Multiport switch 12 also includes a processing interface 50 that allows an external handling entity, such as host CPU 32, to control the overall operation of multiport switch 12. In particular, processing interface 50 decodes CPU accesses within a defined register access space, reads configuration and status values from configuration and status registers 52, and configures and statuses in configuration and status registers 52. Record the values.

An internal decision making engine 40, referred to as an internal rule checker (IRC), makes a frame transmission decision on the received data packets.

The multiport switch 12 also clocks out the state of the conditions per port and drives external LED logic. External LED logic drives the human readable DLE display elements.

Switching subsystem 42 configured to execute frame transfer decisions of IRC 40 includes first-in-first-out (FIFO) buffer 56, multiple output queues 58, multicopy queue 60, multicopy cache 62 , Free buffer queue 62, and reclaim queue 66.

The MAC unit 20 includes modules for each port, each module including a MACM receiver, a receive FIFO buffer, a transmit FIFO buffer, and a MAC transmitter. Data packets from the network station 14 are received by the corresponding MAC port and stored in the corresponding receive FIFO. The MAC unit 20 obtains a free buffer position (i.e., frame pointer) from the free buffer queue 64, and from the corresponding receive FIFO for storage in the external memory 36 at the position designated by this frame pointer. The received data packets are output to the external memory interface 44.

IRC 40 monitors the data bus (ie, "snoops") to determine the frame pointer and header information of the received packet (including source, destination, and VLAN address information). The IRC 40 uses the header information to determine whether the MAC ports will output a data frame stored at the location specified by the frame pointer. Thus, the decision execution engine (i.e. IRC 40) may determine whether a given data frame should be output by a single port, multiple ports, all ports (i.e. broadcast) or not by any ports ( That is, discarded. For example, each data frame includes a header having a source and a destination address, where the decision making engine 40 may identify the appropriate output MAC port based on the destination address. Alternatively, the destination address may correspond to a virtual address that the appropriate decision making engine identifies as the corresponding multiple network stations. The frame may also include a VLAN tag header that identifies the frame as information that will be directed to one or more members of the defined stations. IRC 40 may also determine whether a received data packet should be sent to another multiport switch 12 via expansion port 30. Accordingly, the internal rule checker 40 will determine whether a frame temporarily stored in the external memory 36 should be output to a single MAC port or multiple MAC ports.

The internal rule checker 40 outputs the forwarding decision to the switch subsystem 42 in the form of a forwarding descriptor. Transmit descriptors include a priority class that identifies whether a frame is high or low priority, a port vector identifying each MAC port to which data frames should be sent, a receiving port number, and an untagged. ), A set of VLAN information, a vector identifying each MAC port that should contain VLAN information during transmission, an opcode, and a frame pointer. The format of the transmission descriptor is described below with respect to FIG. The port vector identifies the MAC ports (eg, 10/100 MAC ports 1-12, Gigabit MAC ports, and / or expansion ports) that receive the data frame for transmission. The port vector FIFO 56 decodes the transmission descriptor containing the port vector and supplies a frame pointer to the appropriate output queues 58 corresponding to the output MAC ports that receive the data frame transmission. That is, the port vector FIFO 56 supplies a frame pointer on a per-port basis. Output queues 58 provide a frame pointer to a dequeuing block 76 (shown in FIG. 3), which dequeuing block 76 is external memory 36 through an external memory interface 44. Patch the identified data frame in the port vector, and feed the received data frame to the appropriate transmit FIFO of the identified ports. If the data frame is to be supplied by a management agent, the frame pointer is also supplied to the handling queue 68 which can be processed by the host CPU 32 via the CPU interface 50.

Multicopy queue 60 and multicopy cache 62 keep track of the number of copies of data frames sent from their respective ports, so that when the appropriate number of copies of data frames are output from external memory 36 Until now, it ensures that data frames are not overwritten in external memory 36. If the number of copies output corresponds to the number of ports specified in the port vector FIFO 56, the frame pointer is sent to the reclaim queue 66. Reclaim queue 66 stores the frame pointers that need to be reclaimed, walks the linked list chain, and returns the buffers to free buffer queue 64 as free pointers. After returning to the free buffer queue 64, the frame pointer can be used for reuse by the MAC unit 20 or the gigabit MAC unit 24.

3 illustrates the switch subsystem 42 of FIG. 2 in more detail in accordance with an exemplary embodiment of the present invention. In FIG. 3 other elements of the multiport switch 12 of FIG. 2 are reproduced to show the connections of the switch subsystem 42 to these elements.

As shown in FIG. 3, the MAC module 20 includes a receiver 20a and a transmitter 24b. The receiver 24a and the transmitter 24b are each twelve MAC modules (only two of which are shown, each configured to perform the corresponding receive or transmit function according to the 802.3 protocol, numbered 70a, 70b, 70c and 70d, respectively). Is numbered). MAC modules 70c and 70d perform MAC operations for 10/100 Mb / s switch ports complementary to modules 70a and 70b, respectively.

The gigabit MAC port 24 also includes a receiver 24a and a transmitter 24b, and the expansion port 30 similarly includes a receiver 30a and a transmitter 30b. Gigabit MAC port 24 and expansion port 30 also have receive MAC modules 72a and 72b optimized for their respective ports. In addition, the transmitters 24b and 30b of the gigabit MAC port 24 and the expansion port 30 have transport MAC modules 72c and 72d, respectively. MAC modules are configured to operate in full duplex on the corresponding port, and the gigabit MAC modules 72a and 72c are configured according to the gigabit proposed standard IEEE draft P802.3z.

Each receiving MAC modules 70a, 70b, 72a, and 72b include queue logic 74 that transmits data received from the corresponding internal receive FIFO to external memory 36 and rule checker 40. Each of the transmit MAC modules 70c, 70d, 72c, and 72d is dequeuing logic 76 which transmits data from external memory 36 to the corresponding internal transmit FIFO, and frame pointer from free buffer queue 64. Queuing logic 74 to patch them. The queuing logic 74 stores the received data in the external memory 36 through the external memory interface controller 44 using the patched frame pointer. The frame buffer pointer specifies the location in external memory 36 where the received data frame will be stored by the receive FIFO.

The external memory interface controller 44 communicates with the scheduler 80, which controls memory access by the queuing logic 74 or dequeuing logic 76 of all switch ports to the external memory 36, and with the external memory 36. SSRAM interface 78 for performing read and write operations. In particular, the multiport switch 12 is configured to operate as a non-blocking switch, where network data is received and output from the switch ports at respective wire speeds of 10, 100, or 1000 Mb / s. As such, the scheduler 80 controls access by other ports to optimize bandwidth utilization of the external memory 36.

Each MAC stores the frame portion in an internal FIFO upon receipt from the corresponding switch port; The size of the FIFO is sufficient to store frame data arriving between scheduler time slots. Corresponding queuing logic 74 obtains a frame pointer and sends a write request to external memory interface 44. Scheduler 80 schedules all write requests and write requests from dequeuing logic 76 or other write requests from queuing logic 74, and queue queue 74 (or dequeuing logic 76). Generate a grant request to initiate transmission at the scheduled event (i.e. slot). This way, 64-bit frame data is transferred from the receive FIFO to external memory 36 via write data bus 69a in a direct memory access (DMA) transaction during the assigned slot. As described below, although a number of other buffers can be used to store the data frames, the frame data is stored at the location indicated by the buffer pointer obtained from the free buffer pool 64.

The rule checker 40 also receives a frame pointer and header information (including source address, destination address, VLAN tag information, and the like). The rule checker 40 performs a transmission decision using the header information, and generates a transmission indication in the form of a transmission descriptor including a port vector. The port vector has a set of bits for each output port to which a frame should be sent. If the received frame is a unicopy frame, only one bit is set in the port vector generated by the rule checker 40. The single bit set in the port vector corresponds to a particular one of the ports.

The rule checker 40 outputs a transmission descriptor including the port vector and the frame pointer to the port vector FIFO 56. The port vector is examined by the port vector FIFO 56 to determine if a particular output queue should receive the associated frame pointer. The port vector FIFO 56 places the frame pointer in the appropriate queue 56 and / or 68. This queues the transmission of the frame.

As shown in FIG. 3, each of the transmitting MAC units 70c, 70d, 72c and 72d has associated output queues 58a, 58b, 58c and 58d, respectively. In the preferred embodiment, each output queue 58 has a high priority queue for high priority frames and a low priority queue for low priority frames. High priority frames are used for frames that require guaranteed connection latency, for example frames for multimedia applications or handling MAC frames. Frame pointers stored in FIFO-type output queues 58 are processed by dequeuing logic 76 for each transmitting MAC unit. At any suitable point, the frame pointer reaches the bottom of the output queue 58, eg, the output queue 58d for the gigabit transmit MAC 72c. The dequeuing logic 76 for the transmit gigabit port 24b obtains a frame pointer from the corresponding gigabit port output queue 58d, and scheduler for reading frame data from the external memory 36 at the memory location specified by the frame pointer. Send a request to 80. The scheduler 80 schedules the request, issues a grant to the dequeuing logic 76 of the transmit gigabit port 24b and initiates a DMA read. In response to the authorization, the dequeuing logic 76 reads frame data (along the read bus 69b) from the location in the external memory 36 specified by the frame pointer (along the read bus 69b) and by the transmit gigabit MAC 72c. Frame data is stored in an internal transmit FIFO for transmission. If the transfer descriptor specifies a unicopy transfer, the frame pointer is returned to the free buffer queue 64 after writing the entire frame data into the transmit FIFO.

Multicopy transmission is similar to unicopy transmission except that the port vector has multiple sets of bits representing the multiple ports on which the data frame is to be transmitted. The frame pointer is located in each appropriate output queues 58 and sent by the appropriate transmitting MAC units 20b, 24b and / or 30b.

Free buffer pool 64, multicopy queue 60, reclaim queue 66, and multicopy cache 62, once the data frame is sent to its designated output port (s), utilize the frame pointers and It is used to coordinate the reuse of frame pointers. In particular, dequeuing logic 76 passes the frame pointers for unicopy frames to frame buffer queue 64 after the buffer contents are copied to the appropriate transmit FIFO.

For multicopy frames, port vector FIFO 56 supplies multiple copies of the same frame pointer to one or more output queues 58, each frame pointer having a set of up to zero unicopy bits. Porter vector FIFO 56 also copies the frame pointer and copy count to multicopy queue 60. The multicopy queue 60 writes a copy count to the multicopy cache 62. Multicopy cache 62 is a random access memory with a single copy count for each buffer (ie, each frame pointer) for external memory 36.

Once dequeuing logic 76 retrieves the frame data for a particular output port based on the patched frame pointer and stores the frame data in the transmit FIFO, dequeuing logic 76 has set the unicopy bit to 1. Check it. If the unicopy bit is set to 1, the frame pointer is returned to the free buffer queue 64. If the unicopy bit is set to zero indicating a multicopy frame pointer, dequeuing logic 76 writes a frame pointer with a copy count of -1 to multicopy queue 60. Multicopy queue 60 adds a copy count to entries stored in multicopy cache 62.

When the copy count in the multicopy cache 62 for the frame pointer reaches zero, the frame pointer is passed to the reclaim queue 66. Since multiple frame pointers may be used to store a single data frame in multiple buffer memory locations, the frame pointers are referenced to each other so that a linked-list of frame pointers may be used to identify a completely stored data frame. That is, to form a chain). Reclaim queue 66 traverses the chain of buffer locations identified by the frame pointers, passing the frame pointers to free buffer queue 64.

The above description of the switch architecture provides an overview of switch operations in a packet switched network. A more detailed description of the features of the invention implemented in the multiport switch 12 is described below.

Internal rule checkers

The present invention relates to providing a trunking function in a network switch, and more particularly to trunking of multiple ports forming a single network line. First, the IRC 40 will be described, and then the trunking method and apparatus in the multiport switch 12 will be described in detail.

As previously described, switch subsystem 42 provides switching logic to receive frames and send them to the appropriate output ports. However, the transmission decision is made by the IRC 40 located in the multiport switch 12. According to the embodiment of the present invention illustrated in FIG. 4, the IRC 40 includes four functional logic blocks: an ingress rule engine 200, a source address (SA) lookup engine 210, and a destination address ( DA) a lookup engine 220 and an egress rule engine 230. In an exemplary embodiment, four engines 200, 210, 220, and 230 are shown as separate devices. However, in an alternative configuration, these engines may be combined into a single logic device.

In the example embodiment shown in FIG. 4, the IRC 40 includes an address table 82. In an alternate embodiment, the address table 82 may be located outside the IRC 40 inside another part of the multiport switch 12 or even outside the multiport switch 12.

According to the exemplary embodiment, the address table 82 supports capacities for 4096 user addresses and 64 unique virtual local area networks (VLANs). However, the number of supported addresses and VLANs can be increased by extending the table size. VLANs provide "broadcast domains" where broadcast traffic is maintained "inside" of the VLAN. For example, a particular VLAN may contain a group of users at a high level of organization. When sending data to the group of users, the data may include a specific VLAN identifier associated with the particular group to ensure that only the users receive the data. Such VLAN groupings may be a kind of "sub-networks" in the wider network.

5 illustrates the organization of the IRC address table 82. The IRC address table 82 includes an array of 4096 entries. The first "n" entries 92 are considered "empty entries" and have addresses from "0" to "n-1". The remaining entries 94 are considered "heap entries" and have addresses from "0" to "4095". Each table entry includes a 72-bit address entry field and a 12-bit "next pointer" field.

FIG. 6 illustrates the configuration of each 84-bit table entry shown in FIG. The hit bit is used for entry address " aging " to remove from the address table 82 entries that have not been used for a predetermined time. Static bits are used to prevent deletion of address entries. The traffic capture bit identifies the traffic capture source and destination MAC addresses for monitoring the MAC talking with the handling queue 68.

The VLAN index field is a 6-bit field used to refer to a 12-bit VLAN identifier (ID). The VLAN index-VLAN ID table 86 shown in FIG. 4 includes mapping combinations. The switch 12 receives both tagged and untag frames. When the switch 12 receives data tags that are untagged, i.e. without VLAN tag information, the IRC 40 sets a VLAN index based on the receiving port of the received frame. Assignment is made from the index table 88. The VLAN index-ID table 86 and the VLAN port-index table 88 are located in configuration and status registers 52. However, in an alternative configuration, the tables 86 and 88 may be located inside the IRC 40.

The port vector is a 15-bit field, which provides a transport descriptor for the vector identifying the port (s) to which the frame should be transmitted.

The MAC address field is a 48-bit field, which contains all the addresses for the source address and the destination address. The addresses may be unicast, multicast, or broadcast. Individual / group (I / G) bits are also included in the MAC address field.

In an exemplary embodiment of the present invention, host CPU 32 functions as a handling entity and is connected to the IRC 40 via the CPU IF 50. Alternatively, a handling MAC may be associated with the CPU IF 50 to operate as a handling entity.

The host CPU 32 is responsible for initializing the address table 82 values. Upon powering up, the host CPU 32 loads values into the address table 82 based on the network configuration including VLAN configurations. The IRC 40 uses specific fields of the address table 82 to determine frame transmission when frames are received at the switch 12. More specifically, the IRC 40 searches the address table 82 using the engines 200-230 for frame transmission information, and generates a transmission descriptor for outputting the port vector FIFO 56. do.

As discussed previously, the engines 200-230 are separate logic engines, which can process data frames independently, thereby increasing data throughput compared to systems that process one frame at a time. In other words, each logic engine can process different data frames separately and simultaneously, like other separate logic engines. The operation of each logic engine will be briefly described below.

The ingress rule engine 200 performs various pre-processing functions on the input data frames. For example, the entry rule engine 200 checks to see if the corresponding MAC detects any transmission error when the frame is received. The entry rule engine 200 also examines the received source address to determine if the respective / group (I / G) bits are set. If the I / G bit is set, the entry rule engine 200 processes the frame based on whether the frame was received as an error. That is, when a reception error occurs, the entry rule engine 200 generates a transmission descriptor using a null port vector for discarding the frame. Alternatively, the entry rule engine 200 may forward the error frame to the host CPU 32 to diagnose the error frame.

The entry rule engine 200 also checks the MAC DA of the frame to determine if the frame is passed to the handling entity such as, for example, the host CPU 32. Specifically, the entry rule engine 200 retrieves bridge protocol data units (BPDUs), Generic Attribute Regestration Protocol (GARP) frames, MAC control frames, and physical MAC addresses. The entry rule engine 200 identifies these kinds of frames based on their specific destination address information.

Optionally, the ingress rule engine 200 performs VLAN ingress filtering to prevent the multiport switch 12 from transmission of a frame that does not belong to a VLAN associated with the receive port. The entry rule engine 200 accesses the VLAN member set table, which indicates the VLANs associated with each port and determines whether a particular frame belongs to the VLAN associated with the receiving port. If a frame fails the entry filtering, the entry rule engine 200 generates a transmission descriptor with a null pointer vector without performing SA or DA lookups or egress rule manipulation.

After processing through the entry rule engine 200, the IRC 40 performs the SA and DA searches of the address table 82. The multiport switch 12 must make a relatively fast transmission decision because multiple data frames are simultaneously received via the multiport switch 12. Thus, in an exemplary embodiment of the present invention, a hashing scheme is used to search only a subset of the address entries as described below. The memory structure of Figure 5 provides an indexed array, where a given network address will be assigned to that bin. In other words, each empty entry 96 is configured with reference to a number of table entries (ie, heap entries) 98. Thus, the SA lookup engine 210 performs a search of the address table 82 by first accessing a particular bin 96 specified by a hash key, and then places the corresponding bin to locate the appropriate match. Search the entries internally (ie with reference to it).

Each empty entry 96 is a starting position searched by the SA lookup engine 210 for a particular address within the address table 82. An empty entry does not refer to an address (ie, is empty), but may refer to only one address within the empty entry location or may refer to multiple addresses using a linked list chain structure.

7 is a diagram illustrating empty entries referencing a different number of table entries. Each of the empty entries 96 and heap entries 98 includes a 72-bit address entry and a 12-bit "next pointer" field. The "next pointer" field associated with the empty entry 96 identifies the next entry location of the chain of linked list addresses. For example, bin 3 96d in FIG. 7 has no table entries associated with it. In this case, the contents of the 72-bit entry are garbage values, and the corresponding "next pointer" field of the bin has a value of "1", indicating that there is no entry of that bin. If the bin is empty 1, it contains a single table entry, which stores the switching logic data for a single address of its address entry field, and stores a value "0" in the "next pointer", which is the chain. Indicates there are no other address entries. However, bin 0 96a refers to four addresses using the "next pointer" field to identify the location of the next entry in the chain. Additional entries 96b-96d of the bin are linked to a linear list and shown in FIG. 7. Thus, the first entry of the bin 0 is stored in the address entry field of the bin entry 96a, and the next entry (heap entry 98a) is the address entry " a of the next pointer field of the bin entry 96a. Is referred to.

The SA lookup engine 210 performs hash searches of the IRC address table 82 to detect entries associated with the source address and the VLAN index of the received data frame. 8 is a block diagram illustrating an exemplary hash function circuit 100 used to couple with the SA lookup engine 210 in accordance with an embodiment of the present invention. The hash function circuit 100 includes an array of AND gates 12, an array of exclusive OR (XOR) gates 104, and a shift register 106. The user-defined hash function stored in the user-programmable register (HASHPOLY) 108 includes a 12-bit value that defines the hash polynomial used by the hash function circuit 100. The hash polynomials used for the hashing function of the present invention are x ¹² + x ¹⁰ + x ⁷ + x ³ + x ² +1, which is 0100 1000 1101 in HASHPOLY, x ¹² + x ¹⁰ + x ⁵ + x ³ + 1 is 0100 0010 1001 in HASHPOLY and x ¹² + x ¹⁰ + x ⁸ + x ⁷ + x ⁴ + x ² +1 is 0101 1001 0101 in HASHPOLY. Assuming that x ¹² is always 1, it is not stored in the HASHPOLY register 108. Other polynomials can be used in HASHPOLY depending on the specific design requirements.

The hash function circuit 100 generates a hash key using the source address of the data packet according to a user-defined hash function. Initially, the IRC controller 82 concatenates the VLAN index and the 16 least significant bits of the source address of the data packet to generate a search key. After the entire search key has been processed, the hash function circuit 100 outputs a 12-bit hash key.

From the 12-bit hash key, the SA lookup engine 210 computes a bin number for searching for the appropriate bin list of the address table 82. More specifically, the SA lookup engine 210 uses the lower POLYEN bits of the hash key to generate the bin number. The bin number is in the range of [0, n-1], where n = 2 ^POLYEN , the value of POLYRN is programmed by the host CPU 32 and stored in the register 110. The hash key output by the hash function circuit 100 is provided to a logic circuit such as, for example, a 12-bit parallel AND gate 111, and in accordance with a polynomial allowance value POLYEN stored in a register 210. The least significant bits of the hash key are optionally output. The field "POLYEN" defines how many bits of hash key was used to generate the bin number. For example, if POLYEN = 5, the SA lookup engine 210 uses the lower 5 bits of the hash key. Thus, the hash key output by the logic circuit 100 is based on masking the 12-bit hash key using the register value POLYEN stored in register 110.

After the bin number has been computed, the SA lookup table engine 210 generates an empty list of specific bins for an address entry whose address and VLAN index matches the source address SA and the VLAN index of the received frame. Search.

If the SA lookup engine 210 detects an address entry whose address and VLAN index match the SA and VLAN index of the frame, the SA lookup engine 210 sets a hit bit for the address entry. If the SA lookup engine 210 does not detect a match and is allowed to "learning", i.e., adding new entries to the address table 82, the SA lookup engine 210 will start from the received frame. The new entry is constructed in the IRC address table 82 using the information of.

After the SA lookup engine 210 is complete and a new entry is added, if necessary, the DA lookup engine 220 may then add an address whose VLAN and its address match the destination address DA and the VLAN index of the frame. The address table 82 is searched for entries. The DA lookup engine 220 uses a 12-bit hash function circuit 100, as illustrated in FIG. 8, to generate a 12-bit hash key. The DA lookup engine 220 generates the hash key in a manner similar to that discussed for the SA lookup engine 210, the difference being that the hash function circuit 100 is the destination for generating the search key and the hash key. It uses address information. The DA lookup engine 220 then uses the lower POLYEN bits of the hash key to compute the bin number of the address table 82. The DA lookup engine 220 then searches for an appropriate empty list for DA / VLAN index matching in the address table 82. If a match is found, the DA lookup engine 220 uses the port vector field of the address entry and passes the port vector field information to an egress rule engine 230. If the DA lookup engine 220 does not detect a DA / VLAN index match, the frame must be "flooded" for all members of the VLAN. In this case, the DA lookup engine 220 is set to indicate that all ports transmit the frame.

After the DA lookup engine 220 generates the port vectors, the advance rule engine 230 receives port vector information according to a reception port number and VLAN ID information. Next, the advance rule engine 230 receives the port vector information. Generates a transport descriptor for the frame.

9 illustrates a configuration of a transport descriptor according to an embodiment of the present invention. According to FIG. 9, the priority class field is a one-bit field, which indicates an output priority queue that must be located, for example, the frame pointer at high or low priority.

The port vector field is a 15-bit field, which identifies each port (s) that should receive the data frame for transmission to its destination address. Bit 0 of the port vector field corresponds to port 0 (handling port), bits 1-12 individually correspond to MAC ports 1-12 (10/100 Mb / s ports), Bit 13 corresponds to the gigabit port 24 and bit 14 corresponds to the expansion port 30.

The untagged set field is a 4-bit field, which indicates which ports should remove VLAN tag headers before sending frames. The untagged set is obtained from an untagged set table. The Rx port is a 4-bit field, which indicates the port on which the frame is received.

The VLAN ID field is a 12-bit field, which indicates the VLAN identifier associated with the frame. The opcode is an 11-bit field, which contains instructions on how the frame should be changed before transmission and information that the host CPU 32 can use to process a frame from the handling queue. The frame pointer is a 13-bit field, which contains the location of the frame stored in the external-memory 36.

Once the necessary transmission information is obtained, the advance rule engine 230 outputs a transmission descriptor to the port vector FIFO 56 for queuing as shown in FIG.

TRUNKING function

As described above, the multiport switch 12 has 12 ports capable of 10/100 Mb / s operation. Trunking is a technique that treats two or more point-to-point connections between the same two devices as a single network link. Trunking allows the multiport switch 12 to trunk between the two end devices, for example two network stations, two switches, or a higher bandwidth path between two devices, such as a server and a switch. Acquisition by linking multiple ports forming a transmission path.

For example, consider that four ports on the multiport switch 12 are designed for a 100 Mb / s data rate, and the trunking arrangement links the four ports together to form a single trunk. As a result, the trunk can transmit / receive data over the four ports, causing a 400 Mb / s link between the two end devices.

Through the embodiment of the present invention, the multiport switch 12 may support three independent trunks, and each independent trunk may support two to four ports. In this embodiment, twelve 10/100 Mb / s ports on the multiport switch 12 are separated into three trunk blocks, as shown in FIG. In FIG. 10, the first trunk block, trunk 1 has ports 1 to 4, the second trunk block, trunk 2 has ports 5 to 8, and the second trunk block, trunk 3 has ports 9 to 12. do. Within the trunk block, two to four adjacent ports will be combined into a single trunk.

10 illustrates trunk member coupling for twelve 10/100 Mb / s according to a preferred embodiment of the present invention. In FIG. 10, "T" indicates that the port is included in the trunk, and "-" indicates that the port is not included in the trunk, that is, can be used as an independent port. As described above in this embodiment, two to four adjacent ports may be combined to form a single trunk. For example, referring to FIG. 10, ports 1 and 2 can be combined to form the two-link trunk shown in entry A. However, because ports 1 and 3 are not adjacent to each other, they cannot be combined to form a two-link trunk.

In another embodiment, the multiport switch 12 will include fewer or more ports in a single trunk, up to the maximum number of ports of the multiport switch 12. Further, in other embodiments, the multiport switch 12 will be configured without limitation in that the ports can be linked to each other. For example, ports 1, 3, 5, 7 and 9 can be combined into a 5-link trunk.

The host CPU 32 establishes a particular trunk configuration on the basis of specific network requests, for example based on the end devices requesting a data link with a bandwidth of 100 Mb / s or more. Initially, the host CPU 32 assigns ports to specific trunks by setting trunk control bits of the respective port IRC control registers 114a through 114l, as shown in FIG. In accordance with an embodiment of the invention, the multiport switch 12 includes one port IRC control register 114 for twelve 10/100 Mb / s ports. In another configuration, a single register can be used to store the twelve 10/100 Mb / s ports.

4, each port IRC control register 114 has two trunk control bits: trunk bit and trunk_active bit. A series of trunk bits indicates that the corresponding port is a port of the trunk. A series of trunk_active bits indicates that the corresponding port is an active port of the trunk.

Table 1 below summarizes the various combinations of trunk control bits and how frames are transmitted based on the combinations.

trunk Trunk_active 0 X The port is not in the trunk. Frames destined for that port will not be retransmitted to another port. One 0 The port is part of the trunk but is not active because the link failed. Frames destined for the port will be retransmitted to another port in the trunk. One One The port is the active part of the trunk. Frames may be sent from the port.

In Table 1, if the trunk bit is "0", the corresponding port is not part of the trunk, and frames destined for the port will not be retransmitted to another port, regardless of the trunk_active bit. When the trunk bit is "1" and the trunk_active bit is "0", the corresponding port will not be active due to part of the trunk, or link failure. Frames destined for the port will be retransmitted to another port in the trunk. When the trunk bit is "1" and the trunk_active bit is "1", the corresponding port is the active part of the trunk and frames can be transmitted from the port, as described in more detail below.

Advantageously, using the port IRC control registers 114a through 114l to store trunking information allows the present invention to support trunking without specific trunking information in the IRC address table 82. In addition, the use of 2 bits per port, i.e., the use of trunk and trunk_active bits, representing trunk members, means that the host CPU 32 is downlink / restored or the host CPU 32 is configured for network trunking. It is possible to reconfigure the trunk without changing the IRC address table 82 when changing. For example, consider the host CPU 32 removing port 2 as an active port on trunk 1. The host CPU 32 performs the removal by deleting the trunk_active bit in the port IRC control register 114b.

As described above, when a frame is received, the IRC 40 passes through the entry rule engine 200, the SA lookup engine 210, the DA lookup engine 220, and the advance rule engine 230, respectively. Process the frame with. After the DA lookup engine 220 completes the DA lookup, the advance rule engine 230 receives and inspects the port vector information, and the port from the port IRC control register 114 where the frame is part of a trunk. Determine whether it is transmitted through. When the frame is transmitted through a trunk port, the advance rule engine 230 determines a particular transmission port in the trunk through which the frame is transmitted.

11 is a flowchart illustrating a method of generating frame transmission information associated with trunking. In step 200 of FIG. 11, the advance rule engine 230 receives the port vector information and the reception port information from the DA lockup engine 220. Next, in step 202, the advance rule engine 230 compares the port vector information with the information stored in the corresponding IRC port control register 114. The advance rule engine 230 determines whether the transmission port is part of a trunk. That is, the advance rule engine 230 examines the trunk bit in each port IRC control register 114 corresponding to the port identified by the port vector.

If all of the transport ports are not part of a trunk, i.e. when the trunk bits are all "0", then in step 204 the outgoing rule engine 230 outputs a transmission descriptor to the port vector FIFO 56. However, when the transport bit is part of a trunk, especially if the trunk bit is "1", the outgoing rule engine 230 masks out all the bits in the port vector corresponding to the trunk ports in step 206. mask out).

Next, in step 208, the advance rule engine 230 performs a trunk mapping operation to determine the port to which the frame is transmitted. According to the embodiment shown in FIG. 12, the trunk mapping logic includes an exclusive OR (XOR) gate 120. According to FIG. 12, the trunk mapping logic receives two least significant bits of (SA), (DA) of the frame, and successive XOR bits that produce a two bit output. That is, the trunk mapping logic XORs the least significant bits of (SA), (DA) of the frame, and XORs the second least significant bit of (SA), (DA) of the frame. The advance rule engine 230 selects one of the ports in the trunk to transmit the data based on the 2-bit output.

According to the embodiment of FIG. 12, the output bit pattern " 00 " from the XOR gate 120 corresponds to the first port in the trunk block. The output bit patterns " 01 ", " 10 " and " 11 " respectively correspond to the second to fourth ports in the trunk block.

For example, the port vector contains information indicating that the frame is transmitted on port 2, that is, bit 2 of the 15-bit is set, and port IRC control register 2 114b indicates that port 2 is trunk 1; Consider the case of indicating that it is an active member of, i.e., both trunk and trunk_active bits are "1". Also consider that the two least significant bits of the destination address of the received frame are "10". Referring to FIG. 12, the advance rule engine 230 XORs "1" and "0", that is, LSBs of the SA and DA through the XOR gate 120 and outputs "1". The advance rule engine 230 XORs "0" and "1", that is, the second LSBs of the SA and the DA through the XOR gate 120 and outputs "1". Thus, the output of the XOR gate 120 in the example is " 11 ". In this case, the advance rule engine 230 selects the fourth port of trunk 1, that is, port 4, as shown in FIG.

In other configurations, other trunk mapping functions may be used to determine the transport port that transmits the data frame. Advantageously, the particular trunk mapping function used in the present invention optimizes the efficient data transfer rate between the two end devices by distributing the transmission of data frames relatively equally between the ports in the trunk. Also, in configurations where more than four ports are included in a single trunk, the trunk mapping function used will require more bits than the two bits used to select the trunk port. For example, if eight ports were included in the trunk, a three bit output would be required to select an output port among the eight ports.

Next, in step 210, the advance rule engine 230 determines whether the port selected in step 208 is an active port of the trunk. That is, the exit rule engine 230 is the trunk bit of the port IRC control register 114 for the port selected in step 208 is " 1 " indicating that the port is part of the trunk, and the trunk_active Determines whether a bit is "1" indicating that the port is an active link in the trunk.

If the determination at step 210 is no, the advance rule engine 230 selects another port in the same trunk at step 212. According to this embodiment, the advance rule engine 230 selects the next higher port in the trunk block, as indicated by the arrows in FIG. For example, if a third port in the trunk is selected in step 208 and the exit rule engine 230 determines in step 210 that the selected port is not an active member of the trunk, the exit rule engine 230 selects a fourth port in the trunk. The advance rule engine returns to step 210 and repeats the process until the selected port is an active member of the trunk. For example, if the fourth port of the trunk block is selected in step 212 and the fourth port is not an active member of the trunk, then the exit rule engine 230 may be configured to use the first port of the trunk block. Will choose. In another embodiment of the present invention, another method of selecting another port may be employed, for example, selecting the next lower port in the trunk block when the selected port is not an active link in the trunk.

After the active port in the trunk is selected, in step 214 it is checked whether the data frame was received at a trunk fork that is part of the same trunk to which the frame is sent. That is, the advance rule engine 230 checks the contents of the port IRC control register 114 corresponding to the receiving port where the frame is received to determine whether the trunk bit is set. If the determination at step 214 is no, then the advance rule engine 230 outputs a transfer descriptor to the port vector FIFO 56 at step 218. If the determination at step 214 is YES, then the advance rule engine 230 masks at step 216 all the bits in the port vector corresponding to the port (s) contained in the same trunk as the receiving port. Let out. In this way, the exit rule engine 230 confirms that data frames received at the trunk port are not transmitted on the same trunk. Advantageously, this reduces the processing time associated with sending the data frame back to its source.

Next, the advance rule engine 230 includes the port vector to the port vector FIFO 56 and outputs a transmission descriptor. The flowchart shown in FIG. 11 can also be applied to data frames received by the multiport switch 12. However, when the host CPU 32 initiates the transmission, the IRC 40 does not change the port vector information generated by the host CPU 32, thereby performing the trunking algorithm shown in FIG. Evade.

A system and method for trunking in a network interface device have been disclosed. An advantage of the present invention is that the multiport switch 12 supports trunking without storing specific trunking information in the address table 82, thereby not only reducing the time taken to search the address table 82. The size of the address table 82 is reduced. Another advantage of the present invention is that trunking changes are performed quickly and efficiently, without reconfiguration of the address table 82, thereby reducing potential network downtime.

In the above disclosure, preferred embodiments of the invention are disclosed, but it is to be understood that the invention is capable of modifications and variations within the scope of the invention as expressed below, and that they may be used in other combinations and environments.

Claims (18)

A multiport switch for controlling the transmission of data frames between stations and supporting trunking, the multiport switch comprises: A table for storing address information and data transfer information; And a decision making engine, the decision making engine: Search the table to identify the port on which the data frame is sent; Without referring to the table, it is determined whether the identified port is part of a trunk, And when the identified port is part of a trunk, determines a transmission port for transmitting the data frame. 2. The multiport switch of claim 1, wherein the determination execution engine performs a trunk mapping function and outputs a value indicating the transmission port. 3. The method of claim 2, wherein the decision making engine is further configured to generate data transmission information; And change the data transmission information based on the output from the trunk mapping function. 3. The trunk mapping function of claim 2, wherein the trunk mapping function is: And a secondary OR gate configured to receive a predetermined number of least significant bits of both the source address and destination address of the data frame and output the result. The engine of claim 4 wherein the decision making engine is: Mask out bits in the data transmission information corresponding to ports that are part of the trunk; And set a bit in said data transmission information indicative of said transmission port. 6. The engine of claim 5 wherein the decision making engine is: And when said data frame is received at a trunk port, modifying said data transmission information to ensure that said data frame is not sent to a port in the same trunk as said trunk port. The method of claim 1, wherein the multiport switch is: And a memory configured to store trunking information for each of the individual ports, wherein the determination execution engine is configured to determine whether the identified port is part of a trunk based on the contents of the memory. switch. 8. The apparatus of claim 7, wherein the memory is: A trunk field indicating whether the port is a trunk port; And a trunk active field indicating whether the port is an active part of a trunk. In a multiport switch adapted to control the communication of data frames between stations and to support trunking, the multiport has an address table for storing address entries, the method comprising: generating data transmission information; Receiving information from a data frame; Retrieving the address table for data transmission information based on the received information; Determining whether the data frame is transmitted through a port that is part of a trunk; When the frame is transmitted through a port that is part of a trunk, generating a value indicating a transmission port for transmitting the data frame without referring to the address table. How to. The method of claim 9, wherein said generating step: And performing a trunk mapping function and outputting the value representing the transport port. The method of claim 10 wherein the method is: Modifying the data transmission information based on the output from the trunk mapping function. 11. The method of claim 10, wherein the trunk mapping function is: XORing a predetermined number of least significant bits of both the source address and the destination address of the data frame and outputting a result; Mapping the result to a value representing the transmission port. The method of claim 12 wherein the method is: Masking out bits in data transmission information corresponding to ports that are part of the trunk; And setting a bit in said data transmission information indicative of said transmission port. The method of claim 13, wherein the method is: Modifying the data transmission information when the data frame is received on a trunk port to assure that the frame is not transmitted on a port in the same trunk as the trunk port. How to generate transmission information. In a multiport switch adapted to control the communication of data frames between stations and to support trunking, the multiport switch comprises: A table for storing address information and data transfer information; A plurality of programmable registers corresponding to the ports of the multiport switch, and each programmable register configured to store trunking information for one of the respective ports; And a decision making engine, wherein the decision making engine: Search the table to generate data transmission information for a data frame, Determining whether the data frame is transmitted through a trunk port based on the data transmission information and the contents of a plurality of programmable registers, And when the frame is transmitted through a trunk port, generate a value indicating a transmission port for transmitting the data frame. The method of claim 15, wherein the multiport switch is: And an exclusive OR gate configured to receive two least significant bits of both the source address and the destination address of the data frame to produce a two-bit output, wherein the decision making engine is configured to transmit the transmission port based on the two-bit output. Multiport switch, characterized in that to generate a value representing. 17. The engine of claim 16 wherein the decision making engine is: Mask out bits in data transmission information corresponding to ports that are part of the trunk, And setting a bit in data transmission information indicating said transmission port. 16. The method of claim 15, wherein the trunking information is: A trunk field indicating whether the port is a trunk port; And a trunk active field indicating whether the port is an active part of a trunk.