KR20010088207A - Method of forming composite dielectric film of tantalum oxide and titanium oxide - Google Patents
Method of forming composite dielectric film of tantalum oxide and titanium oxide Download PDFInfo
- Publication number
- KR20010088207A KR20010088207A KR1020000012305A KR20000012305A KR20010088207A KR 20010088207 A KR20010088207 A KR 20010088207A KR 1020000012305 A KR1020000012305 A KR 1020000012305A KR 20000012305 A KR20000012305 A KR 20000012305A KR 20010088207 A KR20010088207 A KR 20010088207A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- tantalum oxide
- oxide film
- titanium
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
Abstract
Description
본 발명은 탄탈륨산화막-티타늄산화막 복합유전막 형성방법에 관한 것으로서, 보다 상세하게는 반도체 커패시터 또는 트랜지스터에 이용되는 유전막의 형성방법에 관한 것이다.The present invention relates to a method of forming a tantalum oxide film-titanium oxide composite dielectric film, and more particularly, to a method of forming a dielectric film used in a semiconductor capacitor or a transistor.
반도체 집적회로에서 사용되는 유전막은 박막의 형태로서 반도체 커패시터와모스트랜지스터에 주로 사용되고 있으며, 벌크 상태에서의 유전적 특성을 유지하면서도 안정된 절연적 특성을 유지하여야 한다. 유전적 특성으로서는 박막 상태로 큰 캐패시턴스를 확보하는 것이며, 절연적 특성으로서는 누설전류적 특성을 의미하게 된다. 그러나, 일반적으로는 유전막의 유전상수가 커지면 캐패시턴스는 증가하지만, 유전막내에서의 전기장(electric field)의 크기가 커져 유전막의 누설전류 특성은 취약해지는 경우가 있다. 예를 들어, 실리콘 산화막 또는 ONO막(실리콘산화막/실리콘질화막/실리콘산화막) 등은 비록 유전상수가 3.9 내지 7 정도에 불과하지만 매우 우수한 누설전류 특성을 가지고 있으며, 반면에 탄탈륨산화막 (Ta2O5), BST막 등은 유전상수가 25 내지 400 정도로 매우 높지만 복잡한 도전 메카니즘을 가지며 누설전류 특성이 매우 취약하다는 단점이 있다.Dielectric films used in semiconductor integrated circuits are mainly used in semiconductor capacitors and MOS transistors in the form of thin films, and must maintain stable insulating properties while maintaining dielectric properties in bulk. The dielectric property is to secure a large capacitance in a thin film state, and the insulating property means a leakage current property. However, in general, as the dielectric constant of the dielectric film increases, the capacitance increases, but the magnitude of the electric field in the dielectric film increases, so that the leakage current characteristic of the dielectric film may be weak. For example, silicon oxide film or ONO film (silicon oxide film / silicon nitride film / silicon oxide film) and the like have very good leakage current characteristics, although the dielectric constant is only about 3.9 to 7, whereas tantalum oxide film (Ta 2 O 5 ), BST film, etc. have a very high dielectric constant of about 25 to 400, but has a complicated conduction mechanism and a very weak leakage current characteristic.
그러나 반도체 커패시터나 모스 트랜지스터의 경우, 큰 캐패시턴스를 확보하기 위하여 유전막을 초박막화하는 것으로서, 이러한 유전적 특성이나 절연적 특성을 모두 만족시킬 것을 요구하고 있으며, 이를 위해 유전상수와 누설전류 특성의 적절한 타협(trade-off)이 요구되는 것이다. 이러한 요구에 부응하여 탄탈륨산화막을 유전막으로 사용하는 방법이 소개되어지고 있다.However, in the case of semiconductor capacitors or MOS transistors, the dielectric film is made ultra thin in order to secure a large capacitance, and it is required to satisfy both these dielectric and insulating characteristics, and for this, proper compromise of dielectric constant and leakage current characteristics is required. (trade-off) is required. In response to this demand, a method of using a tantalum oxide film as a dielectric film has been introduced.
탄탈륨산화막은 유전상수가 약 25 정도이나 누설전류 특성이 취약한 재료이며, 이러한 누설전류 특성의 취약점을 보완하기 위해 종래로부터 오존(O3)처리, 건식 산소 어닐링처리 등을 수행하여 산화력을 강화하거나 잔류 불순물의 제거와 결정화등을 꾀하였으나, 이들은 실제로 하부계면에 유전상수가 낮은 실리콘산화막등을 형성하게 되므로 유효 유전상수는 10 정도 수준으로 낮아지게 된다는 문제점이 있다.Tantalum oxide film is a material with a dielectric constant of about 25 but weak leakage current characteristics. To supplement the weakness of the leakage current characteristics, the tantalum oxide film is conventionally subjected to ozone (O 3 ) treatment, dry oxygen annealing treatment, etc., to enhance oxidative power or to remain. Although impurities have been removed and crystallized, they have a problem in that the effective dielectric constant is lowered to about 10 since the silicon oxide film having a low dielectric constant is actually formed on the lower interface.
본 발명의 목적은 안정된 누설전류 특성을 확보하면서 동시에 탄탈륨산화막 본래의 유전상수를 크게 향상시킬 수 있는 탄탈륨산화막-티타늄산화막 복합유전막 형성방법을 제공하는 데 있다.It is an object of the present invention to provide a tantalum oxide film-titanium oxide composite dielectric film formation method which can secure a stable leakage current characteristic and at the same time significantly improve the original dielectric constant of the tantalum oxide film.
도 1은 본 발명의 일 실시예에 따른 복합유전막 형성과정을 나타내는 공정 흐름도이다.1 is a process flow diagram illustrating a process of forming a composite dielectric film according to an embodiment of the present invention.
도 2 내지 도 7은 도 1에 따른 본 발명의 복합유전막 형성과정을 나타내는 공정단면도들이다.2 to 7 are cross-sectional views illustrating a process of forming the composite dielectric film of the present invention according to FIG. 1.
※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing
10 ; 하부층 12 ; 전처리막10; Lower layer 12; Pretreatment membrane
14 ; 탄탈륨산화막 16 ; 티타늄막14; Tantalum oxide film 16; Titanium film
18 ; 복합유전막 20 ; 상부막18; Composite dielectric film 20; Top film
상기 본 발명의 목적을 달성하기 위한 본 발명에 따른 탄탈륨산화막-티타늄산화막 복합유전막 형성방법은, 도전성의 하부막을 준비하고, 상기 하부막상에 유전막 증착전 전처리막을 형성한 후, 상기 전처리막상에 탄탈륨산화막을 형성하고, 이어서 상기 탄탈륨산화막상에 원자층 증착법에 의해 티타늄막을 형성한 후, 산소분위기하에서 열처리를 하여 탄탈륨산화막-티타늄산화막의 복합유전막을 형성하고, 상기 복합유전막상에 도전성의 상부막을 형성함으로써 달성된다.In the method for forming a tantalum oxide film-titanium oxide composite dielectric film according to the present invention for achieving the object of the present invention, after preparing a conductive lower film, and forming a pretreatment film before the dielectric film deposition on the lower film, a tantalum oxide film on the pretreatment film And then forming a titanium film on the tantalum oxide film by atomic layer deposition, followed by heat treatment under an oxygen atmosphere to form a composite dielectric film of tantalum oxide film-titanium oxide film, and forming a conductive upper film on the composite dielectric film. Is achieved.
상기 본 발명의 복합유전막은 반도체 커패시터의 유전막 또는 모스(MOS) 트랜지스터의 게이트절연막으로 사용되는 것으로서, 상기 하부막 및 상부막은 금속, 금속산화막, 금속질화막, 금속질화산화막 및 실리콘 기판과 같은 도전성 재질이 사용될 수 있다.The composite dielectric film of the present invention is used as a dielectric film of a semiconductor capacitor or a gate insulating film of a MOS transistor. The lower film and the upper film are made of a conductive material such as a metal, a metal oxide film, a metal nitride film, a metal nitride oxide film, and a silicon substrate. Can be used.
한편, 상기 산소분위기하에서 열처리를 수행하기 전에 불활성 분위기하에서 열처리공정을 더 수행하여 탄탈륨산화막 내부로 티타늄의 확산을 효과적으로 촉진할 수 있으며, 상기 탄탈륨산화막을 형성하는 단계, 상기 탄탈륨산화막상에 원자층 증착법에 의해 티타늄막을 형성하는 단계, 산소분위기하에서 열처리를 하여 탄탈륨산화막-티타늄산화막의 복합유전막을 형성하는 단계는 적어도 2회이상 반복하여 수행함으로써, 탄탈륨산화막내로의 티타늄의 도핑 정도 및 티타늄산화막의 형성 정도를 균일하게 할 수도 있다.Meanwhile, before the heat treatment is performed under the oxygen atmosphere, the heat treatment process may be further performed in an inert atmosphere to effectively promote the diffusion of titanium into the tantalum oxide film, and the tantalum oxide film may be formed. The atomic layer deposition method may be performed on the tantalum oxide film. Forming the titanium film by heat treatment and forming the composite dielectric film of the tantalum oxide film-titanium oxide film by performing heat treatment under an oxygen atmosphere by repeating at least two or more times, and thus doping the titanium into the tantalum oxide film and forming the titanium oxide film. It can also make it uniform.
본 발명에 따르면, 탄탈륨산화막에 티타늄산화막을 첨가함으로써 탄탈륨산화막 자체 보다도 훨씬 증가된 유전율을 확보할 수 있으며, 유전막을 초박막으로 실현할 수 있기 때문에 높은 캐패시턴스를 확보할 수 있으며, 후속의 산소 어닐링공정에 의해 안정된 누설전류 특성을 확보할 수 있다.According to the present invention, by adding a titanium oxide film to the tantalum oxide film, it is possible to secure a much higher dielectric constant than the tantalum oxide film itself, and to achieve a high capacitance because the dielectric film can be realized as an ultra-thin film, and by a subsequent oxygen annealing process Stable leakage current characteristics can be ensured.
이하, 본 발명의 실시예에 대하여 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 일 실시예에 따라 반도체 커패시터의 유전막 형성과정을 나타내는 공정 흐름도이며, 도 2 내지 도 7은 도 1에 따른 본 발명의 복합유전막 형성과정을 나타내는 공정단면도들이다. 비록 본 실시예가 반도체 커패시터의 유전막 형성에 관한 것이지만, 반도체 기판상에 유전막을 개재하여 게이트전극이 형성되는 모스 트랜지스터의 유전막에도 동일한 원리가 적용될 수 있음은 물론이다.1 is a process flow diagram illustrating a process of forming a dielectric film of a semiconductor capacitor according to an embodiment of the present invention, and FIGS. 2 to 7 are process cross-sectional views illustrating a process of forming a composite dielectric film of the present invention according to FIG. 1. Although the present embodiment relates to the formation of the dielectric film of the semiconductor capacitor, the same principle can be applied to the dielectric film of the MOS transistor in which the gate electrode is formed via the dielectric film on the semiconductor substrate.
도 1 내지 도 7을 참조하여 본 발명의 유전막 형성과정을 살펴본다. 먼저, 하부전극(10)을 형성한다(단계 S10). 하부전극(10)은 일반적인 반도체 제조공정에 따라 제작되며, 특히 반도체 메모리장치에서 반도체기판 내의 불순물영역과 접속되는 스토리지전극일 수 있으며, 금속, 금속산화막, 금속질화막, 금속산화질화막 등의 도전성 재질로 형성하며, 도전성 실리콘 재질로 형성할 수도 있다.A process of forming the dielectric film of the present invention will be described with reference to FIGS. 1 to 7. First, the lower electrode 10 is formed (step S10). The lower electrode 10 may be manufactured according to a general semiconductor manufacturing process. In particular, the lower electrode 10 may be a storage electrode connected to an impurity region in a semiconductor substrate in a semiconductor memory device. It may be formed, and may be formed of a conductive silicon material.
이어서, 하부전극(10)상에 유전막을 증착하기 전에 전처리를 수행하여 전처리막을 형성한다(단계 S20). 상기 전처리막(12)은 통상적으로 RTP(Rapid Thermal Process) 또는 CVD(Chemical Vapor Deposition)법으로 증착될 수 있으며, 일반적인 조성은 실리콘 나이트라이드(SiNx), 실리콘 옥사이드(SiOx), 실리콘 옥시나이트라이드(SiOxNy) 등이다. 상기 RTP 방법으로써는 암모니아 분위기에서 500 내지 900 ℃ 사이의 온도범위에서 수행되는 RTN 방법 또는 산소(O2), 산화질소(N2O) 등의 분위기하에서 500 내지 900 ℃의 온도범위에서 수행되는 RTO 방법 등이 있으며, 이들 방법을 복합하여 사용할 수도 있다. 이때 활성화 에너지를 낮추기 위하여 플라즈마, 광, 자외선 등의 에너지를 이용할 수 있다.Subsequently, before the dielectric film is deposited on the lower electrode 10, pretreatment is performed to form a pretreatment film (step S20). The pretreatment layer 12 may be typically deposited by a rapid thermal process (RTP) or chemical vapor deposition (CVD) method, and the general composition is silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride ( SiO x N y) and the like. As the RTP method, an RTN method performed at a temperature range of 500 to 900 ° C. in an ammonia atmosphere or an RTO performed at a temperature range of 500 to 900 ° C. under an atmosphere of oxygen (O 2 ), nitrogen oxide (N 2 O), or the like. Methods, and these methods may be used in combination. In this case, in order to lower the activation energy, energy such as plasma, light, or ultraviolet light may be used.
이어서, 상기 전처리막(12)상에 유전막(14)을 증착한다(단계 S30). 상기 유전막(14)은 탄탈륨산화막이며, CVD법에 의해 형성한다. 탄탈륨산화막의 증착시 사용되는 전구체로서는 Ta(OC2H5)5와 같은 메탈 알콕사이드(Metal Alkoxide)나 메탈 베타-디케토네이트(Metal Beta-Deketonate)와 같은 유기금속물들이나 TaCl5와 같은 메탈 할라이드 등이 사용될 수 있다. 일반적으로 전구체를 기체상태로 만든 후 운반가스를 이용하여 반응기내 또는 반응기의 입구에서 산소와 반응시켜 상기 전처리막(12)상에 탄탈륨산화막을 증착시키며, 증착온도는 350 내지 550 ℃, 증착압력은 100 mTorr 정도 이상으로 유지한다. 상기 반응기의 형태는 단일 웨이퍼에 대하여 공정을 수행하는 매엽식 또는 복수개의 웨이퍼에 대하여 함께 공정을 수행하는 배치식이 사용될 수 있다.Subsequently, a dielectric film 14 is deposited on the pretreatment film 12 (step S30). The dielectric film 14 is a tantalum oxide film and is formed by CVD. Precursors used in the deposition of tantalum oxide films include organic metals such as metal alkoxides such as Ta (OC 2 H 5 ) 5 , metal beta-deketonate, and metal halides such as TaCl 5. And the like can be used. In general, the precursor is made into a gaseous state and then reacted with oxygen in the reactor or at the inlet of the reactor using a carrier gas to deposit a tantalum oxide film on the pretreatment film 12, the deposition temperature is 350 to 550 ℃, the deposition pressure is Keep at least 100 mTorr. The type of the reactor may be a sheet-fed process for performing a process for a single wafer or a batch process for performing a process for a plurality of wafers together.
이어서, 상기 탄탈륨산화막의 유전막(14)상에 원자층 증착법(Atomic LayerDeposition;ALD)법으로 티타늄막(16)을 증착한다(단계 S40). 원자층 증착법은 소오스 입력시간(Source input time), 소오스 출력시간(Source output time) 및 사이클(펄싱 및 퍼징을 반복하는 주기)을 조절하여 극박막의 두께를 실현할 수 있는 증착법으로서, 티타늄 원자층 증착공정은 먼저 TMA와 같은 알루미늄 소오스를 이용하여 알루미늄 모노레이어를 형성시킨 후, TiCl4를 주입하여 티타늄을 증착시키고, 알루미늄은 염화알루미늄(AlCl3)의 형태로 퍼징하여 제거함으로써 극박막의 티타늄층을 증착하는 것이다. 증착되는 티타늄의 두께는 후속 열처리공정과 함께 탄탈륨산화막내의 티타늄산화막의 몰%를 결정하는 중요한 요소로 작용하며, 탄탈륨산화막 내에 티타늄산화막의 첨가량은 유전율을 결정짓는 중요한 요소이기 때문에, 원자층 증착법에 의해 증착되는 티타늄막(16)의 두께가 정밀하게 제어해야 한다. 바람직하게는 티타늄막(16)의 두께는 50 Å 이하가 되도록 형성한다.Next, a titanium film 16 is deposited on the dielectric film 14 of the tantalum oxide film by atomic layer deposition (ALD) (step S40). Atomic layer deposition is a deposition method that can achieve ultra-thin film thickness by adjusting source input time, source output time and cycle (period of pulsing and purging). The process first forms an aluminum monolayer using an aluminum source such as TMA, and then deposits titanium by injecting TiCl 4 , and purging and removing aluminum in the form of aluminum chloride (AlCl 3 ) to remove the ultrathin titanium layer. To deposit. The thickness of the deposited titanium is an important factor in determining the mole percent of titanium oxide in the tantalum oxide film with the subsequent heat treatment process. The thickness of the titanium film 16 to be deposited must be precisely controlled. Preferably, the thickness of the titanium film 16 is 50 kPa or less.
이어서, 증착된 상태의 탄탈륨산화막의 전기적 특성, 특히 누설전류 특성의 개선을 위해 산소분위기 하에서 열처리를 수행한다(단계 S50). 열처리 분위기는 오존, 산소, 산화질소 등 산소를 포함한 기체 분위기하에서 진행하며, 열처리의 온도는 500 내지 900℃에서 수행하며, 이때 활성화에너지를 낮추기 위하여 플라즈마, 광, 자외선 등의 에너지를 이용할 수 있다. 따라서, 이러한 열처리를 통하여 티타늄이 탄탈륨산화막으로 확산되면서 동시에 티타늄산화막을 형성하여 유전막 전체의 유전율이 향상된다. 일반적으로 벌크 세라믹공정(bulk ceramic process)에서 탄탈륨산화막에 8 몰%(mol %)의 티타늄산화막이 첨가된 경우 탄탈륨산화막의 유전율이35.4에서 126.2 까지 증가되는 것으로 알려져 있으며, 고주파수(RF) 스퍼터링공정에 의해 티타늄산화막을 5 내지 10 몰% 첨가한 경우 38%의 유전율 증가가 이루어진다는 보고도 알려져 있다.Subsequently, heat treatment is performed under an oxygen atmosphere in order to improve electrical properties, particularly leakage current characteristics, of the tantalum oxide film in the deposited state (step S50). The heat treatment atmosphere is carried out in a gas atmosphere containing oxygen, such as ozone, oxygen, nitrogen oxide, the temperature of the heat treatment is carried out at 500 to 900 ℃, in this case, to lower the activation energy may be used energy such as plasma, light, ultraviolet rays. Therefore, through such heat treatment, titanium diffuses into the tantalum oxide film and simultaneously forms a titanium oxide film, thereby improving the dielectric constant of the entire dielectric film. In general, when 8 mol% (mol%) of titanium oxide is added to a tantalum oxide film in a bulk ceramic process, the dielectric constant of the tantalum oxide film is known to increase from 35.4 to 126.2. It is also known that the dielectric constant increase of 38% when the titanium oxide film is added by 5 to 10 mol%.
한편, 상기 산소 분위기하에서 열처리를 수행하기 전에 불활성 분위기하에서 저온 열처리를 수행함으로써 티타늄이 탄탈륨산화막으로 효과적으로 확산이 이루어질 수 있도록 할 수 있다.On the other hand, by performing a low temperature heat treatment in an inert atmosphere before the heat treatment in the oxygen atmosphere it can be effectively diffused titanium to the tantalum oxide film.
상기 열처리공정에 의하여 티타늄산화막이 소정 몰% 만큼 첨가된 탄탈륨산화막-티타늄산화막의 복합유전막(18)이 형성된다.By the heat treatment process, a composite dielectric film 18 of a tantalum oxide film-titanium oxide film to which a titanium oxide film is added by a predetermined mole% is formed.
이어서, 상기 복합유전막(18)상에 통상의 반도체공정에 따른 상부막(20)을 형성한다. 상부막의 재질은 도전성 재질로서, 전술한 하부막(10)과 같은 재질로 구성할 수 있다.Subsequently, an upper film 20 according to a conventional semiconductor process is formed on the composite dielectric film 18. The material of the upper film is a conductive material, and may be made of the same material as the lower film 10 described above.
한편, 탄탈륨산화막내에 티타늄의 도핑 정도 및 티타늄산화막의 형성 정도를 보다 균일하게 하기 위하여 상기 탄탈륨산화막 증착, 원자층 증착법에 의한 티타늄막 증착 및 열처리공정을 적어도 2회이상 반복하여 수행할 수도 있다.On the other hand, in order to make the doping degree of titanium and the formation degree of the titanium oxide film in the tantalum oxide film more uniform, the tantalum oxide film deposition, the titanium film deposition by the atomic layer deposition method and the heat treatment process may be repeatedly performed at least two times.
이상에서, 커패시터의 유전막으로서의 바람직한 실시예에 대하여 상세히 설명하였지만, 모스 트랜지스터의 게이트절연막으로서의 유전막에 관하여 동일한 원리가 적용될 수 있음은 전술한 바와 같으며, 유전막의 구조도 하부막의 표면형상에 따라 다양하게 예상할 수 있음은 물론이며, 본 실시예들에서 사용되는 막질의 종류 및 치수등에 대하여도 다양하게 선택하여 적용할 수 있다.In the above, the preferred embodiment of the capacitor as the dielectric film has been described in detail, but the same principle may be applied to the dielectric film as the gate insulating film of the MOS transistor, and the structure of the dielectric film may vary depending on the surface shape of the lower film. Of course, it can be expected, it can be variously selected and applied to the type and dimensions of the film quality used in the present embodiments.
본 발명에 의하면, 후속되는 산소 열처리공정에 의하여 유전막의 전기적 특성이 향상되면서도 탄탈륨산화막의 고유 유전율이 감소하지 않고 오히려 상당히 증가되기 때문에 유전막으로서의 유전적 특성 및 절연적 특성을 모두 만족시킬 수 있게 되며, 원자층 증착법에 의해 탄탈륨산화막에 첨가되는 티타늄의 첨가량을 정확히 제어할 수 있게 되어 신뢰성이 향상된 유전막을 구현할 수 있게 되었다.According to the present invention, it is possible to satisfy both the dielectric and insulating properties of the dielectric film because the intrinsic permittivity of the tantalum oxide film is increased rather than decreasing while the electrical properties of the dielectric film are improved by a subsequent oxygen heat treatment process. The atomic layer deposition method can precisely control the amount of titanium added to the tantalum oxide film to realize a dielectric film having improved reliability.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000012305A KR20010088207A (en) | 2000-03-11 | 2000-03-11 | Method of forming composite dielectric film of tantalum oxide and titanium oxide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000012305A KR20010088207A (en) | 2000-03-11 | 2000-03-11 | Method of forming composite dielectric film of tantalum oxide and titanium oxide |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010088207A true KR20010088207A (en) | 2001-09-26 |
Family
ID=19654339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000012305A KR20010088207A (en) | 2000-03-11 | 2000-03-11 | Method of forming composite dielectric film of tantalum oxide and titanium oxide |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010088207A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422565B1 (en) * | 2001-06-12 | 2004-03-12 | 주식회사 하이닉스반도체 | Method of forming a capacitor of a semiconductor device |
| KR100437618B1 (en) * | 2002-05-21 | 2004-06-30 | 주식회사 하이닉스반도체 | METHOD FOR FORMING SEMICONDUCTOR CAPACITOR USING (Ta-Ti)ON DIELECTRIC THIN FILM |
| KR100582415B1 (en) * | 2000-06-28 | 2006-05-23 | 주식회사 하이닉스반도체 | Method of forming a capacitor in a semiconductor device |
| WO2010120954A2 (en) * | 2009-04-16 | 2010-10-21 | Advanced Technology Materials, Inc. | Doped zro2 capacitor materials and structures |
| US9443736B2 (en) | 2012-05-25 | 2016-09-13 | Entegris, Inc. | Silylene compositions and methods of use thereof |
| US10186570B2 (en) | 2013-02-08 | 2019-01-22 | Entegris, Inc. | ALD processes for low leakage current and low equivalent oxide thickness BiTaO films |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930012120A (en) * | 1991-12-17 | 1993-07-20 | 하기주 | Dewatering Device of Latex Waste |
| JPH07263573A (en) * | 1994-03-24 | 1995-10-13 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| KR970054073A (en) * | 1995-12-27 | 1997-07-31 | 김광호 | Method of manufacturing capacitors in semiconductor devices |
| KR19990016401A (en) * | 1997-08-14 | 1999-03-05 | 윤종용 | Capacitor Manufacturing Method of Semiconductor Device for Heat Treatment of Dielectric Film in Hydrogen Atmosphere |
-
2000
- 2000-03-11 KR KR1020000012305A patent/KR20010088207A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930012120A (en) * | 1991-12-17 | 1993-07-20 | 하기주 | Dewatering Device of Latex Waste |
| JPH07263573A (en) * | 1994-03-24 | 1995-10-13 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| KR970054073A (en) * | 1995-12-27 | 1997-07-31 | 김광호 | Method of manufacturing capacitors in semiconductor devices |
| KR19990016401A (en) * | 1997-08-14 | 1999-03-05 | 윤종용 | Capacitor Manufacturing Method of Semiconductor Device for Heat Treatment of Dielectric Film in Hydrogen Atmosphere |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100582415B1 (en) * | 2000-06-28 | 2006-05-23 | 주식회사 하이닉스반도체 | Method of forming a capacitor in a semiconductor device |
| KR100422565B1 (en) * | 2001-06-12 | 2004-03-12 | 주식회사 하이닉스반도체 | Method of forming a capacitor of a semiconductor device |
| KR100437618B1 (en) * | 2002-05-21 | 2004-06-30 | 주식회사 하이닉스반도체 | METHOD FOR FORMING SEMICONDUCTOR CAPACITOR USING (Ta-Ti)ON DIELECTRIC THIN FILM |
| WO2010120954A2 (en) * | 2009-04-16 | 2010-10-21 | Advanced Technology Materials, Inc. | Doped zro2 capacitor materials and structures |
| WO2010120954A3 (en) * | 2009-04-16 | 2011-03-24 | Advanced Technology Materials, Inc. | Doped zro2 capacitor materials and structures |
| US9443736B2 (en) | 2012-05-25 | 2016-09-13 | Entegris, Inc. | Silylene compositions and methods of use thereof |
| US10186570B2 (en) | 2013-02-08 | 2019-01-22 | Entegris, Inc. | ALD processes for low leakage current and low equivalent oxide thickness BiTaO films |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100415538B1 (en) | Capacitor with double dielectric layer and method for fabricating the same | |
| US6387761B1 (en) | Anneal for enhancing the electrical characteristic of semiconductor devices | |
| KR100351056B1 (en) | Method of manufacturing semiconductor device including step of selectively forming metal oxide layer | |
| US6204203B1 (en) | Post deposition treatment of dielectric films for interface control | |
| KR100338110B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| US6355519B1 (en) | Method for fabricating capacitor of semiconductor device | |
| KR20060054387A (en) | Surface preparation prior to deposition on germanium | |
| KR20040077565A (en) | Atomic layer deposition of nanolaminate film | |
| CN100561684C (en) | The formation method of underlying insulation film | |
| KR100507860B1 (en) | Capacitor having oxidation barrier and method for fabricating the same | |
| KR100373159B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR20020083772A (en) | capacitor of semiconductor device and method for fabricating the same | |
| KR20010045961A (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100331270B1 (en) | Forming method of capacitor with TaON thin film | |
| KR100431740B1 (en) | Semiconductor with High-k dielectric layer and Method for fabricating the same | |
| KR20010088207A (en) | Method of forming composite dielectric film of tantalum oxide and titanium oxide | |
| KR20060001048A (en) | Method for forming capacitor of semiconductor device | |
| KR100594207B1 (en) | Method for forming thin film using atomic layer deposition | |
| KR20000042429A (en) | Method for manufacturing ferroelectric capacitor of semiconductor device | |
| KR100382611B1 (en) | Method for forming of capacitor the cell used high-integrated DRAM | |
| KR100624927B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR20010064099A (en) | A new method for forming alumina layer and fabricating method of semiconductor device using the same | |
| KR100231604B1 (en) | Manufacturing method of capacitor of semiconductor device | |
| KR100540476B1 (en) | Method for fabricating capacitor in semiconductor device | |
| KR100557961B1 (en) | Method for forming capacitor of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |