KR20010076782A - Cell Acquisition of Asynchronous CDMA System - Google Patents

Abstract

PURPOSE: A cell scanner of an asynchronous CDMA(Code Division Multiple Access) communication system is provided to construct simple hardware by removing previously phase error components. CONSTITUTION: A complex despreading unit(21) multiplies input data and a spreading code to despread the input data. A delay unit(23,24) delays the in-phase component and the quadature-phase component of the despread data. A multiplication unit(25,26) multiplies the in-phase component of the despread data and the in-phase component of the delayed data, and multiplies the quadature-phase component of the despread data and the quadature-phase component of the delayed data. An integration unit(27) adds two results from the multiplication unit(25,26).

Description

Cell Acquisition of Asynchronous CDMA System

The present invention relates to a code division multiplex access communication system. In more detail, a code having a pilot channel energy calculation block using a delay input for despreading and removing a phase error component to obtain a processing gain is obtained. A cell finder of a split multiplexed communication system.

In general, code division multiplexing (CDMA) communication systems spread and transmit information using a pseudo random number (PN) code, which is a spreading code. Therefore, in order to recover transmission information of the CDMA communication system, the information of the spreading code must be known. The pseudorandom code, which is a spreading code, is generated by a given generation formula in the system, but various kinds of delays occur depending on the distance between the sender and the receiver and the transmission medium. Therefore, in the CDMA communication system, it is necessary to find out the delay information and generate a pseudo pseudorandom code corresponding to the delay to remove the spread signal. In order to know this delay, we use the initial synchronous search function to find the delay time along each path of the code. In addition, it performs a function for extracting the transmission information using the confirmed delay time information. The function necessary in this process is to remove the spreading signal by the pseudo random number code by multiplying the local pseudo random number signal generated by the receiver side with the received signal as a correlator. However, the received signal contains not only the original transmission information and the spread signal information, but also includes a phase error in the transmission process and the reception process. In particular, this phase error must be eliminated when information is sent to the phase.

As a method of removing such a phase error, there is a method of removing a phase error component through asynchronous detection when no phase information is available, such as initial synchronous search. When the phase error component is known, it can be removed by multiplying the phase error component, which is called a synchronous detection method. That is, a function for removing the spreading code component from the received signal and simultaneously removing the phase error component should be included. In order to implement this function, the conventional detection method adds the despread signal from which the spread signal is removed by a given processing gain for asynchronous detection and synchronous detection, and then uses a squarer and a multiplier to remove the phase error. Removed. However, this method has a problem in that the complexity of processing increases as the number of squares and multiplications to be processed increases.

As described above, the CDMA communication system carries information in phase. When the receiver moves without stopping, a change in reception frequency occurs due to a Doppler transition during propagation of radio waves, which affects the phase in which the received information is carried. In addition, this effect also changes the phase of the received signal if there is a mismatch between the transmit and receive frequencies when dropping the radio wave arriving at the receiver to the baseband. When such a phase error occurs, the size of the received signal changes with time. The propagation of the signal to the phase changes the phase probabilistic, which in turn prevents the accurate separation of transmission information.

In general, a CDMA communication system transmits a pilot channel with known information and estimates signal delay and phase error using the pilot channel. The delay signal is despread using the delay estimation information, and the phase error included therein is multiplied by the estimated phase error to remove the effect. Since no information on the phase error is available for the delay estimation in the pilot channel, the phase error included in the despread signal is converted to the energy value through asynchronous detection to delay the delay estimation. .

1 is a block diagram showing such a conventional asynchronous pilot channel energy searcher. The received signal is despread in despreader 11 by receive generation spreading code 12, and the two integrators 13 and 14 despread this despread signal to obtain a processing gain. Integrate the signal for a given period of integration. The integrator 13 integrates the positive phase component, and the integrator 14 integrates the quadrature phase component. The squarer 15 squares the despread signal to change the energy value, and adds the positive phase and quadrature components to the energy value. In this case, if the integral section of the integrator is too long, the integral value may be very small due to the phase error component. Therefore, the integrator 16 that stores the energy value is necessary because the integral section is not too large and the integral is divided. .

In an asynchronous CDMA communication system, there is no synchronization between base stations. In order to exchange information in such a communication system, first of all, the information of the base station to which the terminal belongs. To do this, the information of the spreading code is found in a hierarchical manner. First, the slot boundary is found using the main code. Since the main code is repeatedly transmitted every slot and is not transmitted according to the time interval, a very fast operation must be performed to search for this. We use matched filter structure for this fast code search. Subcodes are generated at the same time as the main code. Since subcodes are spread using different orthogonal codes in each slot using orthogonal codes, the orthogonal codes are searched for all possible codes to find the spreading code group and the frame position. Next, a known pilot channel spread by a spreading code is searched to find a spreading code by searching all spreading codes included in a spreading code group. That is, the slot boundary is identified by the main code, the code group and the frame boundary are identified by the subcode, and the spreading code is found by searching the spreading codes included in the spreading code group.

What is needed in this process is that it is necessary to multiply and integrate the input signal through the correlator for several subcodes simultaneously. In addition, it is necessary to multiply and integrate multiple spreading codes through the correlator for the spreading codes included in the spreading code group at the same time as in the subcode. The despreading value is then integrated over a given integration period to obtain the proper signal-to-noise ratio. And in order to remove the phase error included in the square and quadrature components squared and added to make the energy value. In this process, it is necessary to use several squares to calculate the energy value.

As described above, since the conventional method performs many square and multiplication operations, the complexity increases when the number of squares and multiplications to be processed increases.

Accordingly, the present invention has been made to solve the problems of the prior art as described above, by multiplying the despread signal by one time signal and the following despread signal to remove the phase error commonly included in the two signals, When multiplying using a multiplier, only the multiplication sign is used to provide a cell searcher that can be easily implemented and reduced in computation.

1 is a block diagram of a conventional asynchronous pilot channel energy calculation block;

2 is a block diagram of a pilot channel energy calculation block using a delay input according to an embodiment of the present invention;

3 is a block diagram of a pilot channel energy calculation block using delay input according to another embodiment of the present invention;

4 is a block diagram of a searcher for cell recognition in an asynchronous code division multiplexing communication system;

5 is a control flowchart of a code finder for cell recognition;

6 is an integrator output control diagram,

7 is a flowchart illustrating a method of generating a scrambling code.

In order to achieve the above object, the cell search apparatus of the asynchronous code division multiplexing communication system of the present invention includes spreading code generation means for generating a plurality of spreading codes, and code selection for sequentially selecting one of the plurality of spreading codes. Means, energy calculation means for detecting channel energy of the selected code, maximum value detection means for detecting a maximum value of channel energy detected by the energy calculation means, and a code of the maximum value or maximum value detected by the maximum value detection means. It characterized in that it comprises a storage means for storing the index.

In addition, the energy calculation means according to the present invention comprises: complex despreading means for despreading the input data by multiplying the input data and a spreading code; Delay means for delaying the normal phase component and the quadrature phase component of the despread data output from the complex despreading means; The normal phase component of the despread data output from the complex despreading means and the normal phase component of the despread data delayed by the delay means are multiplied, and the quadrature phase component of the despread data output from the complex despreading means and the delay means. Multiplication means for multiplying quadrature components of the delayed despread data in the apparatus; And integration means for adding two result values of the multiplication means.

Hereinafter, with reference to the accompanying drawings will be described in more detail "cell searcher of the asynchronous code division multiplexing communication system" according to an embodiment of the present invention.

2 is a block diagram of a pilot channel energy calculation block using a delay input according to an embodiment of the present invention. The input positive and quadrature signals are a mixture of base station transmission channels and other base station transmission signals. Therefore, in order to estimate the delay signal, the search is started at any spreading code position at any time. Therefore, the spreading code generator 22 generates the code at an arbitrary position. The generated code is input to the complex despreader 21 together with the input signals I and Q and despread, whereby the spreading code is removed. In this case, the complex despreader 21 is used to divide the phase change caused by the radio channel property and the frequency mismatch of the receiver into real and imaginary parts. The despread positive and quadrature signals are stored through two registers 23 and 24 and input to two multipliers 25 and 26. In addition, the despread signal is input to two multipliers 25 and 26. The delayed signals input to the multipliers 25 and 26 and the signals which have not undergone the delay occur almost in close time and thus have almost the same phase error. Therefore, when the two multipliers 25 and 26 pass, the phase signal is squared, and when the result signals of the two multipliers 25 and 26 are added through the integrator 27, the signals having the phase error removed are collected. This added value is integrated by making the value for the given integration period. At this time, if the position of the set spreading code coincides with the spreading code of the received signal, a very large value is obtained. Otherwise, if the set spreading code position does not match the spreading code of the received signal, a very small value is obtained. The obtained value is analyzed to find the delay of the transmission signal and used to obtain the value of another channel.

3 is a block diagram illustrating a pilot channel energy calculation block according to another embodiment of the present invention. In the figure, 31 is a complex despreader, 32 is a spreading code generator, 33 and 34 are registers, which are the same as those of FIG. The outputs of the registers 33 and 34 are converted into one bit information by the two sign units 35 and 36. This one bit information has only a code component. Therefore, the two multipliers 37 and 38 multiply only the output of the complex despreader by the phase information code of the code part, and when the integral is integrated through the integrator 39, the phase error is eliminated. This method is simpler in construction than the method of FIG. This configuration can reduce the use of the integrator compared to the conventional method. In addition, it is possible to prevent the integral loss that occurs when the integral section is increased indefinitely by the phase error component. And since no additional function for energy calculation is needed, code search can be speeded up when multiple codes are simultaneously searched.

4 is a block diagram illustrating a cell searcher using the energy calculation blocks shown in FIGS. 2 and 3. This is a configuration for asynchronous cell search. The energy calculation blocks 431, 432, 433, and 434 include the blocks of FIGS. 2 to 3. The spreading code generation block includes a plurality of code generation blocks 411, 412, 413, and 414 for different purposes and a plurality of code selectors 421, 422, 423, and 424. The energy values calculated in the energy calculation blocks 431, 432, 433, and 434 are input to the maximum value detector 440. The maximum value detector 440 detects the local maximum value or the maximum value from the calculated energy values. The information thus obtained is stored in the index storage unit 450.

The present invention is structure that searches for several code positions or several code types at the same time. That is, if a code is sequentially delayed using one code generator in the code generation blocks 411, 412, 413, and 414, the cell searcher of FIG. 4 may search for energy at multiple code locations for one code at the same time. Can be. In this case, one code is selected through the cell selectors 421, 422, 423, and 424. The selected code uses a code that is sequentially delayed by one chip. The energy calculation blocks 431, 432, 433, and 434 receive the spreading codes input from the selectors 421, 422, 423, and 424, and simultaneously receive the digital input signal and calculate energy at different positions. The calculated energy is input to the maximum value detector 440 to obtain a local maximum value. The local maximum is large compared to the search energy at the front and back. The local maximum value is selected and stored in the index storage unit 450. The stored local energy maximum can be found simultaneously in several locations by the multipath delay of the radio waves. In addition, the channel of the adjacent cell may be searched. The retrieved local maximum is checked once again in the next slot. The verification process is the same as described above. If it matches the stored location information during the verification process, the stored information is used. Otherwise, the location information with the new local energy maximum is found and stored.

When the code block generators 411, 412, 413, and 414 generate different codes, the code blocks having the largest energy are stored. In this case, the energy calculation blocks 431, 432, 433, and 434 calculate energy by using the code and the digital input signal selected through the code selectors 421, 422, 423, and 424. The calculated energy value stores the spread code index of the code block generator in which the maximum value is generated in the maximum value detector 440. The largest spreading code index is stored in every slot, and once all stored code indices are found, the frame boundary and code group are found. Using the found code group, the spreading code generator generates the code group. At this time, different codes are generated and the generated codes are input to energy calculation blocks 431, 432, 433, and 434 for calculating the energy through the code selectors 421, 422, 423, and 424. The energy value calculated in this block is sent to the maximum value detector 440, and the code index of the location where the largest energy is extracted from the codes included in the code group is stored in the index storage 450.

5 is a flowchart illustrating an operation of the code searcher of FIG. 4. Start at any code location. At this time, set necessary driving variables together. Next, in the step S501 of identifying the slot boundary, local energy is extracted from the retrieved energy and stored therein. At the same time, if the end of the slot is not known even though the end of the search is completed in the searched code range, the process moves to the next position (S506). After all the search in the given search range, the scheduled code position is confirmed. In this process, a code search is performed in a range including a predetermined code position, and the above steps S501 and S506 are repeated.

In this process, if the correct slot boundary is found, the process of finding the next code group and the frame boundary is performed. In this process, you first set up the code to be searched at the same time. In step S502, a code index is obtained and stored. After the calculation, the process proceeds to step S507 to obtain a code index using the same code in the next slot. When the code index is obtained, the code index is stored and the process proceeds to step S503 to find the code group. If no code group is found, the process returns to step S501 to find a new slot boundary.

However, if the code group is successfully found using the code index, the spreading code is searched. First, spreading codes included in the code group are simultaneously set, and in step S504, which spreading codes are spreading codes having the largest energy. At this time, the checking operation of step S508 is repeated in the next frame, and the spreading code is determined by checking the obtained spreading code. If it fails to find the spreading code, the process proceeds to step S502 where the task of finding the code group is performed. If the spreading code is found correctly, the cell search is terminated.

On the other hand, the integrator must be controlled as shown in FIG. 6 in order to search for codes in several search ranges at the same time by delaying one chip by using the same spreading code. Here, the integrator start and end times of the integrator searching from one chip apart are one chip different. Using this structure, the local maximum of the integral result can be obtained using only the integrator. Otherwise, it must store all integral values or store the value of the integrator until the local maximum is obtained. Therefore, this problem is overcome by varying the integration periods of all the integrators.

7 is a configuration diagram of a spreading code generator for obtaining energy at various code positions in one spreading code. Block 710 stores the spreading code value at on time and block 720 stores the half chip delay time spreading code. Using the value output from this, it is possible to simultaneously generate as many spreading codes as desired search periods at the time and delay positions. Block 730 is a block for generating a spreading code, using a spreading code generated here first, and then using a spreading code generated in block 740 to generate a spreading code for use at a next code search position in advance. There should be no. Block 730 then generates code in advance for the next search location after block 740 is used. Block 750 is a selector for selecting such a code.

While the invention has been described above based on the preferred embodiments thereof, these embodiments are intended to illustrate rather than limit the invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments can be made without departing from the spirit of the invention. Therefore, the protection scope of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

As described above, according to the present invention, it is possible to design a structure that reduces the use of hardware when searching multiple spreading codes simultaneously. That is, since the present invention eliminates the phase error component in advance, if the integrator for two different phase components is not necessary, the secondary integrator is not necessary to prevent the integral value including the phase error from decreasing. However, there are two multipliers to replace the squarer, but since the number of bits in the input signal is small, in general, using a multiplier is more advantageous than using a squarer. In addition, the proposed cell searcher can search multiple code locations simultaneously using a single structure, and can simultaneously search for different types of codes. Therefore, it is possible to construct hardware that is much simpler than the existing matched filter structure and simultaneous search structure for multiple codes.

Claims (11)

Complex despreading means for multiplying the input data by a spreading code to despread the input data; Delay means for delaying despread data output from the complex despreading means; And And calculation means for multiplying the despread data output from the complex despreading means and the despread data delayed by the delay means and outputting a result value. 2. The pilot channel energy calculator of claim 1, wherein the delay means comprises at least two registers for storing the positive and quadrature components of the dynamic calculation data output from the complex despreading means. 3. The method according to claim 2, wherein the calculating means multiplies the positive phase component of the despread data output from the complex despreading means and the positive phase component of the despread data delayed by the register, and the quadrature component of the despread data At least two multiplication means for multiplying quadrature components of the despread data delayed by the register; And integrating means for adding two result values multiplied by said at least two multiplication means. 2. The apparatus according to claim 1, further comprising code bit detection means connected between said delay means and said calculation means for detecting a code bit of despread data delayed by said delay means and providing it to said calculation means. Is multiplied by the sign bit of the despread data and the delayed despread data and outputs a result value. The method of claim 4, wherein the calculation means, Multiplying the positive phase component of the despread data output from the complex despreading means and the sign bit of the positive phase component of the delayed despreading data, wherein the quadrature phase component of the despreading data and the quadrature At least two multiplication means for multiplying sign bits, And integrating means for adding two result values multiplied by said at least two multiplication means. Spreading code generating means for generating a plurality of spreading codes; Code selecting means for sequentially selecting one code among the plurality of spreading codes; Energy calculation means for detecting channel energy of the selected code; Maximum value detecting means for detecting a maximum value of channel energy detected by said energy calculating means, and And a storage means for storing the maximum value or the code index of the maximum value detected by the maximum value detection means. 7. The cell finder of claim 6, wherein the plurality of spreading codes are codes in which one code is sequentially delayed. 7. The asynchronous communication apparatus according to claim 6, wherein a plurality of said spreading code generating means, code selecting means, and energy calculating means are connected to said maximum value detecting means for searching a plurality of code positions or a plurality of different codes. A cell finder in a code division multiplexing communication system. The method of claim 6 or 8, wherein the spreading code generating means, A code generation block for generating a spreading code for use in the current search position, a time code storing block for storing and outputting a time spreading code, and a delay for storing and outputting a delay spreading code delayed by half the chip with the time spreading code A cell finder of an asynchronous code division multiplexing communication system comprising a time code storage block. 10. The method of claim 9, wherein a code generation block for generating a spreading code for use in a next search position and one block of the two code generation blocks are selected to spread the spreading code to the time code storage block and the delay time code storage block. A cell finder of an asynchronous code division multiplexing communication system, further comprising selecting means for providing. 7. The apparatus of claim 6, wherein the energy calculation means comprises: complex despreading means for despreading the input data by multiplying the input data by a spreading code; Delay means for delaying the normal phase component and the quadrature phase component of the despread data output from the complex despreading means; The normal phase component of the despread data output from the complex despreading means and the normal phase component of the despread data delayed by the delay means are multiplied, and the quadrature phase component of the despread data output from the complex despreading means and the delay means. Multiplication means for multiplying quadrature components of the delayed despread data in And And a integration means for adding two result values of the multiplication means.