KR20010068781A - Semiconductor chip package - Google Patents
Semiconductor chip package Download PDFInfo
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- KR20010068781A KR20010068781A KR1020000000886A KR20000000886A KR20010068781A KR 20010068781 A KR20010068781 A KR 20010068781A KR 1020000000886 A KR1020000000886 A KR 1020000000886A KR 20000000886 A KR20000000886 A KR 20000000886A KR 20010068781 A KR20010068781 A KR 20010068781A
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- semiconductor chip
- circuit board
- printed circuit
- package
- chip package
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
본 발명은 반도체 칩 패키지에 관한 것으로서, 더욱 상세하게는 반도체 칩의 실장수단으로서 인쇄회로기판을 이용하는 구조로서 박형화와 적층 칩 패키지 구현이 용이한 반도체 칩 패키지에 관한 것이다.The present invention relates to a semiconductor chip package, and more particularly, to a semiconductor chip package having a structure using a printed circuit board as a mounting means of a semiconductor chip, which can be easily thinned and a laminated chip package.
반도체 소자는 집적도가 증가하면서 점점 더 많은 수의 입출력 핀을 요구하기 때문에 소자의 크기를 소형화하는 것이 중요하다. 그러나, 소형의 반도체 소자가 많은 입출력 핀을 가지게 되면 반도체 칩 패키지의 리드 피치가 너무 작아져서 패키지의 리드가 외부의 충격에 손상되고, 전기적인 기생변수로 인한 칩 성능 저하도 발생되며, 패키지의 취급에 세심한 주의가 필요하다는 문제점이 생긴다. BGA(Ball Grid Array) 패키지는 PGA(Pin Grid Array) 패키지에서 리드의 길이가 길기 때문에 발생할 수 있는 유도성 성분에 의한 부정적 요소를 배제하면서 입출력 핀의 효율성이라는 장점을 취할 수 있는 패키지로서 많은 수의 입출력 단자가 필요한 소자에 적합하다. BGA 패키지의 예를 소개하기로 한다.Since semiconductor devices require an increasing number of input / output pins as the degree of integration increases, it is important to miniaturize the size of the device. However, if a small semiconductor device has many input / output pins, the lead pitch of the semiconductor chip package is too small, leading to damage of the package lead to external shock, and deterioration of chip performance due to electrical parasitic variables. There is a problem that requires careful attention. The Ball Grid Array (BGA) package is a package that can take advantage of the efficiency of input / output pins while eliminating negative factors due to inductive components that may occur due to the long lead length in the PGA (Pin Grid Array) package. Suitable for devices requiring input and output terminals. Here is an example of a BGA package.
도 1은 일반적인 BGA 패키지를 나타낸 단면도이다.1 is a cross-sectional view showing a typical BGA package.
도 1을 참조하면, 일반적인 BGA 패키지(100)는 금속배선(도시안됨)이 형성되어 있는 인쇄회로기판(121)의 상면에 접착제(115)로 반도체 칩(111)이 부착되어 있고, 그 반도체 칩(111)의 본딩패드(113)와 인쇄회로기판(121)의 금속배선(도시안됨)이 도전성 금속선(145)으로 와이어 본딩(wire bonding)되어 전기적인 연결을 이루고 있으며, 반도체 칩(111)과 도전성 금속선(145) 및 그 접합 부위를 외부환경으로부터 보호하기 위하여 성형 수지로 패키지 몸체(149)가 형성되어 있고, 인쇄회로기판(121)의 하면에 외부 접속 단자로서 솔더 볼(141)들이 부착되어 있는 구조를 가지고 있다.Referring to FIG. 1, in a typical BGA package 100, a semiconductor chip 111 is attached to an upper surface of a printed circuit board 121 on which a metal wiring (not shown) is formed, using an adhesive 115. Metal bonding (not shown) of the bonding pad 113 of FIG. 1 and the printed circuit board 121 is wire bonded to the conductive metal wire 145 to form an electrical connection. In order to protect the conductive metal wire 145 and its bonding portion from the external environment, a package body 149 is formed of molding resin, and solder balls 141 are attached to the lower surface of the printed circuit board 121 as external connection terminals. Has a structure.
그러나, 이와 같은 BGA 패키지와 같이 인쇄회로기판을 이용하는 반도체 칩 패키지 구조는 패키지 두께의 축소에 한계가 있으며, 외부 접속 단자로서 사용되는 솔더 볼이 한 면으로만 형성될 수 있기 때문에 기판에 실장시 일정한 한 방향으로만 가능하다. 동일한 제품이 항상 같은 기판에 실장된다면 문제가 없겠으나 고객들의 요구가 다양하고 또한 동일 제품에 대해서도 볼 형태를 요구하기도 하고 판널 형태를 요구하는 등 한 가지 디자인으로는 대응이 어려운 문제가 생긴다. 그리고, 종래의 BGA 패키지는 동일 패키지 두 개가 한 번에 기판 상에 실장되는 경우 평면 형태로 실장될 수밖에 없다.However, a semiconductor chip package structure using a printed circuit board, such as a BGA package, has a limitation in reducing the thickness of the package, and is fixed at the time of mounting on a board because solder balls used as external connection terminals can be formed only on one side. Only in one direction. If the same product is always mounted on the same board, there will be no problem, but there is a problem that it is difficult to cope with a single design, such as customer demands, ball type and panel type for the same product. In addition, the conventional BGA package may be mounted in a planar form when two identical packages are mounted on a substrate at one time.
본 발명의 목적은, 패키지 두께를 최소화하면서도 기판 실장에 대한 자유도를 향상시키며 적층 패키지 구현이 용이한 새로운 형태의 반도체 칩 패키지를 제공하는 데에 있다.An object of the present invention is to provide a new type of semiconductor chip package that can improve the degree of freedom for mounting the substrate while minimizing the package thickness and can easily implement a multilayer package.
도 1은 일반적인 BGA(Ball Grid Array) 패키지를 나타낸 단면도,1 is a cross-sectional view showing a typical ball grid array (BGA) package,
도 2는 본 발명에 따른 반도체 칩 패키지를 나타낸 단면도,2 is a cross-sectional view showing a semiconductor chip package according to the present invention;
도 3은 본 발명에 따른 반도체 칩 패키지의 평면도,3 is a plan view of a semiconductor chip package according to the present invention,
도 4는 본 발명에 따른 반도체 칩 패키지의 저면도,4 is a bottom view of a semiconductor chip package according to the present invention;
도 5는 본 발명에 따른 반도체 칩 패키지를 이용한 적층 패키지를 나타낸 단면도이다.5 is a cross-sectional view showing a laminated package using a semiconductor chip package according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; 반도체 칩 패키지 11; 반도체 칩10; Semiconductor chip package 11; Semiconductor chip
13; 본딩패드 15; 접착제13; Bonding pads 15; glue
21; 인쇄회로기판 23; 상부 랜드21; Printed circuit board 23; Upper land
25; 하부 랜드 27; 볼 접합 랜드25; Lower land 27; Ball junction land
31; 제 1단차면 33; 제 2단차면31; First step surface 33; 2nd step
35; 금속배선 37; 비아 콘택35; Metallization 37; Via contact
39; 보호막 41; 솔더 볼39; Protective film 41; Solder ball
45; 본딩 와이어 49; 봉지부45; Bonding wire 49; Encapsulation
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 칩 패키지는, 복수의 본딩패드를 갖는 반도체 칩과, 상기 반도체 칩이 실장되며 금속배선이 형성된 인쇄회로기판을 구비하는 반도체 칩 패키지에 있어서, 상기 인쇄회로기판은 캐버티 형성에 의해 상면으로부터 단차를 가지며 금속배선이 노출된 제 1단차면과, 상기제 1단차면과 단차를 가지며 반도체 칩이 부착되는 제 2단차면과, 그 캐버티 외측의 상기 인쇄회로기판의 상면과 하면에 상기 금속배선과 전기적으로 연결된 비아 콘택에 의해 전기적으로 연결되는 상부 도금층과 하부 도금층이 동일 패턴으로 형성되어 있고, 상기 반도체 칩의 본딩패드와 상기 금속배선이 상기 본딩 와이어로 와이어 본딩되어 있으며, 상기 반도체 칩과 상기 본딩 와이어 및 그 접합 부위를 봉지하며 캐버티에 들어차도록 봉지부가 형성되어 있는 것을 특징으로 한다.The semiconductor chip package according to the present invention for achieving the above object is a semiconductor chip package having a semiconductor chip having a plurality of bonding pads, and a printed circuit board on which the semiconductor chip is mounted, the metal wiring is formed, the printing The circuit board includes a first stepped surface having a step from an upper surface by forming a cavity and an exposed metal wiring, a second stepped surface having a step from the first stepped surface and to which a semiconductor chip is attached, and the outer side of the cavity. The upper plating layer and the lower plating layer electrically connected to the upper and lower surfaces of the printed circuit board by the via contact electrically connected to the metal wiring are formed in the same pattern, and the bonding pad and the metal wiring of the semiconductor chip are the bonding wires. The wire is bonded to the semiconductor chip and the bonding wire and the bonding portion thereof is enclosed in the cavity To it characterized in that the sealing portion is formed.
이하 첨부 도면을 참조하여 본 발명에 따른 반도체 칩 패키지를 보다 상세하게 설명하고자 한다.Hereinafter, a semiconductor chip package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체 칩 패키지를 나타낸 단면도이고, 도 3은 본 발명에 따른 반도체 칩 패키지의 평면도이며, 도 4는 본 발명에 따른 반도체 칩 패키지의 저면도이다.2 is a cross-sectional view illustrating a semiconductor chip package according to the present invention, FIG. 3 is a plan view of a semiconductor chip package according to the present invention, and FIG. 4 is a bottom view of the semiconductor chip package according to the present invention.
도 2내지 도 4를 참조하면, 이 반도체 칩 패키지(10)는 반도체 칩(11)의 실장 수단으로서 인쇄회로기판(21)을 이용하고 있으며, 반도체 칩(11)이 인쇄회로기판(21)에 매립되는 형태로서, 외부 접속 단자로서 인쇄회로기판의 상면과 하면에 동일한 패턴으로 형성된 상부 도금층(23)과 하부 도금층(25)을 이용하는 형태이다. 이 패키지 구조를 좀 더 상세하게 설명하기로 한다.2 to 4, the semiconductor chip package 10 uses a printed circuit board 21 as a mounting means of the semiconductor chip 11, and the semiconductor chip 11 is attached to the printed circuit board 21. As a form of embedding, the upper plating layer 23 and the lower plating layer 25 formed in the same pattern on the upper and lower surfaces of the printed circuit board are used as external connection terminals. This package structure will be described in more detail.
인쇄회로기판(21)은 캐버티(cavity)가 형성되어 상면으로부터 소정 깊이로 형성된 제 1단차면(33)과, 그 제 1단차면(33)으로부터 다시 소정 깊이로 형성된 제 2단차면(31)을 갖는다. 제 1단차면(33)에는 금속배선(35)이 형성되어 있다. 제 2단차면(31)은 반도체 칩(11)이 실장되는 영역으로서 그 깊이와 크기는 반도체 칩(11)의 두께 및 본딩 와이어(45)의 와이어 루프(wire loop) 높이 및 인쇄회로기판(21)의 두께 등을 고려하여 결정된다.The printed circuit board 21 includes a first stepped surface 33 having a cavity formed to a predetermined depth from an upper surface thereof, and a second stepped surface 31 formed again to a predetermined depth from the first stepped surface 33. Has The metal wiring 35 is formed on the first step surface 33. The second step surface 31 is a region in which the semiconductor chip 11 is mounted, and the depth and size thereof are the thickness of the semiconductor chip 11, the height of the wire loop of the bonding wire 45, and the printed circuit board 21. Is determined in consideration of the thickness and the like.
인쇄회로기판(21)의 상면과 하면에는 캐버티 외측에 위치하며 서로 대칭이 되도록 각각 동일한 패턴으로 구리 도금에 의해 상부 도금층(23)과 하부 도금층(25)이 형성되어 있다. 이 상부 도금층(23)과 하부 도금층(25)은 인쇄회로기판(21)을 관통하도록 비아 홀(via hole) 도금 방식에 의해 형성된 비아 콘택(37)에 의해 전기적으로 연결되어 있다. 이때, 비아 콘택(37)은 제 1단차면(33)에 노출되도록 형성된 금속배선(35)과 인쇄회로기판(21)의 내부에서 접합되어 전기적으로 연결되어 있다.The upper plating layer 23 and the lower plating layer 25 are formed on the upper and lower surfaces of the printed circuit board 21 by copper plating in the same pattern so as to be located outside the cavity and to be symmetrical with each other. The upper plating layer 23 and the lower plating layer 25 are electrically connected to each other by a via contact 37 formed by via hole plating to penetrate the printed circuit board 21. In this case, the via contact 37 is bonded to the metal wiring 35 formed on the first step surface 33 and the printed circuit board 21 to be electrically connected to each other.
그리고, 인쇄회로기판(21)은 하면에 형성된 하부 도금층(25)의 내측 영역에 그 하부 도금층(25)과 전기적으로 연결되도록 하여 솔더 볼(41)의 부착을 위한 볼 패드(27)가 형성되어 있으며 인쇄회로기판(21)의 하면은 보호막(39)에 의해 보호된다. 여기서, 볼 패드(27)는 외부 접속 단자로서 솔더 볼(41)을 사용하여 볼 그리드 어레이(Ball Grid Array) 형태를 갖도록 하는 데에 필요하다.The printed circuit board 21 is electrically connected to the lower plating layer 25 at an inner region of the lower plating layer 25 formed on the lower surface thereof, thereby forming a ball pad 27 for attaching the solder balls 41. The lower surface of the printed circuit board 21 is protected by the protective film 39. Here, the ball pad 27 is necessary to have a ball grid array form using the solder balls 41 as external connection terminals.
반도체 칩(11)은 복수의 본딩패드(13)가 가장자리에 형성되어 있는 에지패드(edge pad)형으로서, 인쇄회로기판(21)의 제 2단차면(31)에 접착제(15)에 의해 부착되어 있다. 본딩패드(13)는 제 1단차면(33)에 형성된 금속배선(35)에 금선과 같은 도전성의 본딩 와이어(45)로 와이어 본딩되어 있으며, 에지패드형의 반도체 칩(11)이기 때문에 와이어 본딩의 길이가 짧다. 이에 의해 반도체 칩(11)과 인쇄회로기판(21)이 전기적으로 연결된다. 이때, 본딩 와이어(45)의 와이어 루프높이는 인쇄회로기판(21)의 상면보다 아래쪽에 위치한다.The semiconductor chip 11 is an edge pad type in which a plurality of bonding pads 13 are formed at the edges, and is attached to the second step surface 31 of the printed circuit board 21 by an adhesive 15. It is. The bonding pad 13 is wire bonded to the metal wiring 35 formed on the first step surface 33 by a conductive bonding wire 45 such as gold wire, and is a wire bonding because it is an edge pad type semiconductor chip 11. The length of is short. As a result, the semiconductor chip 11 and the printed circuit board 21 are electrically connected to each other. At this time, the height of the wire loop of the bonding wire 45 is located below the upper surface of the printed circuit board 21.
에폭시 성형 수지(epoxy molding compound)와 같은 수지 봉지재로 형성되는 봉지부(49)는 인쇄회로기판(21)의 제 1단차면(33)에 노출되는 금속배선(35)과 반도체 칩(11) 및 이들을 연결해주는 본딩 와이어(45)를 봉지하도록 형성되어 있다. 이에 의해 외부 환경으로부터 물리적으로나 화학적으로 보호된다.The encapsulation portion 49 formed of a resin encapsulation material such as an epoxy molding compound includes a metal wiring 35 and a semiconductor chip 11 exposed to the first step surface 33 of the printed circuit board 21. And it is formed to seal the bonding wire 45 connecting them. This protects them physically and chemically from the external environment.
이와 같은 본 발명의 반도체 칩 패키지는 상부 도금층과 하부 도금층을 외부 접속단자로 사용하여 QFN(Quad Flat Non-lead) 형태가 가능하고, 볼 패드에 솔더 볼을 형성함으로써 BGA 형태가 가능하다. 그리고, 상면과 하면에 동일 패턴으로 상부 도금층과 하부 도금층이 형성되기 때문에 상하 구분이 없이 페이스-업(face-up)과 페이스-다운(face-down) 형태로 실장이 가능하며, 이를 이용하여 적층 패키지 구현이 용이하다.Such a semiconductor chip package of the present invention may be formed in a quad flat non-lead (QFN) form by using an upper plating layer and a lower plating layer as external connection terminals, and a BGA form by forming solder balls on a ball pad. In addition, since the upper plating layer and the lower plating layer are formed in the same pattern on the upper surface and the lower surface, it is possible to mount in the form of face-up and face-down without using the upper and lower divisions, and lamination using this. Package implementation is easy.
도 5는 본 발명에 따른 반도체 칩 패키지를 이용한 적층 패키지를 나타낸 단면도이다.5 is a cross-sectional view showing a laminated package using a semiconductor chip package according to the present invention.
도 5를 참조하면, 이 적층 패키지는 전술한 본 발명의 반도체 칩 패키지 구조를 갖는 3개의 반도체 칩 패키지들(10a,10b,10c)을 각각의 상부 도금층과 하부 도금층이 접합되도록 하여 적층한 형태의 구조로서, 상위에 위치한 반도체 칩 패키지들(10a,10b)은 상부 도금층과 하부 도금층을 외부 접속단자로 사용하는 QFN 형태이고, 최하위에 위치한 반도체 칩 패키지(10c)는 솔더 볼을 외부 접속단자로 사용하는 BGA 형태이다. 물론, 최하위에 위치한 반도체 칩 패키지(10c)를 QFN 형태를 갖도록 할 수도 있다.Referring to FIG. 5, the multilayer package is formed by stacking three semiconductor chip packages 10a, 10b, and 10c having the semiconductor chip package structure of the present invention to each of the upper and lower plating layers. As a structure, the upper semiconductor chip packages 10a and 10b have a QFN type using the upper plating layer and the lower plating layer as external connection terminals, and the lowermost semiconductor chip package 10c uses solder balls as the external connection terminals. It is a BGA form. Of course, the lowermost semiconductor chip package 10c may have a QFN shape.
이상과 같은 본 발명에 의한 반도체 칩 패키지 구조에 따르면, 외부 접속 단자가 돌출되어 있지 않는 QFN 형태나 일면으로 면 배열되어 있는 BGA 형태 모두로 사용될 수 있다. 또한, 인쇄회로기판의 상면과 하면에 동일 패턴으로 상부 도금층과 하부 도금층이 형성되어 있기 때문에 상하 구분이 없이 패키지 실장이 가능하며 적층 패키지 구현이 용이할 뿐만 아니라 기판 제작의 자유도를 극대화할 수 있다. 더욱이, 반도체 칩이 인쇄회로기판에 매립되어 있기 때문에 박형 패키지 구현이 가능하며 전기적 특성이 우수한 패키지 구현이 가능하다. 그리고, 기존의 자재 및 공정 설비를 그대로 이용할 수 있기 때문에 생산비용이 저렴하다.According to the semiconductor chip package structure according to the present invention as described above, it can be used both in the QFN form in which the external connection terminal does not protrude or in the BGA form arranged in one surface. In addition, since the upper plating layer and the lower plating layer are formed in the same pattern on the upper and lower surfaces of the printed circuit board, it is possible to mount the package without distinguishing between the upper and lower sides, and it is easy to implement the laminated package and maximize the degree of freedom in manufacturing the substrate. Furthermore, since the semiconductor chip is embedded in the printed circuit board, a thin package can be realized and a package having excellent electrical characteristics can be realized. In addition, production costs are low because existing materials and process equipment can be used as they are.
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| KR1020000000886A KR20010068781A (en) | 2000-01-10 | 2000-01-10 | Semiconductor chip package |
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| KR100542671B1 (en) * | 2000-07-27 | 2006-01-12 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
| KR100618901B1 (en) * | 2004-08-14 | 2006-09-01 | 삼성전자주식회사 | Semiconductor package having nonlinear characteristics of impact test and manufacturing method the same |
| KR100987783B1 (en) * | 2008-02-27 | 2010-10-18 | 박재순 | Semiconductor package and method of manufacturing for the same |
| KR101442170B1 (en) * | 2007-12-10 | 2014-09-18 | 삼성전자주식회사 | Semiconductor Package and Manufacturing Method of the same |
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| KR19980054997A (en) * | 1996-12-27 | 1998-09-25 | 김광호 | Stacked Semiconductor Packages |
| KR19990025444A (en) * | 1997-09-12 | 1999-04-06 | 구본준 | Semiconductor substrate, stacked semiconductor package, and method of manufacturing the same |
| KR19990039991A (en) * | 1997-11-15 | 1999-06-05 | 구본준 | Stacked ball grid array semiconductor package and manufacturing method thereof |
| KR19990069447A (en) * | 1998-02-09 | 1999-09-06 | 구본준 | Semiconductor package and manufacturing method |
| US6297548B1 (en) * | 1998-06-30 | 2001-10-02 | Micron Technology, Inc. | Stackable ceramic FBGA for high thermal applications |
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| KR19980054997A (en) * | 1996-12-27 | 1998-09-25 | 김광호 | Stacked Semiconductor Packages |
| KR19990025444A (en) * | 1997-09-12 | 1999-04-06 | 구본준 | Semiconductor substrate, stacked semiconductor package, and method of manufacturing the same |
| KR19990039991A (en) * | 1997-11-15 | 1999-06-05 | 구본준 | Stacked ball grid array semiconductor package and manufacturing method thereof |
| KR19990069447A (en) * | 1998-02-09 | 1999-09-06 | 구본준 | Semiconductor package and manufacturing method |
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| KR100542671B1 (en) * | 2000-07-27 | 2006-01-12 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
| KR100618901B1 (en) * | 2004-08-14 | 2006-09-01 | 삼성전자주식회사 | Semiconductor package having nonlinear characteristics of impact test and manufacturing method the same |
| KR101442170B1 (en) * | 2007-12-10 | 2014-09-18 | 삼성전자주식회사 | Semiconductor Package and Manufacturing Method of the same |
| KR100987783B1 (en) * | 2008-02-27 | 2010-10-18 | 박재순 | Semiconductor package and method of manufacturing for the same |
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