KR20010065616A - Synthesizer of Digital TV Translator - Google Patents

Abstract

PURPOSE: A synthesizer of digital repeater is provided to generate plus off-set frequency and minus off-set frequency selectively by preparing a VCXO(voltage controlled crystal oscillator) in a synthesizer. CONSTITUTION: A channel VCXO(31) generates a channel signal for a channel. A first directional coupler(32) divides the output signal of the channel VCXO(31). A mixer(33) mixes an intermediate frequency output from the first directional coupler(32) with an off-set frequency supplied by a divider(39). An off-set frequency control unit(200) outputs a voltage signal variably according to the output signal of the channel VCXO(31) supplied by the first directional coupler(32). A multiplexer(34) multiplies a reference signal and the output signal of the mixer(33) according to an established selection signal and outputs them selectively. A phase detector(35) detects a phase from the output signal of the multiplexer(34). A PLL(phase locked loop)(36) determines the phase in comparison with a phase difference detected in the phase detector(35). An off-set VCXO(37) makes a plus or a minus off-set frequency of the output signal of the PLL(36) according level of a voltage signal output from the off-set frequency control unit(200). A second directional coupler(38) divides the output signal of the off-set VCXO(37) and outputs it each to the divider(39) and a mixer of digital TV repeater.

Description

Synthesizer of digital repeater {Synthesizer of Digital TV Translator}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synthesizer of a digital repeater, and in particular, a voltage controlled crystal oscillator (VCXO), which improves a conventional synthesizer generated by separating +/- offset frequencies. The present invention relates to a synthesizer for a digital repeater capable of selectively generating a + offset frequency and a -offset frequency by using < RTI ID = 0.0 >

In general, a frequency synthesizer is a variable oscillator that oscillates an arbitrary arbitrary frequency by processing the oscillation frequency such as multiplication, diminishing or mixing, based on one crystal oscillator having high accuracy and stability. It is mainly used for measurement, and it is often used as a controllable point as a frequency reference of short wave transmitter and receiver.

1 is a block diagram of a conventional digital repeater. Referring to FIG. 1, a digital broadcast signal transmitted from a main transmitter (not shown) is input to a low noise amplifier (LNA) 12 through a receiving antenna 11 and amplified.

Subsequently, the output signal of the low noise amplifier (LNA) 12 is input to the demodulator 13, and is first converted into an intermediate frequency of 44 MHz while passing through a tuner provided in the demodulator 13. Subsequently, the converted intermediate frequency signal is separated into an I channel and a Q channel signal, and is then reproduced as a signal having the same quality as the transmission signal of the main transmitter by recovering the broken data through an error correction procedure. Subsequently, the reproduced signal is converted into SMPTE310 (Society of Motion Picture and Television Engineers) signal, which is an advanced television systems committee (ATSC) standard, and then output.

This converted signal is then modulated again via the 8 VSB modulator 14 shown in FIG. 1 and made into the desired channel signal (eg channel 18) via the up / down converter 10. Subsequently, the output signal of the up / down converter 10 is amplified to enable radio radiation from a high power amplifier (HPA) 18 and broadcasted to the area of the digital TV repeater through the transmitting antenna 19.

In this case, when a D digital TV repeater is installed in a region in which a repeater or a main transmitter of another broadcasting station is installed or is affected by another broadcast, broadcast signals of other broadcasting stations may interfere. For example, if a KBS station operates a repeater on channel 18 in a particular area, and the MBC station transmits the signal from the main transmitter to channel 18, the area is within the sphere of influence of the MBC station and KBS station. Will be. Therefore, the viewer watching the KBS broadcast is poor in the quality of the broadcast signal because it is interfered with by the MBC broadcast having the same channel.

To compensate for this problem, the influence of the same channel interference is reduced by transmitting and receiving an offset frequency to the channel signal of each repeater in the region where the same channel interference occurs. This offset frequency is generated by the synthesizer 17 of the up / down converter 10 shown in FIG. 1, and the synthesizer circuit producing this offset frequency is shown in FIG.

The synthesizer circuit of FIG. 2 includes a mixer 22 for mixing a channel VCXO 21 for producing a channel signal and an offset frequency input through a path different from the channel frequency output from the channel VCXO 21, and a set selection signal. a multiplexer 23 for multiplexing and selectively outputting the output signal and the reference signal of the mixer 22 according to (+/- select), a phase detector 24 for detecting a phase in the output signal of the multiplexer 23, An offset VCXO 26 that produces a channel signal + an offset frequency according to an output signal of a phase locked loop (PLL) 25 that determines a phase by comparing the phase difference detected by the phase detector 24, and an offset, And a directional coupler 27 for branching the output signal of the VCXO 26 for output to the mixer 22 and the mixer 15 of the digital TV repeater.

In the digital TV repeater of the present invention, a 44 MHz intermediate frequency (RF) output from the channel VCXO 21 and a local frequency (LO) input from the offset VCXO 26 are mixed to form a channel signal, and the RF compensator 16 To the high power amplifier 18. At this time, the synthesizer 17 outputs only the local frequency LO generated by the channel VCXO 21 when the synthesizer 17 does not use the offset frequency, and generates a local frequency (LO) produced by the offset VCXO 26 when the offset frequency is used. Outputs the frequency plus LO) and offset frequency. Here, the output signals of the channel VCXO 21 and the offset VCXO 26 are input to the mixer 22, so that only the offset frequency outputs only the intermediate frequency IF signal of the mixer 27. This intermediate frequency signal is eventually input to the phase locked loop 25. Therefore, the offset VCXO 26 is controlled by the DC output from the phase locked loop 25 to output the correct LO + offset frequency.

At this time, the broadcasting station operator must determine in advance whether to use a + offset frequency or a-offset frequency. Therefore, in case of using + offset, the offset VCXO 26 should be provided with the + offset VCXO, and in the case of using-offset, the offset VCXO 26 should be provided with the-offset VCXO. Therefore, the broadcasting station operator must set the offset to be used in the multiplexer 23 in advance, and determine the offset VCXO 26 accordingly.

As a result, the operator of the broadcasting station should have a large number of two types of VCXOs, VCXO for + offset and VCXO for -offset, to match the channels provided in the corresponding area. Whether or not to use an offset frequency must be determined in advance.

Therefore, the operator of a broadcasting station should always install a repeater with a large number of two types of VCXOs and install an appropriate VCXO when installing a digital TV repeater.

In addition, the producers of digital TV repeaters must produce and export various types of digital TV repeaters according to the frequency of use currently provided by the exporting country or region.

The object of the present invention was created in view of the problems of the prior art, and by providing a voltage controlled crystal oscillator (VCXO) in a circuit of a conventional synthesizer, the + offset frequency and-offset It is to provide a synthesizer of a digital repeater capable of selectively generating a frequency.

1 is a block diagram of a conventional digital repeater.

Figure 2 is a block diagram of a conventional synthesizer shown in FIG.

3 is a block diagram of a synthesizer according to the present invention;

4A and 4B are graphs for explaining the operation of the synthesizer shown in FIG. 3, respectively.

5 and 6 are waveform diagrams showing the output waveforms of the offset VCXO, the channel VCXO, and the phase detector shown in FIG. 3, respectively.

<Description of the symbols for the main parts of the drawings>

31: VCXO for Channel 32: Directional Coupler

33: Mixer 34: Multiplexer

35 phase detector 36 phase locked loop (PLL)

37: Offset VCXO 38: Directional Coupler

39: dispenser 40, 41: divider

42: phase detector 43: phase locked loop (PLL)

44 ~ 46: Inverter

In order to achieve the above object, a synthesizer of a digital repeater according to a feature of the present invention includes a channel voltage controlled crystal oscillator for generating a channel signal, a first directional coupler for branching an output signal of the channel voltage controlled crystal oscillator, A mixer for mixing an intermediate frequency output from the first directional coupler and a local frequency provided; an offset frequency controller for variably outputting a voltage according to an output signal provided from the first directional coupler; A phase-locked loop (Phase) for determining a phase by comparing a multiplexer for multiplexing and selectively outputting the output signal and the reference signal of the mixer, a phase detector for detecting a phase in the output signal of the multiplexer, and a phase difference detected by the phase detector. Locked Loop (PLL) and the output signal of the phase locked loop An offset voltage controlled crystal oscillator for generating and outputting a + or − offset frequency according to the voltage level output from the preset frequency controller, and outputting the split signal and the digital TV repeater to branch output signals of the offset voltage controlled crystal oscillator And a second directional coupler.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a synthesizer according to the present invention. Referring to FIG. 3, the synthesizer circuit according to the present invention includes a channel VCXO 31 for generating a channel signal, a first directional coupler 32 for branching an output signal from the channel VCXO 21, and a first directional coupler. The output signal of the mixer 33 for mixing the intermediate frequency output from the combiner 32 and the offset frequency LO provided from the divider 39 and the VCXO 31 for channel provided from the first directional combiner 32. An offset frequency controller 200 for variably outputting a voltage signal according to the multiplexer, and a multiplexer for multiplexing and selectively outputting the output signal of the mixer 33 and the reference signal ref according to a set selection signal (+/− select) ( 34, a phase locked loop (PLL) for determining a phase by comparing the phase detector 35 which detects a phase in the output signal of the multiplexer 34, and the phase difference detected by the phase detector 35 ( 36) and the output signal of the phase locked loop (PLL) 36 The splitter 39 divides the output signal of the offset VCXO 37 and the offset VCXO 37 to generate and output a + or − offset frequency according to the level of the voltage path output from the offset frequency controller 200. And a second directional coupler 38 output to the mixer of the digital TV repeater, respectively.

Here, the offset frequency control unit 200 divides the output signal of the first directional coupler 32 by 64 and outputs the first divider 40, and the second divider divides and outputs the output signal of the divider 39 by 64. The phase 41 is compared with the phase detector 42 for detecting phases in the output signals of the first and second dividers 40 and 41 and the phase difference detected by the phase detector 42 to determine the phase. A phase locked loop (PLL) 43 and a plurality of inverters 44 to 46 are included.

Hereinafter, with reference to the accompanying drawings, the operation of the synthesizer of the digital TV repeater according to the present invention.

In the preferred embodiment of the present invention, it is assumed that the channel VCXO and the offset frequency control unit 200 use the same +/- 2 kHz frequency, and the fc of the two VCXOs is 100.002 MHz.

In FIG. 3, the channel VCXO 31 must output a frequency of 100.002 MHz in order to make an offset of +2 kHz so that the frequency of 2 kHz may be output by the mixer 33. In order to operate in this manner, as shown in FIG. 4A, a control voltage Vc of about 4.3 V must be applied to the offset VCXO 37. That is, when power is applied to the synthesizer, a reference frequency of 2 kHz is input to the reference terminal # 14 of the phase detector 36. The output voltage of the phase locked loop 36 will then increase through the path pass 1 toward a lower voltage 1 to 4.3V, which is close to 0V in nature. Thus, as shown in FIG. 4A, the frequency of the offset VCXO 37 will increase from the low range of the variable range to the frequency of the high range of the variable range.

Here, in order for the synthesizer of the present invention to generate a signal of 100.002 MHz, the radio frequency RF input to the mixer 33 is 100 MHz, and the local oscillation frequency LO input to the mixer 33 is 100.002 MHz. Only when the intermediate frequency IF, which is the output signal of the mixer 33, becomes 2 kHz, it is locked in synchronization with the reference input signal of the phase detector 35. That is, to make + offset frequency, the condition of LO> RE and LO-RF = IF must be satisfied.

Here, if another path (pass2) is open and only the path (pass 1) exists, the synthesizer's phase detector 35 can obtain-offset frequency even if the operator sets the + offset frequency (100.002 MHz). . However, a signal of 100.0 MHz (RE) -99.998 MHz (LO) = 2 kHz is already created at RF> LO, and due to the principle of negative feedback and positive feedback, which will be synchronized with an offset or described later. Therefore, the embodiment of the present invention is configured such that the path pass 2 is added to the path pass 1.

That is, a signal obtained by dividing the channel VCXO 31 by 64 is input into the input terminal # 14 of the phase detector 42, and a signal by 64 divided by the offset VCXO 37 is input into the input terminal # 3. Enter Since these two signals have a difference by an offset, they are not locked and produce a high level or low level signal having an area equal to the offset as shown in FIG. 5. This high level or low level signal passes through the inverters 44 to 46 and is added to the path pass1 by passing only the high level signal in the case of + offset.

As a result, LO-RF = IF is obtained because the starting point of the control voltage Vc applied to the offset VCXO 37 can be started at 100.0 MHz or more by combining the power of the synthesizer with the two paths pass1 and pass2. The phase-lock loop 43 is turned to be 2kHz and synchronized at the desired 100.002MHz.

On the other hand, in order to make the offset frequency of -2 kHz, the channel VCXO 31 is outputted at 100.0 MHz and the offset VCXO 37 is output at 99.998 MHz so that the signal of 2 kHz is output by the mixer 33. In order to operate in this manner, a control voltage Vc of about 1.8 V must be applied to the offset VCXO 37 as shown in FIG. 4A. That is, the phase detector 42 applies only the offset frequency difference to the path pass 2 at a low level voltage, and is synchronized to the desired 99.998 MHz in addition to the path pass1 of the phase detector 35. At this time, even if the path pass2 is open, only one path pass1 can obtain a desired -offset frequency. Here, the voltage signal passing through the path pass1 of the phase detector 35 may be added to the path pass2.

In the embodiment of the present invention, when the + offset frequency and the-offset frequency are used, the switch of the multiplexer 34 is switched. The reason for this is as follows.

6, when the offset frequency of +2 kHz is used, the LO (offset VCXO 37) input to the mixer 33 is larger than the RF (channel VCXO 31).

If the power of the synthesizer is provided, if the intermediate frequency IF initially output from the mixer 33 is 100.003 MHz, the intermediate frequency IF must be decreased in order for the frequency to be locked. Therefore, as can be seen from the equation of LO-RF = IF, the RF is fixed, so that the IF decreases after the LO decreases. That is, 100.003-100.0 = 3 kHz, so if IF 3 is 2, LO 100.003 must be LO100.002. In the present invention, this is called negative feedback.

On the other hand, if an offset frequency of -2 kHz is used, if the intermediate frequency (IF) of the mixer 33 is initially output to 99.997 MHz, then 100.0-99.997 = 3 kHz can be applied from the RF-LO = IF equation. To be this 2, LO 99.997 must be 99.998. In other words, IF increases when LO increases, which is referred to as positive feedback in the present invention.

As described above, since the synchronization method of the offset frequency is opposite directions in the + offset region and the-offset region, the reference input terminal of the phase detector 35 and the input of the VCXO must be changed.

In an embodiment of the present invention, in order to solve the problem of a conventional synthesizer, two types of VCXOs, which are + offset VCXO for generating a + offset frequency and-offset VCXO for generating an offset frequency, must be used. VCXO is used to selectively generate + offset and -offset frequencies. Therefore, when a broadcaster operator installs a repeater, it is not necessary to have both a + offset VCXO and a -offset VCXO.

According to a preferred embodiment of the present invention as described above, to solve the inconvenience of having to use two types of VCXO of the + offset VCXO for generating the + offset frequency and the-offset VCXO for generating the -offset frequency In order to provide a synthesizer of a digital TV repeater capable of selectively generating a + offset frequency and a -offset frequency using a single VCXO. Therefore, it is not necessary for the station operator to install a repeater with a plurality of + offset VCXOs and -offset VCXOs. In addition, since a large number of expensive VCXOs do not have to be provided, there is an advantage of lowering the product price.

Claims (2)

A voltage controlled crystal oscillator for the channel to create a channel signal, A first directional coupler for branching an output signal of the voltage controlled crystal oscillator for the channel; A mixer for mixing the intermediate frequency output from the first directional coupler and the local frequency provided; An offset frequency controller for variably outputting a voltage according to an output signal provided from the first directional coupler; A multiplexer for multiplexing and selectively outputting the output signal and the reference signal of the mixer according to a set selection signal; A phase detector for detecting a phase in an output signal of the multiplexer; A phase locked loop (PLL) for comparing a phase difference detected by the phase detector to determine a phase; An offset voltage controlled crystal oscillator for outputting an output signal of the phase locked loop by generating a + or − offset frequency according to a voltage level output from an offset frequency controller; And a second directional coupler for branching an output signal of the offset voltage controlled crystal oscillator and outputting the divided signal to the divider and the digital TV repeater, respectively. The frequency divider of claim 1, further comprising: a first divider for dividing an output signal of the first directional coupler at a set division ratio; A second divider which divides and outputs an output signal of the distributor at a set division ratio; A phase detector for detecting a phase in the output signals of the first and second dividers; And a phase locked loop (PLL) for determining a phase by comparing the phase difference detected by the phase detector.