KR20010058575A - Semiconductor package - Google Patents
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- KR20010058575A KR20010058575A KR1019990065925A KR19990065925A KR20010058575A KR 20010058575 A KR20010058575 A KR 20010058575A KR 1019990065925 A KR1019990065925 A KR 1019990065925A KR 19990065925 A KR19990065925 A KR 19990065925A KR 20010058575 A KR20010058575 A KR 20010058575A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
Description
본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 입출력 단자수를 극대화할 수 있는 BLP(Bottom Leaded Package)형 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a bottom leaded package (BLP) type semiconductor package capable of maximizing the number of input / output terminals.
BLP형 반도체패키지는 통상 마더보드에 실장되는 입출력 단자가 봉지재로 형성된 패키지몸체의 저면 또는 상면에 형성된 것을 지칭한다. 이러한 반도체패키지는 다수개를 적층하여 사용할 수 있음으로써, 마더보드에서 차지하는 실장면적이 작은 장점이 있다. 즉, 실장밀도가 높다. 따라서, 최근의 경박단소화되어 가는 전자기기에 주로 사용되고 있으며, 특히 메모리 용량을 적은 공간에서 늘려야 하는 경우, 그 메모리 반도체칩을 탑재한 반도체패키지로 주로 사용되고 있다.The BLP type semiconductor package generally refers to an input / output terminal mounted on a motherboard formed on a bottom or top surface of a package body formed of an encapsulant. Since the semiconductor package can be used by stacking a plurality of semiconductor packages, the mounting area occupied by the motherboard is small. That is, mounting density is high. Therefore, in recent years, it is mainly used in electronic devices that are becoming thin and short, and in particular, when it is necessary to increase the memory capacity in a small space, it is mainly used as a semiconductor package containing the memory semiconductor chip.
이러한 종래의 반도체패키지(100')가 도1a 및 도1b에 도시되어 있다.This conventional semiconductor package 100 'is shown in Figures 1A and 1B.
도시된 바와 같이 상면에 다수의 입출력패드(4')가 형성된 반도체칩(2')이 구비되어 있다. 상기 반도체칩(2')의 하면에는 그 하면 영역에서 외측 영역으로 연장되어 다수의 리드(10')가 위치되어 있다. 상기 리드(10')는 통상 반도체칩(2')을 중심으로 방사상으로 형성되어 있으며, 상기 리드(10')는 반도체칩(2')과 접착제나 접착테이프 등으로 접착되어 있다.As shown in the drawing, a semiconductor chip 2 'having a plurality of input / output pads 4' formed thereon is provided. On the lower surface of the semiconductor chip 2 ', a plurality of leads 10' are positioned extending from the lower surface region to the outer region. The lead 10 'is usually formed radially around the semiconductor chip 2', and the lead 10 'is bonded to the semiconductor chip 2' with an adhesive or an adhesive tape.
상기 리드(10')는 다수회 절곡되어 있다. 즉, 상기 반도체칩(2')의 하면이 탑재되는 제1리드부(11'), 상기 제1리드부(11')에 연장되어 상부로 절곡된 제2리드부(12'), 상기 제2리드부(12')로부터 외측으로 연장된 제3리드부(13')로 이루어져있다. 여기서, 상기 제1리드부(11')와 제3리드부(13')는 반도체칩(2')의 상면 또는 하면과 대략 수평면을 이룬다.The lead 10 'is bent many times. That is, the first lead portion 11 'on which the lower surface of the semiconductor chip 2' is mounted, the second lead portion 12 'extended to the first lead portion 11' and bent upwards, It consists of the 3rd lead part 13 'extended outward from the 2 lead part 12'. Here, the first lead portion 11 ′ and the third lead portion 13 ′ form a substantially horizontal plane with an upper surface or a lower surface of the semiconductor chip 2 ′.
상기 반도체칩(2')의 입출력패드(4')와 제1리드부(11')는 골드와이어 또는 알루미늄와이어와 같은 도전성와이어(21')에 의해 상호 접속되어 있다.The input / output pad 4 'and the first lead portion 11' of the semiconductor chip 2 'are connected to each other by a conductive wire 21' such as a gold wire or an aluminum wire.
또한, 상기 반도체칩(2'), 도전성와이어(21') 및 제1,2,3리드부(11',12',13')부는 봉지재로 봉지되어 소정의 패키지몸체(30')를 형성하고 있다.In addition, the semiconductor chip 2 ', the conductive wire 21', and the first, second, and third lead portions 11 ', 12', and 13 'are encapsulated with an encapsulant to seal the predetermined package body 30'. Forming.
여기서, 상기 제1리드부(11')는 그 하면이 패키지몸체(30') 하면으로 노출되어 있고, 제3리드부(13')는 그 상면이 패키지몸체(30') 상면으로 노출되어 있다. 따라서, 상기 반도체패키지(100')는 패키지몸체(30') 외측으로 노출된 제1리드부(11') 또는 제3리드부(13')가 마더보드에 실장 가능하게 된다.Here, the lower surface of the first lead portion 11 'is exposed to the lower surface of the package body 30', and the upper surface of the third lead portion 13 'is exposed to the upper surface of the package body 30'. . Therefore, in the semiconductor package 100 ', the first lead portion 11' or the third lead portion 13 'exposed to the outside of the package body 30' may be mounted on the motherboard.
한편, 최근의 반도체칩은 집적도 향상으로 인해 입출력패드의 개수가 증가함은 물론 파인피치화하고 있다. 그러나, 상기와 같은 반도체패키지는 반도체칩을 중심으로 리드가 방사상 한 개씩 형성되어 있음으로써, 마더보드에 실장되는 입출력 단자수에 한계가 있다. 즉, 입출력패드가 많은 반도체칩을 탑재하지 못하거나 또는 탑재한다 해도 반도체패키지의 전체적 크기를 크게 하여야 하는 문제점이 있다.On the other hand, the recent increase in the degree of integration of the semiconductor chip has increased the number of input and output pads, as well as fine pitch. However, the semiconductor package as described above has a limit on the number of input / output terminals mounted on the motherboard because the lead is formed radially around the semiconductor chip. That is, there is a problem that the overall size of the semiconductor package must be increased even if the I / O pad fails to mount or mounts many semiconductor chips.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 패키지몸체 상면 또는 하면으로 노출되는 입출력 단자의 개수를 극대화할 수 있는 반도체패키지의 제공하는데 있다.Accordingly, the present invention has been made to solve the above-described problems, and to provide a semiconductor package that can maximize the number of input and output terminals exposed to the upper or lower surface of the package body.
도1은 종래의 반도체패키지를 도시한 단면도 및 평면도이다.1 is a cross-sectional view and a plan view showing a conventional semiconductor package.
도2a 및 도2b는 본 발명의 제1실시예에 의한 반도체패키지를 도시한 단면도 및 평면도이다.2A and 2B are a cross-sectional view and a plan view showing a semiconductor package according to a first embodiment of the present invention.
도3은 본 발명의 제2실시예에 의한 반도체패키지를 도시한 단면도이다.3 is a cross-sectional view showing a semiconductor package according to a second embodiment of the present invention.
도4는 본 발명의 제3실시예에 의한 반도체패키지를 도시한 단면도이다.4 is a cross-sectional view showing a semiconductor package according to a third embodiment of the present invention.
도5는 본 발명의 제4실시예에 의한 반도체패키지를 도시한 단면도이다.5 is a cross-sectional view showing a semiconductor package according to a fourth embodiment of the present invention.
도6은 본 발명의 제5실시예에 의한 반도체패키지를 도시한 단면도이다.6 is a cross-sectional view showing a semiconductor package according to a fifth embodiment of the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
101,102,103,104,105; 본 발명에 의한 반도체패키지101,102,103,104,105; Semiconductor package according to the present invention
2; 반도체칩 4; 입출력패드2; Semiconductor chip 4; I / O pad
10; 리드 11; 제1리드부10; Lead 11; First lead part
12; 제2리드부 13; 제3리드부12; Second lead portion 13; Third lead part
11a,113a; 돌출부 14; 칩탑재판11a, 113a; Protrusion 14; Chip board
21; 도전성와이어 22; 도전성범프21; Conductive wires 22; Conductive Bump
23; 이방성 전도 필름 30; 패키지몸체23; Anisotropic conductive film 30; Package body
상기한 목적을 달성하기 위해 본 발명에 의한 본 발명에 의한 반도체패키지는 일면에 다수의 입출력패드가 구비된 반도체칩과; 상기 반도체칩을 중심으로 방사상 위치되며, 상기 반도체칩과 접속되는 제1리드부, 상기 제1리드부로터 상방을 향해 절곡된 제2리드부, 상기 제2리드부로부터 연장된 제3리드부로 이루어져 있으며, 상기 제1리드부의 하면 및 제3리드부의 상면에는 다수의 돌출부가 어레이되어 이루어진 리드와; 상기 반도체칩의 입출력패드와 제1리드부의 상면을 전기적으로 접속시키는 접속수단과; 상기 제1리드부 및 제3리드부의 돌출부가 외측으로 노출 또는 돌출되는 동시에, 상기 반도체칩, 도전성와이어 및 리드를 봉지재로 봉지하여 형성된 패키지몸체를 포함하여 이루어진 것을 특징으로 한다.The semiconductor package according to the present invention according to the present invention for achieving the above object is a semiconductor chip having a plurality of input and output pads on one surface; A first lead portion radially positioned around the semiconductor chip and connected to the semiconductor chip, a second lead portion bent upward from the first lead portion rotor, and a third lead portion extending from the second lead portion A lead having a plurality of protrusions arranged on a lower surface of the first lead portion and an upper surface of the third lead portion; Connection means for electrically connecting an input / output pad of the semiconductor chip to an upper surface of the first lead portion; The protrusions of the first lead portion and the third lead portion are exposed or protruded to the outside, and the package body is formed by encapsulating the semiconductor chip, the conductive wire, and the lead with an encapsulant.
여기서, 상기 반도체칩은 다수의 리드와 일정거리 이격된 칩탑재판상에 접착될 수 있다. 또한, 상기 반도체칩은 다수의 제1리드부 상면에 위치될 수 있다.Here, the semiconductor chip may be bonded to the chip mounting plate spaced apart from the plurality of leads by a predetermined distance. In addition, the semiconductor chip may be located on an upper surface of the plurality of first lead parts.
상기 반도체칩과 제1리드부의 접속수단은 도전성와이어, 도전성범프 또는 이방성 전도 필름 중 어느 하나로 할 수 있다.The connecting means of the semiconductor chip and the first lead portion may be any one of conductive wires, conductive bumps, and anisotropic conductive films.
상기 접속수단이 도전성범프 또는 이방성 전도 필름인 경우, 상기 반도체칩의 입출력패드가 상기 제1리드부의 상면을 향하도록 되어 있다.When the connecting means is a conductive bump or an anisotropic conductive film, the input / output pad of the semiconductor chip is directed toward the upper surface of the first lead portion.
또한, 상기 반도체패키지는 다수의 반도체패키지가 상,하방향으로 적층되어 있되, 어느 한 반도체패키지의 제1리드부에 형성된 돌출부가 다른 반도체패키지의 제3리드부에 형성된 돌출부와 접속되어 적층될 수 있다.In addition, the semiconductor package is a plurality of semiconductor packages are stacked in the vertical direction, the protrusion formed in the first lead portion of any one of the semiconductor package can be stacked in contact with the protrusion formed on the third lead portion of the other semiconductor package. have.
더불어, 상기 돌출부의 표면에는 도전성볼이 더 융착될 수 있다.In addition, the conductive ball may be further fused to the surface of the protrusion.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 패키지몸체의 상면 또는 하면으로 노출 또는 돌출된 돌출부가 어레이 형태로 형성됨으로써 보다 많은 입출력 단자수를 확보하게 되고, 따라서 다수의 입출력패드가 형성되고 파인피치화한 반도체칩을 용이하게 탑재할 수 있게 된다.As described above, according to the semiconductor package according to the present invention, the protrusions exposed or protruding from the upper or lower surface of the package body are formed in the form of an array, thereby securing a larger number of input / output terminals. Thus, a plurality of input / output pads are formed and pinned. Pitched semiconductor chips can be easily mounted.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a 내지 도6은 본 발명의 제1실시예 내지 제5실시예에 의한 반도체패키지(101,102,103,104,105)를 도시한 단면도이다.2A through 6 are cross-sectional views showing semiconductor packages 101, 102, 103, 104, and 105 according to the first to fifth embodiments of the present invention.
먼저 도2a 및 도2b의 반도체패키지(101)를 참조하여 본 발명의 기본 구조를 설명한다.First, the basic structure of the present invention will be described with reference to the semiconductor package 101 of FIGS. 2A and 2B.
도시된 바와 같이, 상면에 다수의 입출력패드(4)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 하면에는 리드(10)가 부착되어 있다. 상기 리드(10)는 통상 반도체칩(2)을 중심으로 방사상 위치되어 있으며, 크게 제1리드부(11), 제2리드부(12) 및 제3리드부(13)로 이루어져 있다. 즉, 상기 반도체칩(2)의 하면에 접착제로 접착되며, 대략 평탄한 제1리드부(11)와, 상기 제1리드부(11)에 연결되어서 상부로 절곡된 제2리드부(12)와, 상기 제2리드부(12)에 연결되며, 대략 평탄한 제3리드부(13)로 이루어져 있다.As illustrated, a semiconductor chip 2 having a plurality of input / output pads 4 formed thereon is provided on an upper surface thereof, and leads 10 are attached to a lower surface of the semiconductor chip 2. The lead 10 is generally radially positioned around the semiconductor chip 2 and includes a first lead portion 11, a second lead portion 12, and a third lead portion 13. That is, the first lead portion 11 which is adhered to the lower surface of the semiconductor chip 2 by an adhesive, and the second lead portion 12 which is connected to the first lead portion 11 and bent upwards, The third lead part 13 is connected to the second lead part 12 and is approximately flat.
상기 제1리드부(11)의 하면에는 다수의 돌출부(11a)가 형성되어 있으며, 또한 제3리드부(13)의 상면에도 다수의 돌출부(13a)가 형성되어 있다.A plurality of protrusions 11a are formed on the lower surface of the first lead portion 11, and a plurality of protrusions 13a are formed on the upper surface of the third lead portion 13.
상기 제1리드부(11), 제2리드부(12) 및 제3리드부(13)의 절곡된 형태는 통상 기계적 프레싱 기술에 의해 형성되며, 상기 제1리드부(11) 및 제3리드부(13)의 돌출부(11a,13a)는 부분 에칭 기술(소위, 할프에칭이라고도 함)에 의해 형성된 것이다. 즉, 제1리드부(11) 및 제3리드부(13)중 소정 영역을 제외한 나머지 영역을 부분적으로 더 에칭함으로써, 상기와 같은 돌출부(11a,13a)를 형성한 것이다.The bent shape of the first lead portion 11, the second lead portion 12 and the third lead portion 13 is usually formed by a mechanical pressing technique, the first lead portion 11 and the third lead The protrusions 11a and 13a of the portion 13 are formed by a partial etching technique (also called half etching). That is, the above protruding portions 11a and 13a are formed by partially etching the remaining regions of the first lead portion 11 and the third lead portion 13 except for the predetermined region.
상기 반도체칩(2)의 입출력패드(4)와 제1리드부(11)의 상면은 골드와이어 또는 알루미늄와이어와 같은 도전성와이어(21)에 의해 상호 접속되어 있다. 따라서, 상기 반도체칩(2)의 전기적 신호는 입출력패드(4), 도전성와이어(21) 및 리드(10)를 통해 외부의 마더보드 등에 출력(또는 입력)된다.The upper surface of the input / output pad 4 and the first lead portion 11 of the semiconductor chip 2 are connected to each other by a conductive wire 21 such as a gold wire or an aluminum wire. Accordingly, the electrical signal of the semiconductor chip 2 is output (or input) to an external motherboard through the input / output pad 4, the conductive wire 21, and the lead 10.
상기 반도체칩(2), 도전성와이어(21) 및 리드(10)는 봉지재로 봉지됨으로써 반도체패키지(101)의 외형을 이루는 패키지몸체(30)가 형성되어 있다.The semiconductor chip 2, the conductive wire 21, and the lead 10 are encapsulated with an encapsulant so that the package body 30 forming the outline of the semiconductor package 101 is formed.
여기서, 상기 패키지몸체(30)의 상면 및 하면으로는 제1리드부(11) 및 제3리드부(13)의 돌출부(11a,13a) 단부가 노출되거나 또는 돌출되어 형성됨으로써, 상기 돌출부(11a,13a)가 마더보드의 소정 패턴에 실장 가능하게 되어 있다.Here, the upper and lower surfaces of the package body 30 are formed by exposing or protruding end portions of the protrusions 11a and 13a of the first lead portion 11 and the third lead portion 13 to form the protrusions 11a. (13a) can be mounted on a predetermined pattern of the motherboard.
또한, 상기 돌출부(11a,13a)의 표면에는 실장이 용이하게 이루어지도록 솔더가 도금되거나 또는 솔더볼과 같은 도전성볼이 융착될 수 있다.(도시되지 않음))In addition, solder may be plated or conductive balls such as solder balls may be fused to the surfaces of the protrusions 11a and 13a to facilitate mounting.
한편, 도3의 반도체패키지(102)에서와 같이 반도체칩(2)의 하면에는 제1리드부(11)와 일정거리 이격된 칩탑재판(14)이 위치될 수 있으며, 동시에 상기 칩탑재판(14)에 반도체칩(2)이 접착되어 고정될 수 있다. 또한, 상기 칩탑재판(14)의 하면은 패키지몸체(30) 하면으로 노출됨으로써, 상기 칩탑재판(14)이 히트싱크의 역할을 하여 반도체칩(2)의 방열 성능을 향상시킬 수 있게 된다.Meanwhile, as in the semiconductor package 102 of FIG. 3, the chip mounting plate 14 spaced apart from the first lead portion 11 by a predetermined distance may be located on the bottom surface of the semiconductor chip 2, and at the same time, the chip mounting plate The semiconductor chip 2 may be bonded and fixed to the 14. In addition, the lower surface of the chip mounting plate 14 is exposed to the lower surface of the package body 30, so that the chip mounting plate 14 serves as a heat sink to improve the heat dissipation performance of the semiconductor chip (2). .
또한, 도4의 반도체패키지(103)에서와 같이 반도체칩(2)과 리드(10)의 접속을 플립칩 기술을 이용하여 형성할 수도 있다. 즉, 반도체칩(2)의 입출력패드(4)에 미리 도전성범프(22)(예를 들면, 골드나 솔더범프)를 형성하고, 상기 반도체칩(2)을 뒤집은 상태로 도전성범프(22)의 위치와 제1리드부(11)의 위치를 정렬한 후 리플로우 시킴으로써, 상기 도전성범프(22)가 상기 입출력패드(4)와 제1리드부(11)를 접속하게 한 것이다. 이러한 반도체패키지(103)는 제조 공정중 반도체칩(2)과 제1리드부(11)의 접속을 한번에 수행할 수 있는 장점이 있다.In addition, as in the semiconductor package 103 of FIG. 4, the connection between the semiconductor chip 2 and the lead 10 may be formed using flip chip technology. That is, the conductive bumps 22 (for example, gold or solder bumps) are formed on the input / output pads 4 of the semiconductor chip 2 in advance, and the conductive bumps 22 of the conductive bumps 22 are turned over. The conductive bumps 22 connect the input / output pads 4 and the first lead portions 11 by reflowing after aligning the positions with the positions of the first lead portions 11. The semiconductor package 103 has an advantage in that the semiconductor chip 2 and the first lead portion 11 can be connected at a time during the manufacturing process.
계속해서, 도5의 반도체패키지(104)에서와 같이 반도체칩(2)과 리드(10)의 접속을 이방성 전도 필름(23)(ACF; Anisotropic Conductive Film)을 이용하여 수행할 수도 있다.Subsequently, as in the semiconductor package 104 of FIG. 5, the connection between the semiconductor chip 2 and the lead 10 may be performed using an anisotropic conductive film 23 (ACF).
상기 이방성 전도 필름(23)이란, 일반적인 접착 필름과 전도용금속알갱이가 혼합된 것으로 상기 접착 필름의 두께는 약 50μm 정도이고 전도용금속알갱이의 지름은 약 5μm 정도이다. 또한 상기 전도용금속알갱이의 표면은 얇은 폴리머(Polymer)로 코팅되어 있으며, 이러한 이방성 전도 필름(23)의 소정의 영역에 열 또는 압력을 가하게 되면 그 부분의 전도용금속알갱이를 감싸고 있는 폴리머가 녹게되어 전도성을 갖게 되고 그외의 부분은 확실한 절연성을 유지하는 특성을 가지고 있기 때문에 상호 접속될 부분의 위치 맞춤이 용이하다. 즉, 플립칩 기술을 이용한 접속 방법(도4참조)은 반도체칩(2)의 입출력패드(4) 또는 도전성범프(22)의 위치와 제1리드(11)의 위치를 정확히 일치시킨 후 리플로(Reflow)하여야 하지만,상기 이방성 전도 필름(23)을 이용한 경우에는 이러한 고정도의 위치 맞춤이 필요하지 않은 장점이 있다.The anisotropic conductive film 23 is a mixture of a general adhesive film and conductive metal grains, the thickness of the adhesive film is about 50μm and the diameter of the conductive metal grains is about 5μm. In addition, the surface of the conductive metal grains is coated with a thin polymer (Polymer), and when a heat or pressure is applied to a predetermined region of the anisotropic conductive film 23, the polymer surrounding the conductive metal grains of the portion is melted and conductive Since the other parts have the property of maintaining a certain insulating property, it is easy to align the parts to be interconnected. That is, in the connection method using flip chip technology (see FIG. 4), the position of the input / output pad 4 or the conductive bump 22 of the semiconductor chip 2 and the position of the first lead 11 are exactly matched and then reflowed. (Reflow) However, in the case of using the anisotropic conductive film 23 there is an advantage that does not require this highly accurate positioning.
계속해서, 도6에 도시된 반도체패키지(105)와 같이 적어도 2개 이상의 반도체패키지를 적층하여 하나의 반도체패키지(105)로 구비할 수 있다. 즉, 한 반도체패키지의 패키지몸체(30) 하면으로 노출된 돌출부(11a)를 다른 반도체패키지의 패키지몸체(30) 상면으로 노출된 돌출부(13a)와 위치를 맞추고, 솔더 등을 이용하여 상호 접속한 것이다. 상기와 같은 반도체패키지(105)는 특히 메모리용 반도체칩(2)을 탑재한 경우 적은 면적에서 고용량의 메모리를 확보할 수 있는 장점이 있다.Subsequently, as in the semiconductor package 105 shown in FIG. 6, at least two or more semiconductor packages may be stacked and provided as one semiconductor package 105. That is, the protrusions 11a exposed to the bottom surface of the package body 30 of one semiconductor package are aligned with the protrusions 13a exposed to the top surface of the package body 30 of the other semiconductor package, and interconnected by solder or the like. will be. The semiconductor package 105 as described above has an advantage in that a high capacity memory can be secured in a small area, particularly when the memory semiconductor chip 2 is mounted.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
상기와 같이 하여 본 발명에 의한 반도체패키지는 패키지몸체 상,하면으로 노출 또는 돌출되는 돌출부를 어레이시켜 형성할 수 있음으로써 다수의 입출력 단자를 확보할 수 있는 효과가 있다.As described above, the semiconductor package according to the present invention can be formed by arranging protrusions exposed or protruded on the package body and the bottom surface, thereby securing a plurality of input / output terminals.
또한, 이러한 반도체패키지를 다수 적층시켜 하나의 반도체패키지로 구비할 수 있음으로써 고용량의 메모리 등을 얻을 수 있는 효과가 있다.In addition, since a plurality of such semiconductor packages can be stacked and provided as one semiconductor package, a high capacity memory or the like can be obtained.
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