KR20010057766A - A device of sar packet memory controller in mpls label edge router - Google Patents

Abstract

PURPOSE: An apparatus for controlling an SAR(Segmentation And Reassembly) packet memory in an edge router of an MPLS(Multi-Protocol Label Switching) network, is provided to improve process speed and reduce the cost for manufacturing the apparatus, by controlling a packet memory arbitration function between interface functions. CONSTITUTION: A CPU interface part(1) monitors and manages a function of a control apparatus. A packet memory interface part(2) reads and writes transmission reception data and IP(Internet Protocol) header from/in a packet memory(11). An IP lookup process block interface part(3) transfers the IP header received from the packet memory(11) to an IP lookup process block(12). The interface part(3) receives an updated IP header and sends it to the interface part(2) via a transmission reception memory arbitration part(4). An SAR control memory process block interface part(5) interfaces with an SAR control memory process block. An SAR transmission block interface part(7) sends a transmission packet to an SAR transmission block. The arbitration part(4) arbitrates an access to the packet memory(11) by each interface part.

Description

A DEVICE OF SAR PACKET MEMORY CONTROLLER IN MPLS LABEL EDGE ROUTER}

The present invention relates to a split / recombine (SAR) packet memory controller in an edge router of a multiprotocol label switching (MPLS) network. In particular, the present invention relates to a transmission / receipt packet memory control and an internet protocol in an edge router of a multiprotocol label switching network. IP) The present invention relates to a separate / recombined packet memory control device capable of high-speed processing by integrating read / write of a header of a packet so as to be controlled by one device.

With the increase in the amount of information handled by individuals using the Internet and the amount of communication between them, users' demand for information and communication services has gradually advanced to the trend of advancement, diversification, and personalization, and it is necessary to provide high quality, high speed, and high capacity services. . In order to provide Internet services satisfying various needs of users, a multi-protocol label switching (MPLS) method based on an asynchronous transfer mode (ATM) method has emerged.

Multiprotocol Label Switching (MPLS) is a method of delivering Internet Protocol (IP) packets based on a unified routing scheme, using a fixed-length label instead of the traditional longest match method, and introducing a link layer switching technique. This label is the core of the Multiprotocol Label Switching (MPLS) scheme, and has almost the same meaning as the Virtual Path Identifier (VPI) / Virtual Channel Identifier (VCI) in ATM. The label is used as a designator indicating a Label Switched Path (LSP) for a specific Forwarding Equivalency Class (FEC), and has a meaning limited to a Label Switching Router (LSR). Equivalently, ATM's VPI / VCI is used as a designator for a virtual connection (VC) connected between both ends and has a localized meaning at each node. Therefore, the ATM-based MPLS system can be easily configured using the existing ATM fast switching technology as the link layer switch technology of multiprotocol label switching (MPLS). The ATM based MPLS system is largely composed of a Label Switching Router (LSR) in an ATM network and a Label Edge Router (LER) present at the boundary between the ATM network.

The Label Switching Router (LSR) uses ATM switching to transmit at high speeds for cells with fixed-length labels (VPI / VCI), while the Label Edge Router (LER) uses ATM's switching platform to split packets. And Segmentation And Reassembly (SAR) to deliver and receive cells. In particular, in the label edge router (LER), the interworking with the lookup function and the separation and reassembly (SAR) function of the IP packet header becomes an important factor of the performance.

Accordingly, the present invention is applied to an edge router of a multiprotocol label switching network to provide a separation and recombination (SAR) transmission and reception block matching function, packet memory matching function, and IP lookup processing block matching function, and between these matching functions. By controlling the packet memory arbitration function according to the priority set by the CPU, the memory access function for the IP packet header and the transmit / receive packet memory processing function are performed in parallel to enable high-speed processing of 622Mbps. An object of the present invention is to provide an apparatus for separating / recombining (SAR) packet memory in an edge router of a multiprotocol label switching (MPLS) network, which can be manufactured by using one device.

1 is a block diagram of a separate / recombined packet memory controller according to the present invention;

2 is a packet memory access arbitration timing diagram in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

1: CPU matching unit 2: Packet memory matching unit

3: IP lookup processing block matching unit 4: Transmit / receive memory arbitration unit

5: matching / disassembly (SAR) control memory processing block matching unit

6: Receive / Recombine (SAR) receiving block matching unit

7: SAR transmission block matching unit

In order to achieve the above object, the present invention provides a split / recombine (SAR) packet memory controller in an edge router of a multiprotocol label switching network, wherein the state of the packet memory and the controller in an external central processing unit (CPU) / A central processing unit matching means for monitoring a control function and providing an interface function with the central processing unit; Packet memory matching means for recording or reading the packet data and the IP header into the packet memory; IP lookup processing block matching means for transferring the IP header read by the packet memory matching means to the IP lookup processing block, and delivering the IP header updated by the IP lookup processing block to the packet memory matching means; Separation / recombination control memory processing block matching means for providing a matching function with the separation / recombination control memory processing block; Packet receiving block matching means for providing a matching function with the packet receiving block; Packet transmission block matching means for providing a matching function with the packet transmission block; And transmitting / receiving arbitration of access to the packet memory according to priority when the external packet receiving block, the packet transmitting block, and the IP lookup processing block attempt to access the packet memory through the matching means. And memory arbitration means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an apparatus for separating and reassembling (SAR) packet memory according to the present invention.

The present invention largely relates to a central processing unit (CPU) matching unit (1) and a packet memory (11) for monitoring and managing the state and control functions of the packet memory and the controller of the present invention in the central processing unit (CPU). The packet memory matching unit 2 reads and writes the transmission / reception packet data and the IP header, and the IP header received from the packet memory 11 is transmitted to the IP lookup processing block 12, and the updated IP header is received and transmitted. SAR control that performs matching function between the IP lookup processing block matching unit 3 and the separation and reassembly (SAR) control memory processing block, which are transmitted to the packet memory matching unit 2 through the reception / memory arbitration unit 4; A memory processing block matching unit 5, a SAR receiving block matching unit 6 for transmitting a received packet from the SAR receiving block 13, a SAR transmission block matching unit 7 for transmitting a transmission packet to a SAR transmission block, and In each of these matching units, a transmission / mediation mediating access to the packet memory 11 is performed. And a new memory arbitration unit (4).

The CPU matching section 1 also includes a CPU interface arbitration section that provides an interface function with the CPU, a command decoder for decoding instructions input from the CPU, a status / control register for storing status and control data, and data to be transmitted. A transmission memory for storing the data, a reception memory for storing the received data, and a memory arbitration interface for providing an interface function with the transmission / reception memory arbitration section 4.

The control device according to the present invention processes IP packets and OAM cells.

First, we look at the process of processing an IP packet.

When one packet is received, the SAR reception block 13 transmits a usage request signal of the bus to the transmission / reception memory arbitration section 4 through the SAR reception block matching section 6. When the license signal of the bus is received from the transmission / reception memory arbitration section 4, the transmission / reception memory arbitration section 4 is notified that the bus is in use, and the SAR reception block matching section 6 and the packet memory matching section are received. The packet received through (2) is stored in the packet memory 11.

When one packet is stored in the packet memory 11, the SAR control memory processing block 15 transmits / receives the received packet information including the length and position information of the received packet through the SAR control memory processing block matching unit 5. When forwarded to the reception memory arbitration section 4, the transmission / reception memory arbitration section 4 grants the right to use the bus and delivers the reception packet information to the packet memory matching section 2. The packet memory matching unit 2 reads the corresponding IP header from the packet memory according to the received packet information, and processes the IP header and SAR control memory read into the IP lookup processing block 12 through the IP lookup processing block matching unit 3. The received packet information transmitted from the block 15 is transferred.

When the IP header processing is completed by the IP lookup processing block 12, the access right to the packet memory is obtained through the transmission / reception memory arbitration unit 4, and then the IP lookup processing block matching unit 3 is executed. And the updated IP header in the packet memory through the packet memory matching unit 2 to generate a transmission packet corresponding to the received packet. At the same time, the transmission packet information having the length and position information on the transmission packet is transmitted to the SAR control memory processing block 15 so that the transmission packet can be read by the SAR transmission block 14.

In the SAR transmission block 14, the SAR transmission block matching unit 7 requests access authority for the packet memory to the transmission / reception memory arbitration unit 4, obtains the access authority, and then transfers the transmitted data. The transmission packet stored in the packet memory 11 is read and transmitted through the SAR transmission block matching unit 7 and the packet memory matching unit 2 based on the packet information.

Next, a process of processing a reception operation maintenance (OAM) cell from the SAR reception block 13 will be described.

As described above, the SAR receiving block 13 obtains the access right to the packet memory from the transmitting / receiving memory arbitration unit 4, and then matches the received OAM cell with the SAR receiving block matching unit 6 and the packet memory matching. The data is stored in the packet memory 11 via the unit 2. In addition, the SAR control memory processing block 15 transmits the received OAM cell information having position information on the receiving OAM cell to the transmit / receive memory arbitration unit 4 through the SAR control memory processing block matching unit 5, The transmit / receive memory arbitration section 4 grants access rights to the packet memory and delivers the received OAM cell information to the packet memory matching section 2. Then, the packet memory matching unit 2 reads the corresponding receiving OAM cell from the packet memory 11, stores it in the receiving memory of the CPU matching unit 1, and informs the CPU of this. As a result, the central processing unit (CPU) reads the OAM cell stored in the reception memory of the CPU matching unit 1.

Next, a process of processing an OAM cell to be transmitted is as follows.

When the central processing unit (CPU) stores the OAM cell to be transmitted in the transmission memory of the CPU matching unit 1 and notifies it, the transmission / reception memory arbitration unit 4 reads the OAM cell to be transmitted and matches the packet memory. It transfers it to the part 2, so that it may be stored in the packet memory 11. Then, the OAM cell information to be transmitted is transmitted to the SAR control memory processing block 15. Then, the SAR transmission block 14 obtains the access right to the packet memory through the transmission / reception memory arbitration unit 4, and then reads and transmits the OAM cell to be transmitted from the packet memory 11.

In the present invention, the CPU matching unit 1, the SAR receiving block matching unit 6, the SAR transmitting block matching unit 7, the SAR control memory processing block matching unit 5, and the IP lookup processing block matching unit 3 In each case, the bus use request signal is sent to access the external packet memory 11, and the transmit / receive memory arbitration unit 4 sends the bus use permission signal according to the priority set in the matching unit. In each block that requests the use of the bus, when the bus use permission signal is received, the bus use signal is sent to the transmission / reception memory arbitration unit 4 and the bus is used.

A timing diagram for this operation is shown in FIG.

As shown in Fig. 2, when a bus use request signal is generated, a bus license signal is generated according to the priority by the transmit / receive memory arbitration unit. Then, the bus busy signal is received in a block that receives the bus license signal. Occurs.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention as described above, it provides a SAR transmission and reception block matching function, packet memory matching function and IP lookup processing block matching function, and provides a memory arbitration function between these matching functions, an important factor of performance in the MPLS edge router The memory access function for the IP packet header and the transmit / receive packet memory processing function are performed in parallel, thereby enabling the high-speed processing of 622 Mbps and reducing the manufacturing cost by using one device.

Claims (3)

An apparatus for separating / recombining (SAR) packet memory in an edge router of a multiprotocol label switching network, Central processing unit matching means for monitoring a state / control function of the packet memory and the control unit in an external CPU and providing an interface function with the central processing unit; Packet memory matching means for recording or reading the packet data and the IP header into the packet memory; IP lookup processing block matching means for transferring the IP header read by the packet memory matching means to the IP lookup processing block, and delivering the IP header updated by the IP lookup processing block to the packet memory matching means; Separation / recombination control memory processing block matching means for providing a matching function with the separation / recombination control memory processing block; Packet receiving block matching means for providing a matching function with the packet receiving block; Packet transmission block matching means for providing a matching function with the packet transmission block; And Transmit / receive memory for arbitrating access to the packet memory according to priority when accessing the packet memory from the external packet receiving block, the packet transmitting block, and the IP lookup processing block through the matching means Arbitration Means Separator / recombination packet memory controller in the edge router of the multi-protocol label switching network comprising a. The method of claim 1, The central processing unit matching means, A central processing unit interface arbitration means for providing an interface function with the central processing unit; Decoding means for decoding the command data inputted through the central processing unit interface arbitration means; A status / control register for storing status and control data; A transmission memory for storing data to be transmitted; A receiving memory for storing the received data; And Memory arbitration unit interface means for providing an interface function with the transmission / reception memory arbitration means Separation / recombination packet memory control device in the edge router of the multi-protocol label switching network comprising a. The method according to claim 1 or 2, The transmitting / receiving memory arbitration means arbitrates access to the packet memory according to a priority determined in advance and delivered by the central processing unit. Separation / recombination at the edge router of the multiprotocol label switching network. Packet memory controller.