KR20010048185A - Apparatus for generating interrupt - Google Patents

Abstract

PURPOSE: An interrupt processor is provided to process generated interrupts by generating a carry signal from N bits counter in case that an interrupt is generated for more fixed times, by combining the carry signal with an interrupt signal, and by applying the signal to a microprocessor. CONSTITUTION: An AND gate(300) receives the M number of external interrupts. The signals are logically multiplied. A buffer(310) confirms whether a microprocessor(320) generates what sort of external interrupt. The microprocessor(320) processes the external interrupt generated. In case that the interrupt is changed into '0' from '1', the microprocessor(320) receives and processes the interrupt. An OR gate(330) logically sums up an output of the AND gate(300) and a carry signal output of an N bits counter(340).

Description

Interrupt processing unit {Apparatus for generating interrupt}

The present invention relates to an interrupt processing apparatus. In particular, when a microprocessor is processing an interrupt in an interrupt generator of a method of applying a microprocessor after combining several interrupts to generate a single interrupt, when another interrupt occurs, It relates to an interrupt handler that can handle all other interrupts that have occurred.

Hereinafter, an interrupt processing apparatus according to the prior art will be described with reference to the accompanying drawings.

1A is a diagram showing a circuit configuration of an interrupt processing apparatus according to the prior art, and FIG. 1B is an interrupt processing timing diagram of the interrupt processing apparatus shown in FIG. 1A.

The prior art illustrated in FIG. 1A combines the external M interrupt signals and applies them to the microprocessor 110.

When the M external interrupts are "0", they are inputted to the AND gate 100 as signals for requesting interrupts, and the output signal of the AND gate 100 is input to the microprocessor 110. Therefore, the microprocessor 110 checks whether the interrupt source is an external interrupt source through the buffer 120 when an interrupt occurs, and processes the interrupt according to the interrupt request signal input from the AND gate 100 in the case of the interrupt source.

This conventional technology has a problem when the interrupt recognition method of the microprocessor 110 recognizes that the interrupt signal changes from "1" to "0".

That is, as shown in FIG. 1B, when all interrupt sources are “1” and an interrupt occurs at INT-0, the output of the AND gate 100 is changed from “1” to “0.” At this time, the microprocessor 110 ) Recognizes the interrupt and handles the interrupt associated with INT-0. If an interrupt occurs at INT-1 or another interrupt source during INT-0 interrupt processing, the output of AND gate 100 remains unchanged and the microprocessor 110 does not recognize the occurrence of the interrupt, there is a problem that can not perform interrupt processing for work related to INT-1 or other interrupt source, that is, INT-1 or other interrupt source.

FIG. 2A is a diagram showing another example of a circuit configuration of an interrupt processing apparatus according to the prior art, and FIG. 2B is an interrupt processing timing diagram of the interrupt processing apparatus shown in FIG. 2A.

Another example of the prior art shown in FIG. 2A is similar to the technique shown in FIG. 1A, the difference being that when the external interrupt becomes “1”, it requires an interrupt and AND of FIG. 1A to combine the external interrupt signal. OR gate 200 is used instead of the gate.

The microprocessor 210 also recognizes when the interrupt signal changes from " 0 " to " 1. "

Therefore, when the interruption occurs at another interrupt source during the INT-0 interrupt processing as shown in FIG. 2B, the microprocessor 210 does not recognize the interrupt and thus fails to process the interrupt. do. Therefore, a big problem occurs that the stability of the system is degraded.

Accordingly, an object of the present invention is to solve the problems according to the prior art. The object of the present invention is to create a single interrupt by combining several interrupts, and then apply the microprocessor to a microprocessor in the interrupt generator. An interrupt handler is provided to handle other interrupts that occur when another interrupt occurs while the interrupt is being processed.

In order to achieve the above object, a feature of the present invention is to use an N-bit counter, and if an interrupt is continuously generated for a predetermined time, the N-bit counter generates a carry signal and combines the interrupt signal with a microprocessor. By applying this, all interrupts generated are handled.

That is, the interrupt processing apparatus according to the present invention is characterized in that the interrupt processing apparatus comprises: a first logic operation unit for receiving a plurality of external interrupts and performing a logical operation on the received plurality of interrupts; A storage unit which stores a plurality of external interrupt signals; A counting unit which starts counting according to a logic operation result signal output from the first logical calculating unit and outputs a carry signal according to an output value of any N bits; A second logic operation unit configured to perform a logical operation on the carry signal output from the coefficient unit and a signal output from the first logic operation unit; And an interrupt processor for recognizing an interrupt according to a logic operation result of the second logic operator and processing an external interrupt generated by reading the storage.

In addition, another aspect of the present invention provides an interrupt processing apparatus comprising: a first logical operation unit for receiving a plurality of external interrupts and performing a logical operation on the received plurality of interrupts; A storage unit which stores a plurality of external interrupt signals; A first inverting unit for inverting the output signal of the first logical operation unit; A counting unit which starts counting according to the signal inverted by the first inverting unit and outputs a carry signal according to an output value of any N bits; A second inverting unit for inverting the carry signal output from the counting unit; A second logic operation unit configured to perform a logic operation on the signal inverted by the second inverting unit and a signal output from the first logic operation unit; And an interrupt processor for recognizing an interrupt according to a logic operation result of the second logic operator and processing an external interrupt generated by reading the storage.

1A is a diagram showing a circuit configuration of an interrupt processing apparatus according to the prior art, and FIG. 1B is an interrupt processing timing diagram of the interrupt processing apparatus shown in FIG. 1A;

2A is a diagram showing another example of a circuit configuration of an interrupt processing apparatus according to the prior art, and FIG. 2B is an interrupt processing timing diagram of the interrupt processing apparatus shown in FIG. 2A;

3A is a diagram showing a circuit configuration of an interrupt processing apparatus according to the first embodiment of the present invention, and FIG. 3B is an interrupt processing timing diagram of the interrupt processing apparatus shown in FIG.

4A is a diagram showing a circuit configuration of an interrupt processing apparatus according to the second embodiment of the present invention, and FIG. 4B is an interrupt processing timing diagram of the interrupt processing apparatus shown in FIG. 4A.

<Explanation of symbols for main parts of drawing>

300, 430: AND gate 310, 410: buffer

320, 420: microprocessor 330, 400: OR gate

340, 440: counter 450, 460: NOT gate

Hereinafter, an interrupt processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings for each embodiment.

(First embodiment)

3A is a diagram showing a circuit configuration of an interrupt processing apparatus according to the first embodiment of the present invention. FIG. 3B is an interrupt processing timing diagram of the interrupt processing apparatus shown in FIG. 3A. Looking at, it is composed of an AND gate 300, a buffer 310, a microprocessor 320, an OR gate 330 and an N-bit counter 340.

The AND gate 300 receives and multiplies M external interrupts. When the external interrupt is "0", the AND gate 300 generates an interrupt. When the external interrupt occurs, the AND gate 300 outputs "0".

The buffer 10 is used to determine which external interrupt occurs in the microprocessor 320 when an interrupt occurs. The microprocessor 320 processes the generated external interrupt.

When the interrupt is changed from "1" to "0", the microprocessor 320 receives and processes the interrupt. The OR gate 330 logically sums the output of the AND gate 300 and the carry signal output of the N-bit counter 340, and outputs "1" to the microprocessor if any one of the two output signals is "1".

The N-bit counter 340 starts counting when the output of the AND gate 300 is "0", and generates a carry signal "1" when the output of N bits is all "1", thereby generating the OR gate 330. Will output That is, the counting is started only when the signal output from the AND gate 300 is provided as a reset and enable / reset signal of the N-bit counter 340 so that "0" is output from the AND gate 300. .

The operation of the interrupt processing apparatus according to the first embodiment of the present invention having such a configuration will be described.

As shown in FIG. 3B, the initial state is that all external interrupts are "1", the output of the AND gate 300 and the output of the OR gate 330 are "1", and the N-bit counter 340 resets. ), The N bit counter 340 outputs all "0" and the carry output also becomes "0". At this time, when the interrupt occurs in the external interrupt INT-0, the output of the OR gate 330 is changed from "1" to "0", when the microprocessor 320 changes from "1" to "0", It recognizes an interrupt and reads the buffer 310 to process an external interrupt generated.

In addition, from this time, the N-bit counter 340 operates, and after a predetermined time, the outputs of the N-bit counter 340 are all "1" and the carry output is "1", and the carry output is "0" at the next clock. The output of the OR gate 330 changes from "1" to "0." At this time, the microprocessor 320 recognizes the interrupt and reads the buffer 310 to process the generated external interrupt.

When all external interrupts are processed, the output of AND gate 300 changes to " 1 " and N-bit counter 340 is reset to stop operation. Therefore, even if another external interrupt occurs before the first external interrupt occurs, the interrupt can be processed.

(Second embodiment)

4A is a diagram showing a circuit configuration of an interrupt processing apparatus according to the second embodiment of the present invention, and FIG. 4B is an interrupt processing timing diagram of the interrupt processing apparatus shown in FIG. 4A.

As shown in FIG. 4A, the second embodiment of the present invention includes an OR gate 400, a buffer 410, a microprocessor 420, an AND gate 430, an N-bit counter 440, and a NOT gate 450. 460).

The OR gate 400 receives and ORs M external interrupts. When the external interrupt is “1”, the OR gate 400 generates an interrupt. The OR gate 400 outputs “1” when any external interrupt occurs. .

The buffer 410 is used to determine which external interrupt has occurred when the microprocessor 420 generates an interrupt, and the microprocessor 420 processes the generated external interrupt. The microprocessor 420 receives and processes the interrupt when the interrupt is changed from "0" to "1".

The AND gate 430 logically multiplies the output of the OR gate 400 and the output of the N-bit counter 440, and outputs “0” if any one of the two output signals is “0”.

The N-bit counter 440 starts counting when the output of the OR gate 400 is "1", and generates a carry output signal "1" when all of the N-bit outputs are "1".

The NOT gate 450 inverts the carry output signal " 1 " generated by the N-bit counter 440 to " 0 " and then outputs the result to the microprocessor 420.

In addition, the NOT gate 460 inverts the output signal of the OR gate 400 to provide the reset signal and the enable signal of the N-bit counter 440.

The operation of the interrupt processing apparatus according to the second embodiment of the present invention having such a configuration will be described.

As shown in FIG. 4B, the initial state is that all external interrupts are "0", the output of the AND gate 430 and the output of the OR gate 400 are "0", and the N-bit counter 440 resets. N bit counter 440 is all "0", and the carry output is also "0". At this time, when an interrupt occurs in the external interrupt INT-0, the output of the AND gate 430 is changed from "0" to "1", when the microprocessor 420 changes from "0" to "1", An interrupt is recognized and the external interrupt generated by reading the buffer 410 is processed.

In addition, since the N-bit counter 440 operates from this time, all outputs of the N-bit counter 440 become "1" and the carry output becomes "1", and the carry output becomes "0" at the next clock. As a result, the output of the AND gate 430 changes from "0" to "1." At this time, the microprocessor 420 recognizes the interrupt and reads the buffer 410 to process the generated external interrupt.

When all external interrupts are processed, the output of OR gate 400 changes to " 0 ", and N-bit counter 440 is reset to stop operation. Therefore, even if another external interrupt occurs before the first external interrupt is processed, the interrupt can be handled.

As described above, the interrupt processing apparatus according to the present invention uses an N-bit counter. If an interrupt continues to occur for a predetermined time, the N-bit counter generates a carry signal and combines the interrupt signal to the microprocessor. By granting, all interrupts generated are handled.

Therefore, even if another interrupt occurs during the interrupt processing, it is possible to handle the other interrupt generated, thereby improving the stability of the system.

Claims (8)

In the interrupt processor, A first logic calculating section for receiving a plurality of external interrupts and performing a logic operation on the received plurality of interrupts; A storage unit which stores a plurality of external interrupt signals; A counting unit which starts counting according to a logic operation result signal output from the first logical calculating unit and outputs a carry signal according to an output value of any N bits; A second logic operation unit configured to perform a logical operation on the carry signal output from the coefficient unit and a signal output from the first logic operation unit; And an interrupt processing unit for recognizing an interrupt according to a logical operation result of the second logical operation unit and processing an external interrupt generated by reading the storage unit. The method of claim 1, And the first logic operation portion is an AND gate, and the second logic operation portion is an or gate. The method according to claim 1 or 2, The counting unit starts counting when the signal output from the first logic calculating unit is "0" and outputs a carry output signal "0" to the second logic calculating unit when all N bits are output as "1". Interrupt processing unit. The method of claim 1, And the interrupt processing unit recognizes an interrupt when the output of the second logic operation unit changes from "1" to "0". In the interrupt processor, A first logic calculating section for receiving a plurality of external interrupts and performing a logic operation on the received plurality of interrupts; A storage unit which stores a plurality of external interrupt signals; A first inverting unit for inverting the output signal of the first logical operation unit; A counting unit which starts counting according to the signal inverted by the first inverting unit and outputs a carry signal according to an output value of any N bits; A second inverting unit for inverting the carry signal output from the counting unit; A second logic operation unit configured to perform a logic operation on the signal inverted by the second inverting unit and a signal output from the first logic operation unit; And an interrupt processing unit for recognizing an interrupt according to a logical operation result of the second logical operation unit and processing an external interrupt generated by reading the storage unit. The method of claim 5, Wherein the first logic operation unit is an OR gate, the second logic operation unit is an AND gate, and the first and second inverting units are NOT gates. The method of claim 5, The counting unit starts counting when the signal output from the first inverting unit is "0", and outputs a carry output signal "1" to the second inverting unit when all N bits are output "1". Interrupt processing unit. The method of claim 5, And the interrupt processing unit recognizes an interrupt when the output of the second logic operation unit changes from "0" to "1".