KR20010037712A - An apparatus for simultaneous displaying two sd type images on screen by using an hd type video decoder - Google Patents

Abstract

PURPOSE: A two screen display device of an SD grade video using an HD grade video decoder is provided to simultaneously decode two SD grade bit streams using a video decoder which is used in a digital TV of an ATSC standard. CONSTITUTION: A sequence header is transferred by greater than a picture data level of an MPEG-2 video stream. The first and second register sets(107,108) store parameters of each bit stream which have a sequence extension, an extension and user data, and a picture header. A bit stream controller(109) selects one of two SD grade bit streams, and selects and outputs parameters stored in the first and second register sets(107,108) suited to the selected bit stream. The bit stream controller(109) includes a multiplexor. An MPEG-2 video decoder outputs the encoded bit stream and parameters from the bit stream controller(109) as two decoded videos formed by a variable length coding, a reverse quantization, a reverse discrete cosine conversion and a motion compensation.

Description

A two-screen display device of SD class video using HD video decoder {AN APPARATUS FOR SIMULTANEOUS DISPLAYING TWO SD TYPE IMAGES ON SCREEN BY USING AN HD TYPE VIDEO DECODER}

The present invention relates to a two-screen display device of the SD image using an HD video decoder that can simultaneously decode two SD video streams with a video decoder that meets the ATSC standard of the US Digital TV. The present invention relates to a two-screen display device of SD-grade video using an HD-class video decoder to decode two video streams simultaneously, thereby extending the application range of a digital TV.

Digital TV, currently being broadcast in the United States, follows the ATSC standard, which broadcasts video streams with screen sizes up to 1920 x 1080 pixels.

Then, the configuration and operation of the decoder that can show the video of the largest screen by the ATSC standard is as follows.

1 is a block diagram of a conventional MPEG-2 video decoder. As shown in FIG. 1, a variable length encoder 11 represented by a length code according to a frequency of occurrence of a code included in an input encoded bit stream, An inverse scan unit 12 for scanning the output of the variable length encoder 11 in reverse and outputting the inverse quantizer 13 for inversely quantizing the output of the inverse scan unit 12, and the inverse quantizer ( 13) an inverse discrete cosine transform unit 14 for performing inverse discrete cosine transform to restore the original image, a frame storage unit 16 for storing the input image in units of frames, and the inverse discrete cosine transform. The motion compensation unit 15 estimates the degree of motion from the image reconstructed by the unit 14 and moves the signal of the previous frame stored in the frame storage unit 16 by a motion vector and outputs the motion vector.

Referring to the prior art configured as described above is as follows.

When the encoded bit stream is output from an encoder (not shown), the variable length encoder 11 receives the encoded bit stream, and the frequency of occurrence of the code included in the bit stream is short, and the frequency is short. The output is indicated by the sign of long length.

When the variable length encoder 11 displays and outputs the sign of the length, the inverse scan unit 12 scans the output in reverse and transfers the output to the inverse quantizer 13.

Accordingly, the inverse quantizer 13 inverse quantizes the output of the inverse scan unit 12, performs inverse discrete cosine transform on the inverse discrete cosine transform unit 14, and restores the original image to the motion compensation unit 15. Output

The motion compensator 15 estimates the degree of motion from the reconstructed image, reads out the image signal of the previous frame stored in the frame storage unit 16, and outputs the encoded image obtained by moving by the motion vector.

The MPEG-2 video decoder operating as described above decodes the input bit stream of HD level, and is broadcasted to the receiver with a screen size of 1920 × 1080 pixels as shown in FIG. 2.

And, as shown in Figure 3, when the SD-class bit stream is input to the receiver in a screen size of 720 × 480 pixels.

However, in the prior art as described above, even when decoding an SD class bit stream even with a decoder and a memory capable of decoding HD class video, hardware can be decoded as it is. There is a problem that does not increase the efficiency of.

Accordingly, an object of the present invention to solve the above-mentioned conventional problems is to enable simultaneous decoding of two SD class bit streams using a video decoder used in a digital TV that complies with the ATSC standard currently being broadcast in the United States. It is to provide a two-screen display device of the SD image using an HD video decoder.

Another object of the present invention is to provide a two-screen display device of an SD video using an HD video decoder to decode two bit streams using a single video decoder to increase the efficiency of hardware.

1 is a block diagram of a conventional MPEG-2 video decoder.

FIG. 2 is an explanatory diagram illustrating a process of decoding and displaying an HD-level bit stream on a screen in FIG. 1; FIG.

FIG. 3 is an explanatory diagram illustrating a process of decoding and displaying an SD class bit stream on a screen in FIG. 1; FIG.

Figure 4 is a block diagram of a two-screen display device of the SD image using the HD video decoder of the present invention.

5 is a high level bit stream configuration diagram of an MPEG-2 video stream.

6 is a configuration diagram of a bit stream controller in FIG. 4;

7 is a B-picture memory map when decoding an HD video stream.

8 is a B-picture memory map when decoding an SD class 2 video stream.

9 is a flowchart of a decoding frame and a display frame in the case of decoding one HD video stream.

10 is a flowchart of a decoding frame and a display frame in the case of decoding two SD video streams.

FIG. 11 is an explanatory diagram showing a screen in which two videos are decoded simultaneously by the display frame of FIG. 10; FIG.

***** Explanation of symbols for the main parts of the drawing *****

101: variable length encoder 102: inverse scan unit

103: inverse quantizer 104: inverse discrete cosine transform unit

105: motion compensation unit 106: frame storage unit

107,108: register set 109: bit stream controller

In order to achieve the above object, the present invention stores the parameters of each bit stream, such as sequence header, sequence extension, extension and user data, picture header, and the like, carried by the portion of the picture data level of the MPEG-2 video stream. Variable length encoding of the register sets 1 and 2, the two SD class bit streams and the bit stream controllers which mux and output the register sets 1 and 2, and the encoded encoded bit streams transmitted through the bit stream controllers. And an MPEG-2 video decoder for outputting two decoded images made through inverse quantization, inverse discrete cosine transform, and motion compensation.

Hereinafter, with reference to the accompanying drawings in detail as follows.

FIG. 4 is a block diagram of an apparatus for displaying a two-screen SD video using an HD video decoder according to the present invention. As shown in FIG. 4, a sequence header transmitted by a part of a picture data level or higher of an MPEG-2 video stream is shown in FIG. sequence headers, sequence extensions, extensions and user data, groups of picture headers, picture headers, picture header extensions, and the like. Register sets 1, 2 (107) 108, which store the parameters of each bit stream, two SD class bit streams, and register sets 1, 2 (107) 108, which are muxed by one picture of each bit stream. A bit length controller 109 outputs a table as a length code based on a frequency of occurrence of a sign included in a muxed encoded bit stream transmitted through the bit stream controller 109. A variable length encoder 101, an inverse scan unit 102 that scans and outputs the output of the variable length encoder 101 in reverse, and an inverse quantizer that inverse quantizes the output of the inverse scan unit 102. (103), an inverse discrete cosine transforming unit (104) for performing an inverse discrete cosine transform on the output of the inverse quantizer (103) to restore an original image, and a frame storing unit storing the input image in units of frames. And a motion for estimating the degree of motion from the image reconstructed through the inverse discrete cosine transform unit 104 and shifting and outputting a signal of a previous frame stored in the frame storage unit 106 by a motion vector. Compensation section 105 is configured.

In the variable length encoder 101, the frame storage unit 106 is an MPEG-2 video decoder.

Referring to the operation and effect of the present invention configured as described in detail as follows.

The high-level bitstream configuration of the MPEG-2 video stream is divided into a sequence header, a sequence extension, an extension and user data, and a group of picture headers as shown in FIG. It has parameters such as a picture header, a picture header, a picture header extension, and the like.

These parameters are parameters of a higher level of picture data and have parameters to be applied to several pictures such as a sequence or a picture group.

In addition, since the parameters are not included in every picture data, they are stored in two register sets 1, 2 (107) and 108 shown in FIG. 4, and are decoded again when decoding corresponding picture data. It should be used after setting.

In FIG. 4, when two SD class bit streams (Coded bit stream 1 and Coded bit stream 2) are input, the bit stream controller 109 first selects one picture data from one SD class bit stream. After reading the corresponding parameters from register set 1 (107) according to this bit stream and transmitting them to the variable length encoder 101 of the MPEG-2 video decoder, one picture data from another SD class bit stream is transferred. The selected parameters are read from register set 2 (108) stored in accordance with the bit stream and transmitted to the variable length encoder (101).

The bit stream controller 109 that selects the bit stream and the parameters as described above uses the multiplexer MUX as shown in FIG. 6.

When the bit stream controller 109 alternately selects two SD class bit streams and transmits the parameters to the variable length encoder 101 with the parameters corresponding to the selected bit stream, the variable length encoder 101 is transferred. The bit stream is encoded in length and output to the inverse scan unit 102.

Accordingly, the bit stream scanned inversely by the inverse scanning unit 102 is inversely quantized by the inverse quantizer 103 and reconstructed into an original image through inverse discrete cosine transform through the inverse discrete cosine transform unit 104. The compensator 105 compensates for the motion and outputs the final image. As two bit streams are input through the bit stream controller 109, two decoded images are simultaneously output as shown in FIG. 11. .

7 is a B-picture memory map when decoding an HD-level bit stream, in which I, P-pictures are used as reference pictures for decoding B-pictures, and B-pictures are used again after being displayed. Since it is not used to store the next B-picture.

FIG. 8 is a B-picture memory map in the case of decoding two SD class bitstreams, and the number of pixels of an HD class picture is 1920 × 1080 pixels, that is, 2073600 pixels, based on a luminance pixel.

The number of chrominance pixels varies depending on the chroma format, but is proportional to the number of luminance pixels. Therefore, the number of chrominance pixels is considered based on the number of luminance pixels only.

The memory required to store an HD-quality picture is 1920 × 1080, or 2073600 bytes. This is six times 720 × 480 and 345600 bytes of an SD picture.

Therefore, the I, P picture used as a reference will contain two SD pictures in the space of each I, P picture of the HD picture, and each SD will be required by the following decoding and display sequence in the case of the B-picture. A total of four B-pictures 2 of the class bitstream enter the memory as shown in FIG.

In the case of B-pictures, two pictures are stored in memory for each bitstream, and double buffering is performed to alternately read and write two areas.

Therefore, the frame storage unit 106 in the MPEG-2 video decoder is sufficient to store pictures for two SD class bitstreams.

Next, a process of decoding one HD class decoded frame and a process of decoding two SD class decoded frames by the bit stream controller 109 will be described with reference to FIGS. 9 and 10.

FIG. 9 illustrates the decoding of one HD video stream by using the MPEG-2 video decoder shown in FIG. 4, as shown in (a) of I1, P1, B1, B2, P2, B3, B4, I2, and P3. When the display frame is to be displayed with respect to a decoding frame such as B5, the display frame is decoded and displayed in the order of I1, B1, B2, P1, B3, B3, P2, I2, and B5 as shown in (b).

However, when two SD class bitstreams are decoded using the same video decoder used in FIG. 9, the decoding frames as shown in FIG. 10A are decoded in the same display frame order as in FIG. Is displayed as in.

Even though two bitstreams are decoded, the display is simultaneously displayed on one screen as shown in FIG. 11, so that two pictures decoded in each bitstream are displayed within 1/60 second.

Decoding also allows decoding one picture of each bitstream in 1 / 60th of a second.

The speed of the decoder is sufficient because the size of the HD class picture is 6 times the size of the SD class picture, so the bit stream controller 109 selects two SD class bit streams using a multiplexer and fits the selected bitstream. Register set 1 (107) and register set 2 (108) are selected and output.

As described in detail above, the present invention is capable of simultaneously decoding and displaying two SD video streams by applying a small amount of additional circuits using an HD digital video decoder, thereby extending the application range of the digital TV. have.

Claims (2)

Register sets 1 and 2 that store parameters of each bit stream, such as sequence header, sequence extension, extension and user data, and picture header, which are transmitted by the portion of the picture data level or higher of the MPEG-2 video stream, and two SD class. A bit stream controller that selects one of the bit streams and selects and outputs a parameter stored in the register set 1 or the register set 2 according to the selected bit stream, and an encoded bit stream and a parameter transmitted through the bit stream controller. 2-screen display of an SD video using an HD video decoder, comprising an MPEG-2 video decoder that outputs two decoded images through variable length coding, inverse quantization, inverse discrete cosine transform, and motion compensation. Device. The apparatus as claimed in claim 1, wherein the bit stream controller is multiplexed.