KR20010036202A - Memory module for protecting voltage noise - Google Patents

Abstract

PURPOSE: A memory module for suppressing power noise is provided which has memory devices that operate with different phases but have the same output data phase to disperse a point of time at which high power is consumed, thereby reducing momentary consumption power. CONSTITUTION: A memory module has a plurality of memory devices(A,B). The memory devices operate with different phases and output data at the same clock phase in response to an instruction word, address and data input signal. The memory devices include at least input latch circuit(12) to operate at clock phases different from each other. Both of the memory devices have output latch circuits(16,22) to output data at the same clock phase.

Description

Memory module for protecting power noise

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a memory module for preventing power noise, which can reduce the maximum power consumption of a memory by distributing instantaneous power consumption in a module equipped with a plurality of high speed and highly integrated semiconductor memory devices.

In general, a module refers to a set of devices or a set of programs having a single function, and is a function that is embedded in an advanced electronic device having various processing functions such as a computer to process various language processes. Say.

In addition, a memory module is a package device such as various semiconductor devices mounted on a printed circuit board (PCB) and connected to a panel or the like by a plurality of connection pins.

On the other hand, since the memory devices in the memory module perform data processing at the same time, the power consumption supplied to the memory module during the memory operation increases. On the contrary, when the memory is not operated, the power consumption supplied to the memory module is reduced.

Therefore, memory modules equipped with high-speed (more than 100MHz) and highly integrated (64Mbit or more) memory devices may have different amounts of power supplied to each memory device due to unstable power usage. There was a problem of power noise, such as a malfunction caused by not supplying, or supplying too much power, causing distortion in the data signal at the output terminal.

An object of the present invention is to solve the problems of the prior art as described above by mounting a memory device having the same output data phase while operating at different phase differences in the module to distribute the instantaneous power consumption by dispersing the instant of high power consumption in the module The present invention provides a memory module for preventing power noise.

1 is a diagram illustrating a memory module in which a plurality of memory devices operating in different phase shifts are alternately mounted according to an embodiment of the present invention;

FIG. 2 is a detailed internal circuit block diagram of the two memory devices shown in FIG. 1.

* Description of the symbols for the main parts of the drawings *

1: memory module

10: input line

12: input latch circuit

14,20: memory circuit

16, 22: output latch circuit

18, 24: output line

A, B: Memory device having different phase difference

In order to achieve the above object, the present invention provides a memory module equipped with a plurality of memory devices, each of which operates in different phases and outputs data in the same clock phase in response to input signals of instructions, addresses, and data in the memory module. It characterized in that a plurality of memory devices are mounted.

The memory device of the present invention outputs data in the same phase, but operates with different phase differences, thereby distributing power consumption consumed during memory operation in the memory module, thereby greatly reducing instantaneous power consumption.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a memory module in which two memory devices operating with different phase shifts are alternately mounted in accordance with one embodiment of the present invention.

In the embodiment of the present invention, as shown in FIG. 1, two memory devices A and B having different operating phases are mounted in one memory module 1. Here, memory 1 (A) and memory 2 (B) output data in the same clock phase in response to input signals of the same command, address, and data, but memory operations are performed at different phases.

FIG. 2 is a detailed internal circuit block diagram of the two memory devices shown in FIG. 1.

Referring to FIG. 2, memory 1 (A) receives a command, an address, and data, and outputs data in synchronization with memory 2 (B). However, memory 1 (A) has an input latch circuit 12 that delays a signal applied from the input line 10 by a predetermined time so as to have a different clock phase difference with respect to memory 2 (B). Further, the memory 1 (A) further includes an output latch circuit 16 to synchronize with the other memory 2 (B) when outputting data of the memory circuit portion 14 to the output line 18.

In addition, the memory 2 (B) receives commands, addresses and data in synchronization with the memory 1 (A) and outputs data, but is applied from the input line 10 to have a different clock phase difference with respect to the memory 1 (A). The supplied signal is supplied to the memory circuit unit 20 as it is. The memory 2 (B) has an output latch circuit 22 to synchronize with the other memory 1 (A) when data is output from the memory circuit section 20 to the output line 24.

In the embodiment of the present invention, the operations of the memory 1 (A) and the memory 2 (B) are as follows.

When the memory circuit unit 14 or 20 operates other than reading data, the memory 2 (B) receives an input signal such as command / address / input data and the like at the same time as the memory 1 (A), and receives the memory 1 through the input latch circuit 12. The memory circuit unit 14 performs the corresponding operation by leading one cycle from (A). If data is input to the memory 1 (A), a cycle is stored using the input latch circuit 12 and then transferred to the memory circuit unit 14 in the same phase as the instruction address. However, the memory 2 (B) receives the command / address / input data into the memory circuit unit 20 without time delay. After one cycle has elapsed, the operation of the memory 2 (A) is completed, and the operation of the memory circuit unit 20 of the memory 1 (B) starts. As a result, the memory circuit portion 14 of the memory 1 (A) operates with a phase difference of one cycle from the memory circuit portion 20 of the memory 2 (B), thereby separating the power usage moment.

In the data read operation of the memory circuits 14 and 20, the memory 2 (B) receives an input signal such as command / address / input data simultaneously with the memory 1 (A). However, the memory 1 (A) is delayed by one cycle than the memory 2 (B) through the input latch circuit 12 so that the memory circuit 14 performs a data read operation. Then, the memory circuit unit 20 of the memory 2 (B) performs a data read operation for one cycle. After this cycle has elapsed, the data read operation of the memory 2 (B) is completed and the data read to the output latch circuit 22 is completed. Is stored. After the next cycle has elapsed, when the data read operation of memory 1 (A) is completed and the data read operation of memory 1 (A) is completed, the corresponding output data is stored in the output latch circuit 22 of memory 2 (B). It is output to each output line 18 (24) synchronously.

In other words, during the data read operation, the output data phase of the memory 1 (A) is delayed by one cycle compared to the memory 2 (B), so that the data can be cycled by using the output latch circuit 22 of the memory 2 (B). To save. In the next cycle, memory 1 (A) outputs data in synchronization with memory 2 (B).

Therefore, the present invention reduces the overall instantaneous power consumption by mounting a memory that operates with different phase differences in a memory module and operating the memory device with a predetermined phase difference.

As described above, according to the present invention, the instantaneous power consumption is reduced to 50% or less by a module having a different memory operation phase compared to a memory module operating in the same phase of the related art, thereby greatly reducing power noise. Accordingly, the present invention has the advantage of preventing the degradation of the yield and reliability of the high-speed and high-density memory due to power noise of the memory module.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (3)

In a memory module equipped with a plurality of memory devices, And a plurality of memory devices operating in different phases and outputting data in the same clock phase in response to input signals of commands, addresses and data in the memory module. 2. The memory module of claim 1, wherein the memory device includes at least an input latch circuit to operate in a different clock phase with respect to a neighboring memory device. 2. The memory module of claim 1, wherein the memory device includes an output latch circuit to output data at the same clock phase to neighboring memory devices.