KR20010036045A - Method for Thermal treatment of TiAlN layer - Google Patents
Method for Thermal treatment of TiAlN layer Download PDFInfo
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- KR20010036045A KR20010036045A KR1019990042881A KR19990042881A KR20010036045A KR 20010036045 A KR20010036045 A KR 20010036045A KR 1019990042881 A KR1019990042881 A KR 1019990042881A KR 19990042881 A KR19990042881 A KR 19990042881A KR 20010036045 A KR20010036045 A KR 20010036045A
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- 229910010037 TiAlN Inorganic materials 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000007669 thermal treatment Methods 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims abstract description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000011261 inert gas Substances 0.000 claims abstract description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 13
- 238000005121 nitriding Methods 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000011010 flushing procedure Methods 0.000 claims description 6
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 8
- 238000013508 migration Methods 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 금속/유전층/금속(MIM) 구조의 커패시터에서 TiAlN을 전극으로 사용할 경우의 열처리방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a heat treatment method when TiAlN is used as an electrode in a capacitor having a metal / dielectric layer / metal (MIM) structure.
최근 금속/유전층/금속(MIM) 구조의 커패시터에서 전극으로 TiAlN을 사용할 경우, 화학적 원자층 증착공정으로 이를 제조한다. 통상, TiAlN막의 하지막이 실리콘(Si)일 경우, 1200Å 두께의 TiAlN막에 가해지는 장력 스트레스(Tensile stress)는 약 2.0E10 dyne/㎠ 정도이다. 이러한 장력 스트레스는 두께에 따라 변화는 있지만, 이것은 일반적인 장벽층(diffusion barrier layer)으로 사용되는 화학기상증착(CVD: Chemical Vapor Deposition)에 의한 질화티타늄(TiN)막과 비슷한 장력 스트레스이다.Recently, when TiAlN is used as an electrode in a capacitor having a metal / dielectric layer / metal (MIM) structure, it is manufactured by a chemical atomic layer deposition process. Usually, when the base film of the TiAlN film is silicon (Si), the tensile stress applied to the TiAlN film having a thickness of 1200 GPa is about 2.0E10 dyne / cm 2. Although the tensile stress varies with thickness, it is a tensile stress similar to a titanium nitride (TiN) film by chemical vapor deposition (CVD) used as a general diffusion barrier layer.
이렇게 막질 내에서 장력 스트레스가 높아지면 여러 가지 결함(defects)이 발생하는데, 이러한 결함의 발생은 디자인 룰(design rule)이 작은 서브-미크론(Sub-micron) 소자일수록 더욱 심각한 실정이다. 대표적인 결함중의 하나로 메탈층(conductive metal layer)이 움직여 반도체 소자내의 전류의 흐름이 단선(short)되거나, 끊어지거나(open) 혹은 누설전류 등을 야기하는 일렉트로-마이그레이션(Electro-migration)을 들 수 있다. 이러한 일렉트로-마이그레이션 결함은 TiAlN막을 두껍게 증착한 경우에 주로 발생할 수 있는데, 특히 금속/유전층/금속(MIM) 구조의 커패시터 구조에서 TiAlN막을 매몰 콘택(Buried Contact)의 플러그(plug)로 사용할 때 TiAlN막을 두껍게 증착해야 한다. 이렇게 TiAlN막을 두껍게 증착하면 일렉트로-마이그레이션(Electro-migration) 문제뿐만 아니라 리프팅(lifting) 문제까지 발생하여 심각한 공정상의 결함이 야기될 수 있다.As the tensile stress increases in the film, various defects occur. The occurrence of such defects is more serious in a sub-micron device having a small design rule. One of the typical defects is electro-migration, in which a conductive metal layer moves, causing a current to flow in the semiconductor device to be short, open, or leaking. have. This electro-migration defect can occur mainly when the TiAlN film is deposited thickly, especially when the TiAlN film is used as a plug of buried contact in the capacitor structure of the metal / dielectric layer / metal (MIM) structure. It must be deposited thickly. This thick deposition of TiAlN film may cause not only electro-migration problems but also lifting problems, which may cause serious process defects.
따라서, TiAlN을 금속/유전층/금속(MIM) 구조의 커패시터의 전극을 사용할 경우에는, 반도체 소자의 신뢰성을 높이기 위하여 막질 내부에서 발생하는 장력 스트레스(Tensile Stress)를 줄일 필요가 있다.Therefore, when TiAlN uses electrodes of a capacitor having a metal / dielectric layer / metal (MIM) structure, it is necessary to reduce the tensile stress generated inside the film to increase the reliability of the semiconductor device.
본 발명이 이루고자 하는 기술적 과제는 TiAlN막을 금속/유전층/금속(MIM) 구조의 커패시터 전극으로 사용할 경우에 막질 내부의 장력 스트레스를 줄일 수 있는 TiAlN막의 열처리방법을 제공하는데 있다.An object of the present invention is to provide a heat treatment method of a TiAlN film that can reduce the tensile stress inside the film quality when the TiAlN film is used as a capacitor electrode of a metal / dielectric layer / metal (MIM) structure.
도 1은 본 발명에 의한 TiAlN막의 열처리방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view for explaining the heat treatment method of the TiAlN film according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100: 반도체 기판, 102: 절연막,100: semiconductor substrate, 102: insulating film,
104: 하부전극용 TiAlN막.104: TiAlN film for lower electrode.
상기 기술적 과제를 달성하기 위하여 본 발명은, 하부구조가 형성된 반도체 기판에 절연막을 증착하는 공정과, 상기 절연막에 콘택홀을 형성하는 공정과, 상기 콘택홀이 형성된 결과물 상에 금속/유전층/금속(MIM) 구조의 커패시터 전극용 TiAlN막을 화학적 원자층 증착법으로 형성하는 공정과, 상기 TiAlN막에 대한 장력 스트레스(Tensile Stress)를 줄이기 위하여 질소, 산소 및 불활성기체중에 어느 하나를 포함하는 분위기에서 급속질화처리(RTN)를 수행하는 공정을 구비하는 것을 특징으로 하는 TiAlN막의 열처리방법을 제공한다.In order to achieve the above technical problem, the present invention provides a process for depositing an insulating film on a semiconductor substrate having a lower structure, forming a contact hole in the insulating film, and forming a metal / dielectric layer / metal on a resultant in which the contact hole is formed. A process of forming a TiAlN film for a capacitor electrode having a MIM structure by chemical atomic layer deposition, and rapid nitriding treatment in an atmosphere containing any one of nitrogen, oxygen, and an inert gas in order to reduce tensile stress on the TiAlN film. Provided is a heat treatment method for a TiAlN film, comprising the step of performing RTN.
본 발명의 바람직한 실시예에 의하면, 상기 TiAlN막을 형성할 때 암모니아(NH3) 가스를 흘러주는 공정(flushing process)을 1회 이상 하는 것이 적합하며, 상기 TiAlN막의 증착 전후에 암모니아(NH3) 가스를 흘러주는 공정(flushing process)을 더 진행하는 것이 적합하다.According to a preferred aspect of the present invention, when forming the TiAlN film is ammonia (NH 3) appropriate to the process (flushing process) to flow the gas at least once and ammonia to the TiAlN film is deposited before or after (NH 3) gas It is appropriate to proceed further with the flushing process.
본 발명에서의 TiAlN막에 대한 장력 스트레스 감소를 위한 열처리 방법은 금속/유전층/금속(MIM) 구조의 커패시터에 한정되어 설명하였지만, 이는 메탈콘택용으로 사용되는 TiAlN막에도 적용이 가능하며, 반도체 소자의 모든 제조공정에서 사용되는 TiAlN막에 대한 장력 스트레스 완화를 위하여 적용할 수 있음은 물론이다.Although the heat treatment method for reducing the tensile stress on the TiAlN film in the present invention has been described as being limited to a capacitor having a metal / dielectric layer / metal (MIM) structure, it is applicable to a TiAlN film used for a metal contact, and a semiconductor device. Of course, it can be applied to alleviate the tensile stress on the TiAlN film used in all manufacturing processes.
일반적으로 DRAM(Dynamic Random Access Memory)의 제조공정에서 급속질화처리(RTN)와 같은 열처리(annealing)가 이루어지는 목적은, 장벽층(diffusion barrier layer)에 대한 장벽효과를 증대시키거나, 금속/유전층/금속(MIM) 구조의 커패시터 구조나, 금속/유전층/실리콘(MIS) 구조의 커패시터에서 유전층의 특성을 개선하기 위하여 금속과 실리콘층의 계면에서 산화가 발생하여 산화층을 형성함으로써 커패시턴스 특성이 저하되는 것을 방지하기 위해 수행된다. 그러나 본 발명의 특징은 TiAlN막에 대한 장력 스트레스를 완화시키기 위해 급속질화처리(RTN)가 수행되는 특징을 가진다.In general, the purpose of annealing such as rapid nitridation (RTN) in the manufacturing process of Dynamic Random Access Memory (DRAM) is to increase the barrier effect on the diffusion barrier layer, or to increase the metal / dielectric layer / In order to improve the characteristics of the dielectric layer in the capacitor structure of the metal (MIM) structure or the capacitor of the metal / dielectric layer / silicon (MIS) structure, oxidation occurs at the interface between the metal and the silicon layer to form an oxide layer. Is done to prevent. However, a feature of the present invention is that rapid nitriding (RTN) is performed to alleviate the tensile stress on the TiAlN film.
그러므로 본발명에 따르면, 금속/유전층/금속(MIM) 구조의 커패시터에서 TiAlN막을 전극으로 사용할 경우에 막질 내부에 장력 스트레스를 제거하여 일렉트로 마이그레이션( electro-migration)이나 리프팅(lifting) 결함의 발생을 억제할 수 있다.Therefore, according to the present invention, when a TiAlN film is used as an electrode in a capacitor of a metal / dielectric layer / metal (MIM) structure, tension stress is removed from inside the film to suppress the occurrence of electro-migration or lifting defects. can do.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1을 참조하면, 반도체 기판(100)에 하부구조, 예컨대 트랜지스터나 비트 라인(bit line)과 같은 구조(미도시)를 형성하고, 평탄화를 위한 절연막(102)을 형성한다. 이어서, 사진 및 식각공정을 진행하여 하지막을 노출시키는 콘택홀을 형성한다. 그 후, 커패시터의 하부전극층인 TiAlN막(104)을 화학적 원자층 증착방법으로 두껍게 증착한다.Referring to FIG. 1, a structure (not shown) such as a substructure, for example, a transistor or a bit line, is formed on a semiconductor substrate 100, and an insulating film 102 for planarization is formed. Subsequently, a photo hole and an etching process are performed to form a contact hole exposing the underlying film. Thereafter, the TiAlN film 104, which is the lower electrode layer of the capacitor, is deposited thickly by chemical atomic layer deposition.
여기서, 화학적 원자층 증착방법으로 형성된 TiAlN막질 내에 존재할 수 있는 성분은 일반적으로 TiN, AlN, Ti, Al, Si등이 있다. TiAlN막(104)의 하지막이 실리콘층 일때, 상기 TiAlN막(104) 내에 존재하는 개개에 대한 열팽창계수를 살펴보면 아래와 같다.Here, components that may be present in the TiAlN film formed by the chemical atomic layer deposition method generally include TiN, AlN, Ti, Al, Si, and the like. When the underlying film of the TiAlN film 104 is a silicon layer, the coefficient of thermal expansion for each of the TiAlN films 104 is as follows.
표 1에 나타난 열팽창계수를 살펴보면, TiAlN막 내에서 장력 스트레스를 올릴 수 있는 것은 Al 성분이고, 장력 스트레스를 줄일 수 있는 것은 AlN으로 생각할 수 있다. 그러므로, TiAlN막을 질소를 포함하는 분위기에서 열처리를 수행하면 막질 내에서 표면의 조성과 결합상태를 바꿀 수 있기 때문에 장력 스트레스를 줄일 수 있다는 것을 알 수 있다.Looking at the coefficient of thermal expansion shown in Table 1, it can be thought that it is Al component that can raise the tensile stress in the TiAlN film, and that AlN can reduce the tensile stress. Therefore, it can be seen that when the TiAlN film is heat-treated in an atmosphere containing nitrogen, the tensile stress can be reduced because the composition and bonding state of the surface can be changed in the film quality.
따라서, TiAlN막을 화학적 원자층 증착방법으로 형성할 때, 그 형성전 또는 형성후에 질소를 포함하는 가스인 암모니아 가스(NH3)를 흘려주는 공정(Flushing)을 추가하거나, TiAlN막을 형성하는 중간에 적어도 1회 이상 질소를 포함하는 가스인 암모니아 가스(NH3)를 흘려주는 공정(Flushing)을 추가할 수 있다.Therefore, when the TiAlN film is formed by a chemical atomic layer deposition method, a process of flowing ammonia gas (NH 3 ), which is a gas containing nitrogen, before or after the formation thereof is added, or at least in the middle of forming the TiAlN film. Flushing may be added to flow ammonia gas (NH 3 ), which is a gas containing nitrogen one or more times.
일 예로 질소를 포함하는 가스인 암모니아 가스(NH3)를 흘려주는 공정(Flushing)을 막질의 두께가 10∼500Å의 간격마다 진행할 수 있다. 따라서, TiAlN막의 두께가 두꺼운 경우에도 장력 스트레스를 충분히 낮추는 효과를 기대할 수 있다. 이렇게 TiAlN막을 화학적 원자층 증착방법으로 형성할 때 암모니아 가스를 흘려주는 것은 후속공정에서 진행되는 급속질화처리(RTN)와 동일한 효과를 나타내기 때문이며, 상기 급속질화처리(RTN)의 효과에 대해서는 후속공정에서 다시 설명한다.For example, a flushing process of flowing ammonia gas (NH 3 ), which is a gas containing nitrogen, may be performed at intervals of 10 to 500 kPa. Therefore, even when the thickness of the TiAlN film is thick, the effect of sufficiently lowering the tensile stress can be expected. The ammonia gas flowing when the TiAlN film is formed by the chemical atomic layer deposition method has the same effect as the rapid nitriding treatment (RTN) performed in the subsequent process, and the subsequent process for the rapid nitriding treatment (RTN) effect. Will be explained again.
상기 하부전극용 TiAlN막(104)이 형성된 결과물에 장력 스트레스를 줄이기 위한 급속질화처리(RTN: Rapid Thermal Nitridation)를 진행한다. 이러한 급속질화처리는 산소, 질소, 불활성기체중에서 선택된 어느 하나를 포함하는 분위기에서 수행할 수 있다. 산소인 경우에는 O2, O3, N2O가스를 사용하고, 질소인 경우에는 N2, NH3가스를 이용하는 것이 바람직하다.Rapid thermal nitriding (RTN) is performed to reduce the tensile stress on the resultant formed TiAlN film 104 for the lower electrode. Such rapid nitriding may be performed in an atmosphere containing any one selected from oxygen, nitrogen, and inert gas. If the oxygen is O 2, O 3, using the N 2 O gas, it is preferable that if the nitrogen, the use of N 2, NH 3 gas.
본 발명에서는 일 예로 TiAlN막(104)을 120, 240Å의 두께로 각각 형성하고, 챔버의 온도를 850℃로 조절하고, 암모니아 가스(NH3)의 분위기에서 5분간 급속질화처리를 수행하였다. 그 후, 열처리를 수행한 TiAlN 막질과 수행하지 않은 TiAlN 막질에 대한 장력 스트레스를 각각 측정하여 그 결과를 아래에 수록하였다.In the present invention, for example, the TiAlN film 104 was formed to a thickness of 120 and 240 kPa, respectively, and the temperature of the chamber was adjusted to 850 ° C., and rapid nitriding was performed for 5 minutes in an atmosphere of ammonia gas (NH 3 ). After that, the tensile stress for the TiAlN film and the TiAlN film not subjected to the heat treatment were measured, respectively, and the results are listed below.
상기 표에서 알 수 있듯이 본 발명과 같이 하부전극용 TiAlN막(104)에 대하여 급속질화처리를 수행한 경우가, 수행하지 않은 경우보다 장력 스트레스에 대한 특성면에서 크게 개선된 것을 확인 할 수 있다. 이러한 효과는 상기 표 2에서도 알 수 있듯이 TiAlN막질의 두께가 얇을수록 크게 나타난다. 본 발명에서는 금속/유전층/금속(MIM) 구조의 커패시터에 한정하여 TiAlN막의 열처리 방법을 설명하였지만, 이를 금속접촉(Metal Contact)에 장벽층으로 사용되는 TiAlN막에 적용할 경우에는 장벽강화 효과를 얻을 수 있을 뿐만 아니라, Al/Si 접촉, 또는 Cu/Si 접촉계면에서 확산방지 효과도 얻을 수 있다.As can be seen from the above table, it can be seen that the rapid nitriding treatment on the TiAlN film 104 for the lower electrode as in the present invention is significantly improved in terms of the properties of the tensile stress than the case where the nitriding treatment is not performed. As can be seen from Table 2, this effect is larger as the thickness of the TiAlN film is thinner. In the present invention, the heat treatment method of the TiAlN film is limited to a capacitor having a metal / dielectric layer / metal (MIM) structure. However, when this is applied to a TiAlN film used as a barrier layer for metal contact, a barrier strengthening effect is obtained. In addition, the anti-diffusion effect can be obtained at Al / Si contact or Cu / Si contact interface.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 상술한 본 발명에 따르면, 첫째, TiAlN막을 급속질화처리(RTN)하여 TiAlN막에 대한 장력 스트레스(Tensile Stress) 특성을 개선함으로써 일렉트로-마이그레이션(Electro-migration)과 같은 소자 결함을 억제할 수 있다. 둘째, TiAlN막의 급속질화처리시(RTN)에 TiAlN막의 표면이 질화처리되어 유전체막으로부터 유입되는 산소의 확산(oxygen diffusion)을 막아줌으로써, 금속/유전층/금속(MIM) 구조의 커패시터에서 커패시턴스(Capacitance)의 증가와 누설전류(leakage current) 특성을 개선할 수 있다.Therefore, according to the present invention described above, first, the TiAlN film can be rapidly nitrided (RTN) to improve the tensile stress characteristic of the TiAlN film, thereby suppressing device defects such as electro-migration. have. Second, during the rapid nitriding of the TiAlN film (RTN), the surface of the TiAlN film is nitrided to prevent oxygen diffusion from the dielectric film, thereby allowing capacitance in the capacitor of the metal / dielectric layer / metal (MIM) structure. ) And leakage current characteristics can be improved.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100422565B1 (en) * | 2001-06-12 | 2004-03-12 | 주식회사 하이닉스반도체 | Method of forming a capacitor of a semiconductor device |
| US7416954B2 (en) * | 2002-06-27 | 2008-08-26 | Intel Corporation | Enhanced on-chip decoupling capacitors and method of making same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100422565B1 (en) * | 2001-06-12 | 2004-03-12 | 주식회사 하이닉스반도체 | Method of forming a capacitor of a semiconductor device |
| US7416954B2 (en) * | 2002-06-27 | 2008-08-26 | Intel Corporation | Enhanced on-chip decoupling capacitors and method of making same |
| US7843036B2 (en) | 2002-06-27 | 2010-11-30 | Intel Corporation | Enhanced on-chip decoupling capacitors and method of making same |
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