KR20010028675A - Microcontroller consuming low power having power management block - Google Patents

Abstract

PURPOSE: A microcontroller for minimizing power consumption by being equipped with electric power control block is provided to reduce power consumption of a microcontroller by enabling a user to selectively control speed of a clock and provision of clock to each module. CONSTITUTION: A clock control block(12) generates a normal clock generated from a clock source and a slow clock. The clock control block(12) selects one among the normal clock and the slow clock, and provides the clock as a main clock. An electronic power control block(14) receives the main clock generated from the clock control block(12), and generates a plurality of module clocks provided to each module inside of the microcontroller according to predetermined clock selection information.

Description

Microcontroller consuming low power having power management block

The present invention relates to a general purpose microcontroller, and more particularly to a general purpose microcontroller having a power management block that minimizes power consumption in the microcontroller.

In the device equipped with the microcontroller, the power consumption of the microcontroller which makes the data processing faster by increasing the operation speed for high performance is a large portion of the total power consumption. In particular, the design of low power microcontrollers has become one of the main goals in the design of microcontrollers as the microcontrollers are widely installed in portable devices. Therefore, many efforts are continued to minimize the power consumption of the microcontroller.

Typically, a microcontroller contains a number of hardware modules, including a central processing unit (CPU). Each module operates according to a clock generated from a clock source and input through a clock generator. Therefore, methods for reducing the power consumption of the microcontroller have been developed by adjusting the clock used inside the microcontroller. One of these methods is to control the supply of the clock depending on the operating mode of the microcontroller. That is, when the microcontroller is not operating, all of the clocks supplied to each module are cut off and the microcontroller is in a powerdown state. When the central processing unit (CPU) is stopped from operating, the clock supply to the central processing unit (CPU) is cut off and the microcontroller is in an idle state, thereby reducing power consumption.

However, the power management of the conventional microcontroller has a limitation in minimizing power consumption by not considering the clock supply of each module and the clock speed of each module according to the operation of each module therein.

The technical problem to be achieved by the present invention is to provide a general-purpose microcontroller that can minimize the power consumption.

1 is a block diagram schematically illustrating a power management block according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating the clock control block of FIG. 1 in detail.

FIG. 3 is a diagram illustrating the power control block of FIG. 1 in detail.

The present invention for achieving the above technical problem relates to a general-purpose microcontroller having a power management block for performing power management in the microcontroller. The power management block generates a normal clock phase-locked to a received input clock and a low speed clock slower than the speed of the input clock according to an operation state of the device, and selects one of the normal clock and the low speed clock. A clock control block generated by a clock; And a power control block for selectively controlling the supply of the main clock to respective modules in response to predetermined clock selection information.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, for the convenience of description, signals performing the same role through the drawings are denoted by the same reference numerals.

1 is a diagram illustrating a power management block according to an embodiment of the present invention. Referring to this, the power management block 10 of the present invention includes a clock control block 12 and a power control block 14.

The clock control block 12 generates a normal clock NORM_CLK that is phase-locked to an input clock IN_CLK generated from a clock source (not shown) and a low speed clock SLOW_CLK slower than the speed of the input clock IN_CLK. do. The clock control block 12 selects one of the normal clock NORM_CLK and the low speed clock SLOW_CLK and supplies it as the main clock MAIN_CLK. The power control block 14 receives the main clock MAIN_CLK generated by the clock control block 12 and supplies a plurality of module clocks MODULE_CLK0, MODULE_CLK1, which are supplied to each module in the microcontroller according to predetermined clock selection information. ..., MODULE_CLKN).

Therefore, the clock control block 12 controls the speed of the main clock MAIN_CLK, and the power control block 14 can selectively control the supply of the main clock MAIN_CLK to each module.

The detailed configuration of the clock control block 12 is shown in FIG. Referring to this, the clock control block 12 includes a phase locked loop (PLL) circuit 20, a clock divider 22, a selector 24, a clock register unit 26, and a control logic unit 28. . The PLL circuit 20 generates a normal clock NORM_CLK that is phase locked to the input clock IN_CLK. The clock divider 22 generates a slow clock SLOW_CLK slower than the speed of the input clock IN_CLK according to a predetermined slow count value. The selector 24 selects one of the normal clock NORM_CLK and the low speed clock SLOW_CLK in response to the predetermined clock selection signal SEL to supply the main clock MAIN_CLK.

The clock register unit 26 stores clock control information including a slow count value and a slow bit value, which are control information of the clock divider 22. The slow count value is a value for determining the frequency division rate of the clock divider 22. The clock divider 22 divides the input clock IN_CLK into a low speed clock SLOW_CLK desired by the user according to this value. Here, the slow bit value is a value for determining whether or not a low speed clock is generated.

The control logic unit 28 controls the PLL circuit 20 and the clock divider 22 according to the clock control information and the clock control signal and generates a clock select signal SEL. The clock control signal includes a power down signal POWER_DOWN and a wake up signal WAKE_UP. When the slow bit value of the clock control information is set, the control logic unit 28 stops the operation of the PLL circuit 20 through the PLL control signal PCON and the divider control signal DCON and the clock divider 22. Is driven, and also generates a clock select signal SEL which causes the selector 24 to select the slow clock SLOW_CLK and feed it to the main clock MAIN_CLK. When the control logic unit 28 receives the power down signal POWER_DOWN, the control logic unit 28 generates the PLL control signal PCON and the divider control signal DCON, which stop the operation of the PLL circuit 20 and the clock divider 22. Therefore, the supply of the main clock MAIN_CLK is cut off. When the control logic unit 28 receives the wake-up signal WAKE_UP, a PLL control signal PCON for driving the PLL circuit 20 is generated. At this time, the PLL circuit 20 has an initial time and a stable normal clock is generated. After that, the clock select signal SEL is generated to the selector 24 so that the main clock MAIN_CLK can be sent.

3 is a diagram illustrating the power control block 14 of FIG. 1. Referring to this, the power control block 14 includes a power register unit 32 and a module clock control unit 34. The power register section 32 stores clock selection information used to control the supply of the main clock MAIN_CLK to each module in the microcontroller. The clock selection information includes module clock bits indicating whether a clock is supplied for each module and clock down bits indicating whether a clock supply is blocked for all modules.

The module clock controller 34 generates module clocks MODULE_CLK0,..., MODULE_CLKN that selectively supply the main clock MAIN_CLK according to the clock selection information. That is, the module clock controller 34 controls the supply of the main clock MAIN_CLK to the corresponding module according to the setting value of each module clock bit, and supplies the main clock MAIN_CLK to all modules according to the setting value of the clock down bit. To control. There are a plurality of AND gates in the module clock controller 34. The main clock MAIN_CLK is received through one input terminal of each AND gate, and the enable signal E0 is received through the other input terminal, respectively. , E1, ..., EN) are received. The output terminal generates a module clock (MODULE_CLK0, ..., MODULE_CLKN). Therefore, the enable signals E0, E1, ..., EN enable or disable the main clock MAIN_CLK to generate the corresponding module clocks MODULE_CLK0, MODULE_CLKN. The logic states of the enable signals E0, E1, ..., EN are determined by the module clock bits and the clock down bits of the power register section 32.

When the clock down bit is set, the module clock controller 34 cuts off all main clocks MAIN_CLK supplied to each module and generates a power down signal POWER_DOWN. The power down signal POWER_DOWN is input to the control logic unit 28 of the clock control block 12 to stop the operation of the PLL circuit 20 and the clock divider 28. Therefore, the generation of the main clock MAIN_CLK is eventually stopped.

Of the many modules, the memory controller (not shown), the bus controller (not shown) and the interrupt controller (not shown) are always the main clock (MAIN_CLK) supplied. Therefore, except in the case of power-down, always the main The clock MAIN_CLK is designed to be supplied. In addition, in the state where the supply of the main clock MAIN_CLK to the central processing unit CPU is stopped, i.e., in the idle state, the main clock MAIN_CLK is supplied by interruption.

Accordingly, each module other than the above modules can be appropriately adjusted in software by the user using the microcontroller of the present invention. Therefore, the clock supply to each module inside the microcontroller can be freely controlled.

In other words, a user developing a system using the microcontroller of the present invention, by appropriately selecting each value of the clock control information and each bit of the clock selection information by software, the speed of the main clock and the main clock for each internal module The supply of can be controlled. Therefore, the power consumed by the microcontroller can be greatly reduced.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The general purpose microcontroller of the present invention allows the user to selectively control the speed of the clock and the clock supply to each internal module. Therefore, the power consumption of the microcontroller is greatly reduced.

Claims (3)

A general purpose microcontroller having a power management block, The power management block A clock control block generating a normal clock synchronized with a received input clock and a low speed clock slower than a speed of the input clock, and generating any one selected from the normal clock and the low speed clock as a main clock; And And a power control block for selectively controlling the supply of the main clock to respective modules in response to predetermined clock selection information. The method of claim 1, wherein the clock control block A phase locked loop (PLL) circuit for generating the normal clock that is phase locked to the input clock; A clock divider for generating the slow clock slower than the speed of the input clock according to a predetermined slow count value; A selector for supplying any one selected from the normal clock and the low speed clock as the main clock according to a predetermined clock selection signal; A clock register unit which stores clock control information including the slow count value; And And a control logic unit for generating the clock select signal and the signals for controlling the phase-locked loop (PLL) circuit and the clock divider according to the clock control information and a predetermined clock control signal. . The method of claim 1, wherein the power control block A power register unit for storing the clock selection information; And And a module clock controller configured to selectively provide the main clock to each internal module in response to the clock selection information.