KR20010028468A - Apparatus for encrypting and decrypting data and controlling method thereof - Google Patents

Abstract

PURPOSE: A device for encoding and decoding and a method for controlling thereof are provided to reduce the load of CPU carrying out encoding and decoding by using a gate array and to carry out encoding and decoding closely in real time. CONSTITUTION: A device for encoding and decoding and a method for controlling thereof include a CPU interface portion(11), a decoder(12), a memory portion(30), an in/output buffer(13), an engine portion(40), an interrupt controller(20) and a condition register(14). The CPU interface portion(11) is connected to the CPU. The decoder(12) decodes the key value received through the CPU interface portion(11) and data and outputs it. The memory portion(30) confirms a user by the output of the decoder(12) and outputs the data of the set up code. The in/output buffer(13) sends and receives the data between engine portions(40). The engine portion(40) carries out encoding and decoding according to the data received from the in/output buffer(13) and the code value of the memory portion(30). The interrupt controller(20) detects and outputs the condition of the engine portion. The condition register(14) outputs the condition to the CPU through the CPU interface portion(11).

Description

Encryption and decryption device and its control method {APPARATUS FOR ENCRYPTING AND DECRYPTING DATA AND CONTROLLING METHOD THEREOF}

The present invention relates to an encryption and decryption apparatus and a control method thereof, and more particularly, to a decryption apparatus and a control method of a data encryption standard (DES), which is a standard algorithm for encrypting and decrypting.

In general, encryption and decryption are one technical method used to securely transmit personal information as information communication advances. Such encryption and decryption methods are widely used to protect user's identity user information in electronic commerce and the like, and as user demand for information communication increases, more user information is moved to data communication using a communication network. If you send your company's confidential information or personal information directly in plain text without going through such encryption and decryption, these data will be exposed to the outside, and your personal information will be protected. Therefore, companies that perform most data communications or companies with communication servers with multiple subscribers are required to perform encryption and decryption operations during data communications.

Such encryption and decryption is generally performed in accordance with the standard of the standard (hereinafter referred to as DES) standardized and used in the United States to perform encryption and decryption. According to the DES standard, encryption and decryption are performed in a central processing unit (CPU) of a communication system and are performed by executing a program that satisfies this standard. In addition, since the DES standard is configured to encrypt and decrypt the same algorithm 16 times, there is a problem that it takes a lot of time to perform such a task with a program.

In addition, it takes a lot of time to generate and decrypt a single ciphertext, so even if data is transmitted or received in real time, a lot of processing time is required in the process of encryption and decryption. There is a problem that the processing speed of other tasks performed in the server is very slow when the server to generate and process the cipher text.

Accordingly, an object of the present invention is to provide an apparatus for performing encryption and decryption at a high speed and a control method thereof.

Another object of the present invention is to provide an apparatus for satisfying a DES algorithm and performing encryption and decryption and a control method thereof.

The apparatus of the present invention for achieving the above objects is a device for performing encryption and decryption, the CPU interface unit and the key value and data received through the CPU interface unit A decoder which decodes and outputs a memory, a memory unit which outputs data of a set code by identifying a user by an output of the decoder, an input / output buffer which transmits and receives data between the CPI interface unit and an engine unit which performs an encryption and decryption process; An engine unit that performs encryption and decryption according to data received from the input / output buffer and a code value of the memory unit, an interrupt controller that detects and outputs a state of the engine unit, and the CPI interface unit according to an output of the interrupt controller. Status registers that output status to the central processing unit Characterized by configured.

A method of the present invention for achieving the above objects is a control method of an apparatus for performing encryption and decryption, a fixed extraction process for receiving data and key values to extract only a predetermined bit of data, and extracting the fixed extracted data A process of performing a closed ora operation, a process of reading data by extracting an address of a memory after the exclusive ora operation, and shifting the read data by a predetermined number according to the key value; Storing the data in a predetermined register after the shift, increasing the counter after storing the data, checking whether the increased counter value is a predetermined value, and checking the counter value If the predetermined value is preset, the data is outputted. It characterized by constituted by any process.

1 is a block diagram of an apparatus for performing encryption and decryption according to a preferred embodiment of the present invention;

FIG. 2 is a detailed block diagram showing an example of the decoder 12 shown in FIG.

3 is a detailed block diagram of an input buffer in the structure of the input / output buffer of FIG. 1;

4 is a detailed block diagram of an output buffer in the structure of the input / output buffer of FIG. 1;

FIG. 5 is a block diagram illustrating an initial replacement process of the DES engine of FIG. 1. FIG.

6 is a detailed block diagram of a DES engine;

7 is a control flowchart according to the operation of the encryption and decryption apparatus.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an apparatus for performing encryption and decryption according to a preferred embodiment of the present invention. Hereinafter, a configuration and an operation of an apparatus for performing each encryption and decryption will be described in detail with reference to FIG. 1.

The processor connection unit 10 includes a CPU interface unit 11, a decoder 12, an input / output buffer 13, and a state register 14. First, the CPU interface unit 11 is connected to the central processing unit of the CPU and performs an interface between control signals, data to be encrypted, and data to be decrypted. In addition, the CPU interface unit 11 includes a signal latch and a driver therein. The decoder 12 decodes the key signal received from the CPU interface unit 11 and outputs it to the memory unit. At this time, the key signal input by the user is a code value for selecting a password and a code for encryption and decryption. The decoder also has a predetermined size of memory and registers. The input / output buffer 13 is composed of first-in-first-out (FIFO) memory, and the CPU interface unit 11 and the DES engine unit 40 store data to be encrypted and decrypted from the CPU interface unit 11. Perform interface between The state register 14 receives and transmits a control signal and a state signal between the CPU interface unit 11 and the DES engine unit 40. Then, the interrupt controller 20 receives the state signal of the DES engine unit 40 and generates a signal according to the encryption or the end of the encryption and the decryption or the end of the decryption and outputs the signal to the state register 14.

The memory unit 30 includes a key memory 31 and a code memory 32. The key memory has a key value for each user, that is, stores a password. In addition, the code memory 32 has a plurality of code values, and selects and enables codes to be encrypted or decrypted according to key values received from the decoder 12. The enabled code is input to the DES engine unit 40. The DES engine unit 40 is composed of a state output unit 41, a DES engine 42, and a key moving memory 43. First, the state output unit 41 inspects the state of the engine and outputs a state according to the result of the inspection. The DES engine 42 encrypts and decrypts data received from the input / output buffer 13 in accordance with the code value received from the code memory 42. The key shift memory 43 has a shift table for shifting the received data to the right or the left. The table according to the DES standard is shown in Table 1 below.

En / De q1 q2 q3 q4 c0 c1 c3 c4 out One 0 0 0 0 0 0 0 0 One One 0 0 0 One 0 0 0 One One One 0 0 0 One 0 0 One 0 2 One 0 0 0 One 0 0 One One 2 One 0 0 0 One 0 One 0 0 2 One 0 0 0 One 0 One 0 One 2 One 0 0 0 0 0 One One 0 2

As shown in Table 1, the value of the key shift memory 43 is read and the received data is shifted left or right for use in encryption and decryption. The block diagram of FIG. 1 may be configured as a programmable gate array (FPGA).

FIG. 2 is a detailed block diagram showing an example of the decoder 12 shown in FIG. Hereinafter, the configuration and operation of the decoder 12 will be described in detail with reference to FIG. 2.

The decoder 101 receives three bits of data A0 to A2, a CS signal, and a reset signal RESET. Therefore, the decoder 101 stores the received data, the signal output according to the CS signal, and the reset signal, in the control register 102 and the state register 103, and the input buffer counter 104 is 4 to 00-11. It is configured to accept bits. The output buffer counter 105 also has the same configuration. The value decoded by the decoder 101 is output to the memory unit 30 through the data port 106.

3 is a detailed block diagram illustrating an input buffer in the structure of the input / output buffer of FIG. 1. Hereinafter, the configuration and operation of the input buffer will be described in detail with reference to FIG. 3.

The data received in 64 bits from the CPU interface unit 11 are sequentially stored in accordance with the FIFO 110 according to the address indicated by the write pointer 111. The data is inputted to four arithmetic operators 115a, 115b, 115c, and 115d that read out data according to an address indicated by the read pointer 113. Therefore, the data recorded in the FIFO 110 is input to the calculator by 16 bits. In addition, the read / write controller 112 examines the state of the FIFO 110 to output a full and empty signals, receives a read and write signal R / W, and writes an address accordingly. Output to 111 or output to read pointer 113. The code buffer 114 receives data from the code memory 114 and inputs the data to each of the calculators 115a, 115b, 115c, and 115d. Each of the calculators 115a, 115b, 115c, and 115d outputs the data received from the code buffer 114 and the data received from the FIFO 110 to the input register 116. The input register 116 is composed of a left register 116a and a right register 116b, and the left register 116a receives and stores the data input by the exclusive truncation from two operators 115a and 115b. The right register 116b receives and stores data input from the other two calculators 115c and 115d.

4 is a detailed block diagram illustrating an output buffer in the structure of the input / output buffer of FIG. 1. Hereinafter, the configuration and operation of the output buffer will be described in detail with reference to FIG. 4.

When the engine unit 30 performs 16 times of operations and then encrypts and decrypts the data stored in the two-part registers 124a and 124b, the data is encrypted or decrypted. Accordingly, the data stored in each part of the register 124 is stored in the FIFO 120 for output. In this case, data is also written to the read / write pointer 122 at the address indicated by the write pointer 121, the right register 124a stores data from 0 to 31 bits, and the left register 124b is from 32. Stores data up to 63 bits. In addition, under the control of the read / write pointer 122, the read pointer 123 indicates an address of data to be output, and the data of the indicated address is output to the CPU interface unit 11. In addition, the read / write controller 112 examines the state of the FIFO 110 and outputs a full and empty signals, receives the read and write signals R / W, and records the address accordingly. The output is performed by the pointer 121 or the read pointer 123.

5 is a block diagram of a part of a DES engine for explaining an initial replacement process of the DES engine. Hereinafter, an initial substitution process of the DES engine will be described in detail with reference to FIG. 5.

The FIFO 130 storing 64-bit data outputs the data to the exclusive OR calculators 133a, 133b, 133c, and 133d by 16 bits. In addition, the mode signal EBC / CBC is input to the AND gate 131, and the other input terminal of the AND gate 131 is connected to the output terminal of the code buffer 132. The code buffer 132 outputs data according to the step to the AND gate 131. The AND gate 131 combines the two signals and inputs them to each exclusive OR operator 133a, 133b, 133c, and 133d. In this case, when the output value of the AND gate 131 is "0", the output of each of the exclusive OR calculators 133a, 133b, 133c, and 133d is not affected. The output values of each of the exclusive ore calculators 133a, 133b, 133c, and 133d are input to the multiplexer 134, and the multiplexer 134 receives and multiplexes the exclusive ored data together with the value of the previous step. . Accordingly, the multiplexed data is stored in the register 135. The register 135 is composed of a left register 135a and a right register 135b, each composed of 32 bits.

6 is a detailed block diagram of a DES engine. Hereinafter, the block configuration and operation of the DES engine will be described in detail with reference to FIG. 6.

Data output from the output memory portion 200 of the input / output buffer 13 is connected to one input terminal of the four exclusive OR calculators 215a, 215b, 215c, and 215d, and the mode signal 201 and the code buffer ( An output terminal of the AND gate 203 for ORing and outputting the data of 204 is connected to the other input terminal of each of the exclusive OR calculators 215a, 215b, 215c, and 215d. Accordingly, each of the exclusive ore calculators 215a, 215b, 215c, and 215d inputs the input signal to the left register 217 and the right register 218. The right register 218 sums the input data with the data stored in the left register 217 and outputs the data to the second operator 224. In addition, the right register 218 is extended by the expansion substituent 219 and is input to the first operator 220.

56 bits of data output from the key memory 206 are separated into 28 bits and input to the left buffer 207 and the right buffer 208. The output data of each of the buffers 207 and 208 is output to each of the buffers 212 and 213 by moving the received data according to the shift value output from the shift table. do. The data output to each of the buffers 212 is selectively substituted by only 48 bits in the substitution selector 214 and output to the first operator. The first operator 220 then outputs the 48-bit data input from the expansion substituent 219 and the 47-bit data input from the substitution selector 214 by using an exclusive or output. The data thus output is stored in the comparison buffer 221 by 6 bits, and is demodulated using the code memory data 222 selected and selected by the key value input by the user. The decoded data is primarily stored in the buffer 223, and the data stored in the buffer 223 is input to the second operator 224. Accordingly, the second operator 224 inputs exclusively 32 bits of data into the step buffer (step (i-1)) 202.

7 is a control flowchart according to the operation of the encryption and decryption apparatus. Hereinafter, a process of encryption and decryption according to the present invention will be described in detail with reference to FIGS. 1 to 7.

In operation 300, the apparatus for performing encryption and decryption maintains a standby state. When receiving data to be encrypted and decrypted through the CPU interface unit 11 in step 302, the engine unit 40 reads a key value from the memory unit 30 through the decoder 12. . At this time, the key value is inputted through the CPU interlace unit 11 in advance and is held by the key memory 31 and the code memory 32. Subsequently, the process proceeds to step 306 to extract the data received in 64 bits into 32 bits of fixed bits. In operation 308, after performing an exclusive OR operation, the code is read from the code memory 32 of the memory unit 30. Thereafter, the process proceeds to step 310 to extract the memory address from the read code, and to step 312, the data stored in the input / output buffer 13 is read. Then, the read data is shifted to the right or left by the value set in the key shift memory 43. Subsequently, if the process proceeds to step 316, the Ri value is stored in Li, and the process proceeds to step 318, where the counter value CT is incremented by one and stored. In step 320, it is checked whether the increased counter value is 15. In this case, 15 is a case in which 16 times of encryption or decryption are performed from 0 to 15 by repeating 16 times when performing DES encryption and decryption. If the check result counter value of step 320 is 15, the process proceeds to step 322 and stores the counter value in the input / output buffer 13. Then, the data stored in the input / output buffer 13 is output to the CPU through the CPU interface unit 11. However, if the counter value is less than 15, the process proceeds to step 306 to perform the process again from the fixed extraction process.

As described above, by using a gate array which is programmable in an apparatus that performs encryption and decryption, a load on the CPU that performs encryption and decryption is reduced, and there is an advantage that encryption and encryption can be performed in near real time.

Claims (3)

An apparatus for performing encryption and decryption, CPU interface unit connected to the central processing unit, A decoder for decoding the key value received through the CPI interface unit and decoding and outputting data; A memory unit for identifying a user by the output of the decoder and outputting data of a set code; An input / output buffer for transmitting and receiving data between the engine unit performing an encryption and decryption process with the CPI interface unit; An engine unit for performing encryption and decryption according to data received from the input / output buffer and code values of the memory unit; An interrupt controller for detecting and outputting a state of the engine unit; And a state register configured to output a state to the central processing unit through the CPI interface unit according to the output of the interrupt controller. The method of claim 1, wherein the memory, An encryption and decryption apparatus, comprising: a key memory for storing a key value and a code memory for selecting a code value. In the control method of the device for performing the encryption and decryption, A fixed extraction process of receiving data and key values and extracting only predetermined bits of data; Performing an exclusive ora operation on the fixed extracted data; Reading data by extracting an address of a memory after the exclusive OR operation; Shifting the read data by a predetermined digit according to the key value; Storing the data in a predetermined register after the shift; Increasing the counter after storing the data and checking whether the increased counter value is a predetermined value; And if the value of the check result counter is a predetermined value, outputting the data and extracting the data if the value is not the predetermined value.