KR20010015045A - Method and apparatus for accessing special purpose registers within a processor - Google Patents

Abstract

PURPOSE: An improved method and device are provided which accesses an exclusive register contained in a processor and can eliminate a delay that is caused by accessing the exclusive register. CONSTITUTION: In this method/device for accessing an exclusive register contained in a processor, a cache inhibition bit and an exclusive register access bit are supplied. A group of exclusive registers (34) is connected to a data cache (13) via a cache bypass bus (31). The bus (31) is available for a cache inhibition access when the cache inhibition bit is shown. However, the data obtained via the operations of the register (34) can be sent to the registers (34) via the bus (31) when the exclusive register access bit is shown.

Description

METHOD AND APPARATUS FOR ACCESSING SPECIAL PURPOSE REGISTERS WITHIN A PROCESSOR}

The present invention relates generally to methods and apparatus for data processing, and more particularly, to a method and apparatus for accessing registers within a processor. More specifically, the present invention relates to a method and apparatus for accessing a register of a specific purpose inside a processor.

In current processor internals, various types of registers, known as special purpose registers or configuration registers, are used to communicate configuration and status information between the processor and software. While the processor is in standard operation, these special purpose registers supply various information to the processor to change the processor's work. Due to the communication role of specific destination registers, specific destination registers must be readable and writable often by software after they have been updated as requested by the processor.

Although the access methods revealed in software are common across all specific purpose registers within the processor, those specific purpose registers themselves are distributed primarily through the various functional blocks of the processor depending on the local specific use of the information they have. Therefore, in prior art designs, a particular destination register is typically placed near a specific block of hardware that reads and writes the specific destination register. Access to widely distributed, purpose-built registers is provided by dedicated buses with dedicated control circuitry (eg, register engines) and unique protocols. Dedicated buses are commonly connected through all the different areas of the entire processor, since dedicated buses need to be connected to all functional units that contain registers of particular purpose. Thus, due to the long and distributed organization of dedicated buses, there is a large delay associated with specific destination register access instructions. As a result, it would be desirable to provide an improved method and apparatus for accessing a register of a specific purpose, within the processor where the delay associated with the specific object of the register has been eliminated.

In addition to the improved modes of use, further objects and accompanying advantages, the invention itself will be better understood from the following detailed description of the embodiments, with reference to the accompanying drawings.

In accordance with an improved embodiment of the present invention, cache inhibit bits and special purpose registers are provided. Several groups of specific destination registers are connected to the data cache through the cache bypass bus. The cache bypass bus may be used for cache inhibit access when the cache inhibit bit appears. However, when a special purpose register access bit appears, data from the special purpose register operation is allowed to be transferred to the special purpose register via the cache bypass bus.

All objects, features and advantages of the present invention will become apparent from the following detailed description.

1 is a block diagram of a processor in which an improved embodiment of the present invention may be incorporated.

2 is a block diagram of a register having a specific purpose inside a processor according to the prior art;

3 is a block diagram of a particular purpose register placed within the processor of FIG. 1 in accordance with an improved embodiment of the present invention.

4 is a high level logic flow diagram for a method for remapping SPR access inside a processor in accordance with an improved embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

10: processor

11: command unit

12: bus interface unit

13: data cache

14: instruction cache

15: water purification part

16: load / store

17: floating point part

The invention may be practiced in various processors. Such processors are, for example, reduced instruction set computer (RISC) processors or complex instruction set computer (CISC) processors. For purposes of explanation, the improved embodiment of the present invention, described below, is implemented in a RISC processor, such as PowerPCp manufactured by IBM of Armonk, New York.

Reference is now made to FIG. 1, which is a block diagram of a processor incorporating an improved embodiment of the present invention. Inside the processor 10, the bus interface 12 is connected to a data cache 13 and an instruction cache 14. Both data cache 13 and instruction cache 14 allow fast processing of the processor 10 to store a subset of previously transmitted data or instructions from main memory (not shown) with a relatively fast access time. It's a cache. The instruction cache 14 is further connected to an instruction portion 11 that fetches instructions from the instruction cache 14 during each execution cycle.

The processor 10 also includes at least three execution units, namely an integer unit 15, a load / store unit (LSU) 16 and a floating-point unit 17. Each execution unit 15-17 may execute one or more kinds of instructions, and all execution units 15-17 may operate simultaneously during each processor cycle. After the command is executed and terminated, the predetermined execution unit 15-17 stores the data results in each new name buffer, depending on the command type. Subsequently, when a predetermined execution unit 15-17 sends a signal to the termination unit 20, execution of the instruction is terminated. Finally, each instruction is terminated in program order, with the result that data is transferred from each new name buffer to general purpose register 18 or floating point register 19.

Reference is now made to FIG. 2, which shows a block diagram of a specific purpose register placement within processor 21, according to the prior art. As shown, several specific purpose registers (SPRs) 24 are connected to the SPR engine 22 via the SPR bus 23. SPR engine 22 is further coupled to the data path for data cache 25. The stream of instruction opcode 29 that accesses the SPR 24 is delivered to the SPR engine 22 via the bus 26. The command opcode includes instructions that can change the contents of the SPR 24. For example, the instruction opcode may include instructions to load or store data in the SPR 24 (eg, special mfspr and mtspr instructions in a PowerPC processor).

In the prior art, SPR 24 has typically been placed near a particular block of hardware, such as at an end (not shown) needed to read and write any results to SPR 24. Access to the SPR 24 is provided with a unique SPR bus protocol by the SPR engine 22 and the SPR bus 23. Since the SPR bus 23 needs to be connected to all hardware including the SPR, the SPR bus 23 is mainly connected through different areas of the processor 21. As a result, a requirement for the instructions to access the SPR buffer to be tolerated is the large delay incurred in the long and distributed SPR bus 23 organization. In addition, both the SPR engine 22 and the SPR bus 23 must be defined, designed, and verified during the design phase of the processor 21. Due to the sophisticated arrangement of the SPR engine 22 and the SPR bus 23, a huge chip area is occupied by the SPR engine 22 and the SPR bus 23. If the sophisticated bus structure of the SPR engine 22 and the SPR bus can be eliminated, then the processor 21 chip area can be certainly reduced, making the processor 21 much cheaper and more effective.

In general, data is typically written through the data cache during non-cache prohibition operations before the data is delivered to the system bus. However, during the cache inhibit operation, without transferring a copy of the data to the data cache, the data will only be transferred between the executive and the system bus. Therefore, according to an improved embodiment of the present invention, the SPR operation can be handled by using a mechanism similar to that used to handle cache prohibition operations.

Reference is now made to FIG. 3, which shows a block diagram of disposing a register of a particular purpose inside the processor 10 of FIG. 1, in accordance with an improved embodiment of the present invention. As shown, several SPRs 34 are directly connected to the cache bypass bus 31. During the non-cache inhibit operation, if the cache inhibit bit 32 does not appear, a copy of the data is delivered to the data cache 13 before the data is transferred to the system bus 38. During the cache prohibit operation, if the cache prohibit bit 32 appears, data will only be transferred between the execution unit (not shown) and the system bus 38. The data bypasses the data via the cache bypass bus 31.

With regard to the present invention, since the SPR 34 is now directly connected to the cache bypass bus 31, the SPR operation can be handled by using the mechanism used to handle the cache inhibit operation, which is a cache inhibit load and store operation. . In the PowerPCp embodiment, for example, the mtspr and mfspr instructions are executed by the same LUS 16 as the execution unit that handles all cache inhibit load and store operations.

Incidentally, all the buses required for the cache inhibit operation on the chip can also be used to perform the SPR operation. In addition, two or more logic blocks may be included to take advantage of mechanisms used to handle cache inhibit operations, i.e., decoder logic and driver control. Decoder logic is used to enforce a cache inhibit state during the entire SPR operation because there is no segment register connection (cache inhibit bit 32) that is normally provided to indicate the cache inhibit state. Driver control, which may be implemented as a switch or an AND gate, protects the SPR operation from leaving the processor 10 on the system bus 38. Decoder logic may be implemented in the form of special purpose register access (SPRA) bits 33. As with the improved embodiment, the cache inhibit state for the SPR operation may be enforced by causing the SPRA bit 33 to appear during and before the entire SPR operation. The state of the cache inhibit bit 32 is meaningless while the SPR is operating.

For a simpler design, the SPR 34 can be stored in a single array or register file structure. Therefore, only minimal impacts are loaded and stored in memory in the form of reducing execution bandwidth and increasing bus load. However, the reduced bandwidth and increased load must be offset by the advantages gained in the simpler and more convenient deployment of the SPR 34.

In order to maintain high performance on a common bus inside the processor 10 with an additional load of the SPR 34, some local buffering or latching must be provided to isolate the SPR 34. The SPR 34 should generally be placed in close proximity to a common bus that is far from the implementation that uses or updates the SPR 34. This is because the change to the SPR 34 by software must be carefully enforced by synchronizing the instructions to protect proper operation on an out-of-order processor such as the processor 10. Therefore, in rare cases, the additional transfer cycle of the changed state from the execution part using the value can easily be amortized. Hardware updates can also be installed pipelined to control the transfer time.

Reference is now made to FIG. 4, which shows a flow diagram of high level logic for a method of remapping SPR access inside a processor, in accordance with an improved embodiment of the present invention. Beginning at block 40, as shown in block 41, a determination is made as to whether the operation is a cache inhibit operation, and as shown in block 42, another determination is made as to whether the operation is an SPR operation or not. If the operation is one of a cache inhibit operation or an SPR operation, the data is passed on the cache bypass bus to avoid the data cache, as shown in block 45. If the operation is neither a cache inhibit operation nor an SPR operation, the data is passed to the data cache, as shown in block 43, and then to the system bus, as shown in block 44.

After the data is transferred to the cache bypass bus, a determination is made as to whether a particular purpose register access bit (eg, SPRA bit 33 in FIG. 3) has appeared, as shown in block 46. If no specific purpose register access bits have appeared, then the data is transferred to the system bus, as shown in block 44; otherwise, the data is transferred to the appropriate SPR, as shown in block 47.

As noted above, the present invention provides a method and apparatus for remapping SPR access inside a processor. With the placement of the SPR and the improvement of the SPR operation, the SPR controller and SPR bus and their specific rules and characteristics in the prior art configuration can be eliminated.

Since the present invention has been described and illustrated with reference to particularly improved embodiments, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention.

As described above, according to the present invention, the arrangement of the SPR and the improvement of the SPR operation can remove the SPR controller and the SPR bus and their specific specifications and characteristics in the prior art configuration, thereby reducing the chip area.

Claims (12)

In the processor internal device, Cache prohibit bits and special purpose register access bits; A plurality of specific destination registers coupled to the data cache via a cache bypass bus that may be used for a cache inhibit operation when the cache inhibit bit appears; Means for causing data to be transferred to the plurality of specific purpose registers from the specific purpose register operation through the cache bypass bus when the specific purpose register access bits are encountered. 2. The apparatus of claim 1, wherein said specific destination register operation comprises moving to a specific destination register instruction. The processor internal apparatus of claim 1, wherein the specific purpose register operation comprises moving from a specific purpose register instruction. A load / store section for executing a memory access instruction; A bus coupled to the load / store via a data path and configured to read and write to system memory by the load / store in response to the load / store to execute the memory access command; A specific purpose register coupled to the data path and for reading and writing to a specific purpose register by the load / store in response to the load / store for executing a specific purpose register command. Processor. 5. The system of claim 4, wherein the processor further comprises cache control logic and cache memory coupled to the bus to control access to cache memory, The cache control logic enables any memory access by the load / store to update the cache memory, prohibits any other memory access by the load / store to update the cache memory , For the load / store which executes a register command of a particular purpose, the control logic prohibits the load / store from updating the cache memory. 6. The system of claim 5, wherein the processor further comprises a driver coupled to the bus for writing to the system memory by the load / store unit, For the load / store which executes a register command of a particular purpose, the control logic inhibits the driver to prevent the load / store from writing to the system memory. In the information processing system, System memory coupled to the system bus; A processor coupled to the system bus, wherein the processor includes: A load / store section for executing a memory access instruction; A bus coupled to the load / store via a data path and configured to read and write to system memory by the load / store in response to the load / store for executing the memory access command; A particular link connected to the load / store via the data path and performing reading and writing to the register of the specific purpose by the load / store in response to the load / store which executes a register command of a specific purpose; An information processing system comprising a register of interest. 8. The system of claim 7, wherein the processor further comprises cache control logic and cache memory coupled to the bus to control access to cache memory, The cache control logic enables any memory access by the load / store to update the cache memory, prohibits any other memory access by the load / store to update the cache memory , For the load / store which executes a specific destination register instruction, the control logic forbids the load / store to update the cache memory. 8. The system of claim 7, wherein the processor further comprises a driver coupled to the bus for writing to system memory by the load / store unit, For a load / store which executes a register command of a particular purpose, the control logic inhibits the driver to prevent the load / store from writing to the system memory. In a method of accessing a register for a specific purpose in the processor, Executing a memory access instruction at the load / store; Reading and writing to a system memory by a load / store unit in response to the load / store unit executing one of the memory access commands via a bus connected to the load / store unit; The load / store unit, in response to the load / store unit executing one of the memory access instructions in the form of a specific object register in the form of a specific object register, over a bus connected to the load / store unit, And reading and writing. 11. The method of claim 10, wherein the load / store unit, in response to the load / store unit executing one of memory access commands, writes and reads to the cache memory via a bus connected to the load / store unit. Further comprising the steps of: For the load / store which executes a register command of a particular purpose, control logic forbids the load / store to update the cache memory. 11. The method of claim 10, further comprising the step of writing to a system memory by the load / store section, For a load / store that executes a register command of a particular purpose, control logic inhibits the driver to prohibit the load / store from writing to system memory.