KR20010010131A - Method for fabricating chip on board package - Google Patents
Method for fabricating chip on board package Download PDFInfo
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- KR20010010131A KR20010010131A KR1019990028848A KR19990028848A KR20010010131A KR 20010010131 A KR20010010131 A KR 20010010131A KR 1019990028848 A KR1019990028848 A KR 1019990028848A KR 19990028848 A KR19990028848 A KR 19990028848A KR 20010010131 A KR20010010131 A KR 20010010131A
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- printed circuit
- circuit board
- semiconductor chip
- chip
- conductive wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
본 발명은 칩 온 보드 패키지의 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 칩과 인쇄회로기판을 전기적으로 연결시킨 후에 코팅공정 중에서 댐을 형성하여 반도체 칩을 감싸는 코팅수지가 넓게 퍼지는 것을 방지한 칩 온 보드 패키지의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a chip-on-board package, and more particularly, a chip in which a coating resin surrounding a semiconductor chip is prevented from spreading by forming a dam during the coating process after electrically connecting the semiconductor chip and the printed circuit board. It relates to a method of manufacturing the on-board package.
최근, 전자·정보기기가 대용량화, 경량화, 박형화되어 감에 따라 반도체 칩 패키지 또한 고밀도, 소형화 및 박형화를 요구하고 있다. 이로 인해 리드 프레임 상에 반도체 칩을 부착하여 패키징한 후에 반도체 칩 패키지를 인쇄회로기판에 실장하는 과정을 생략하고 반도체 칩을 곧바로 인쇄회로기판에 실장하여 패키징하는 칩 온 보드 패키지가 주목을 받고 있다.In recent years, as electronic and information devices have increased in capacity, weight, and thickness, semiconductor chip packages have also required high density, miniaturization, and thickness. For this reason, the chip-on-board package, which attaches and packages a semiconductor chip on a lead frame, omits a process of mounting a semiconductor chip package on a printed circuit board and directly mounts the semiconductor chip on a printed circuit board and packages the package.
여기서, 칩 온 보드 패키지의 제조 과정을 개략적으로 설명하면 다음과 같다.Here, the manufacturing process of the chip-on-board package is described as follows.
먼저, 외부에서 인가된 전기적 신호를 전달하는 회로패턴들이 복수개 형성된 인쇄회로기판의 소정부분에 반도체 칩을 실장하고, 도전성 와이어를 이용하여 반도체 칩과 회로패턴들을 전기적으로 연결시킨다.First, a semiconductor chip is mounted on a predetermined portion of a printed circuit board on which a plurality of circuit patterns for transmitting an electrical signal applied from the outside are formed, and the semiconductor chip and the circuit patterns are electrically connected using conductive wires.
이어, 반도체 칩과 도전성 와이어 및 도전성 와이어가 연결된 회로패턴들의 소정부분을 보호하기 위해서 반도체 칩에서부터 인쇄회로기판의 가장자리 소정부분까지를 에폭시 수지로 덮어 봉지체를 형성한다.Subsequently, in order to protect a predetermined portion of the semiconductor chip, the conductive wire, and the circuit patterns to which the conductive wire is connected, an encapsulation body is formed by covering the semiconductor chip to a predetermined portion of the edge of the printed circuit board with an epoxy resin.
여기서, 반도체 칩에서부터 인쇄회로기판의 소정영역까지를 봉지하는 방법으로는 반도체 칩 주변을 에폭시 수지로 덮은 후에 에폭시 수지를 경화시키는 코팅방법과, 에폭시 몰딩 컴파운드를 프레스내의 금형에 유입시켜 몰드한 후 경화시키는 몰딩 방식이 있다.The method of encapsulating the semiconductor chip to a predetermined area of the printed circuit board includes a coating method of curing the epoxy resin after covering the semiconductor chip periphery with an epoxy resin, and curing the epoxy molding compound by pouring it into a mold in a press and then curing it. There is a molding method.
그런데, 몰딩 방식은 인쇄회로기판의 물성이나 구조 및 크기 등에 의해 많은 제약을 받을 수 있으므로 현재에는 주로 코팅방식이 이용된다.However, since the molding method may be subject to many restrictions due to the physical properties, structure, and size of the printed circuit board, a coating method is mainly used.
그러나, 코팅방법에도 몇가지 문제점이 있다.However, there are some problems with the coating method.
첫 번째로는 반도체 칩과 인쇄회로기판을 보호하기 위해서 반도체 칩의 주변에 떨어뜨린 겔상태의 에폭시 수지가 저점도이기 때문에 넓게 퍼져 칩 온 보드 패키지의 사이즈가 커진다.First, since the gel-type epoxy resin dropped around the semiconductor chip to protect the semiconductor chip and the printed circuit board is low viscosity, the chip-on-board package increases in size.
두 번째로는, 에폭시 수지가 넓게 퍼짐으로 인해 봉지체의 높이가 낮아져 반도체 칩과 인쇄회로기판을 전기적으로 연결하는 와이어가 봉지체의 외부로 노출되어 부식되거나 단선되며, 공기가 흡습되어 열팽창 계수의 차이로 인해 봉지체 및 반도체 칩에 크랙이 발생될 수 있는 등의 문제로 제품의 신뢰성이 저하된다.Second, due to the wide spread of epoxy resin, the height of the encapsulation is lowered, so that the wires electrically connecting the semiconductor chip and the printed circuit board are exposed to the outside of the encapsulation to corrode or disconnect, and the air is absorbed so that the coefficient of thermal expansion Due to the difference, cracks may occur in the encapsulation member and the semiconductor chip, thereby reducing the reliability of the product.
세 번째로, 에폭시 수지의 퍼짐으로 인해 봉지체의 표면이 라운드 형상을 이루기 때문에 칩 온 보드 패키지를 만든 후 제품의 사향 및 제조회사의 로고를 마킹하기 위해서는 봉지체의 상부면을 그라인딩하여 평탄화시키는 별도의 공정이 추가되어 제품의 생산성이 저하되는 문제점이 있다.Third, since the surface of the encapsulation is round due to the spread of the epoxy resin, after the chip-on-board package is made, in order to mark the musk of the product and the manufacturer's logo, a separate surface of the encapsulation is ground and flattened. There is a problem in that the productivity of the product is reduced by the addition of the process.
한편, 그라인딩 공정을 진행할 때 발생되는 에폭시 분진으로 인해 작업 환경이 오염되는 것을 방지하기 위해서 에폭시 분진을 제거하기 위한 설비가 추가된다.On the other hand, in order to prevent the contamination of the working environment due to the epoxy dust generated during the grinding process, a facility for removing the epoxy dust is added.
이러한 문제점을 개선하기 위해서 인쇄회로기판을 제작할 때 인쇄회로기판의 소정영역에 소정높이를 갖는 댐을 형성한 후에 인쇄회로기판의 소정영역에 반도체 칩을 실장하고 도전성 와이어를 이용하여 반도체 칩과 인쇄회로기판에 형성된 회로패턴들을 전기적으로 연결시킨다.In order to solve this problem, when fabricating a printed circuit board, a dam having a predetermined height is formed in a predetermined area of the printed circuit board, the semiconductor chip is mounted in the predetermined area of the printed circuit board, and the semiconductor chip and the printed circuit are formed using conductive wires. The circuit patterns formed on the substrate are electrically connected.
이후, 반도체 칩과 도전성 와이어 및 도전성 와이어가 연결된 회로패턴들의 일단을 보호하기 위해서 반도체 칩에서부터 인쇄회로기판의 가장자리 소정부분까지를 에폭시 수지로 덮어 봉지체를 만든다.Subsequently, in order to protect one end of the semiconductor chip, the conductive wire, and the circuit patterns to which the conductive wire is connected, an encapsulation body is formed by covering the semiconductor chip from a predetermined portion of the printed circuit board with an epoxy resin.
이때, 인쇄회로기판의 가장자리에 형성된 댐이 에폭시 수지의 흐름을 방지하기 때문에 에폭시 수지가 넓게 퍼지지 못하여 소정높이를 갖는 정확한 몰딩 형상을 이룬다.At this time, since the dam formed at the edge of the printed circuit board prevents the flow of the epoxy resin, the epoxy resin does not spread widely to form an accurate molding shape having a predetermined height.
그러나, 이와 같이 인쇄회로기판을 제조하는 과정에서 댐을 형성할 경우 제조공정이 복잡하여 반도체 칩 패키지의 제조 비용이 상승된다.However, when the dam is formed in the process of manufacturing the printed circuit board, the manufacturing process is complicated and the manufacturing cost of the semiconductor chip package is increased.
따라서, 본 발명의 목적은 상기와 같은 문제점을 감안하여 안출된 것으로써, 칩 온 보드 패키지의 제조비용을 절감하는데 있다.Accordingly, an object of the present invention has been made in view of the above problems, to reduce the manufacturing cost of the chip-on-board package.
본 발명의 다른 목적은 반도체 칩과 인쇄회로기판을 덮는 수지가 넓게 퍼지는 것을 방지하여 칩 온 보드 패키지의 크기를 줄이고 제품의 신뢰성을 향상시키는데 있다.Another object of the present invention is to prevent the resin covering the semiconductor chip and the printed circuit board from spreading widely to reduce the size of the chip-on-board package and improve the reliability of the product.
본 발명의 또 다른 목적은 그라인딩 공정을 생략하여 제조 공정을 단순화시키는데 있다.Another object of the present invention is to simplify the manufacturing process by omitting the grinding process.
본 발명의 또 다른 목적은 다음의 상세한 설명과 첨부된 도면으로부터 보다 명확해 질 것이다.Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.
도 1은 본 발명에 의한 칩 온 보드 패키지의 구조를 나타낸 평면도.1 is a plan view showing the structure of a chip on board package according to the present invention.
도 2a 내지 도 2d는 본 발명에 의한 칩 온 보드 패키지의 제조 과정을 설명하기 위한 설명도.2A to 2D are explanatory diagrams for explaining a manufacturing process of a chip on board package according to the present invention.
이와 같은 목적을 달성하기 위해서 본 발명은 복수개의 회로패턴들과 칩 실장부분이 형성된 인쇄회로기판의 일면 중 칩 실장부분에 접착제를 부착하고 접착제의 상부면에 반도체 칩을 부착하여 인쇄회로기판과 반도체 칩을 접착시키고, 반도체 칩의 일면에 형성된 복수개의 본딩패드들 각각에 도전성 와이어의 일단을 본딩시키며 도전성 와이어의 타단은 회로패턴들의 일단에 본딩시켜 반도체 칩과 상기 인쇄회로기판을 전기적으로 연결시킨 후에, 도전성 와이어의 바깥쪽으로 소정간격 이격된 인쇄회로기판의 소정지점에 점도를 갖는 코팅수지를 인쇄회로기판의 테두리를 따라 도포하고 수십초동안 경화시켜 소정높이의 댐을 형성하고, 이어 댐의 내부에 점도를 갖는 코팅수지를 채워 코팅수지로 반도체 칩과 도전성 와이어 및 도전성 와이어가 연결된 회로패턴들의 소정부분을 감싸고 코팅수지를 경화시켜 봉지체를 형성한다.In order to achieve the above object, the present invention attaches an adhesive to a chip mounting portion of a surface of a printed circuit board on which a plurality of circuit patterns and a chip mounting portion are formed, and attaches a semiconductor chip to an upper surface of the adhesive to print a printed circuit board and a semiconductor. Bonding the chip, bonding one end of the conductive wire to each of the plurality of bonding pads formed on one surface of the semiconductor chip, and bonding the other end to the one end of the circuit patterns to electrically connect the semiconductor chip and the printed circuit board. A coating resin having a viscosity at a predetermined point of the printed circuit board spaced apart by a predetermined distance to the outside of the conductive wire is applied along the edge of the printed circuit board and cured for several tens of seconds to form a dam having a predetermined height. Fill the coating resin with viscosity and open the semiconductor chip, conductive wire and conductive wire with coating resin. The circuit wrapped around a predetermined portion of a pattern by curing the coated resin forms a plug.
이하, 본 발명에 의한 칩 온 보드 패키지의 구조 및 제조 방법을 첨부된 도면 도 1과 도 2를 참조하여 설명하면 다음과 같다.Hereinafter, a structure and a manufacturing method of a chip on board package according to the present invention will be described with reference to FIGS. 1 and 2.
본 발명에 의한 칩 온 보드 패키지(100)는 도 1에 도시된 바와 같이 크게 인쇄회로기판(110), 인쇄회로기판(110)의 소정부분에 접착되는 반도체 칩(130), 반도체 칩(130)과 인쇄회로기판(110)에 본딩되어 이들을 전기적으로 연결시켜 주는 도전성 와이어(140), 도전성 와이어(140)와 소정간격 이격되어 인쇄회로기판(110)의 테두리부를 따라 형성되는 댐(150) 및 반도체 칩(130)에서부터 댐(150)이 형성된 부분까지를 덮는 봉지체(160)로 구성된다.The chip-on-board package 100 according to the present invention includes a semiconductor chip 130 and a semiconductor chip 130 bonded to a predetermined portion of a printed circuit board 110, a printed circuit board 110, as shown in FIG. 1. And a conductive wire 140 bonded to the printed circuit board 110 and electrically connected to the printed circuit board 110, a dam 150 and a semiconductor formed along the edge of the printed circuit board 110 at a predetermined interval from the conductive wire 140. It consists of an encapsulation member 160 covering the chip 130 from the dam 150 is formed.
여기서, 인쇄회로기판(110)의 상부면에는 전기적 신호의 전달 경로를 제공하는 회로패턴들(112)이 복수개 형성되며, 인쇄회로기판(112)의 하부면에는 외부의 설비와 접속되어 외부에서 신호가 입력되는 접속단자들(114; 도 2d참조)이 복수개 형성되는데, 이들 접속단자들(114)은 인쇄회로기판(110)을 관통하는 비아홀들(116)을 통하여 회로패턴들(112)과 전기적으로 연결된다.Here, a plurality of circuit patterns 112 are provided on the upper surface of the printed circuit board 110 to provide an electrical signal transmission path, and the lower surface of the printed circuit board 112 is connected to an external facility to provide a signal from outside. A plurality of connection terminals 114 (refer to FIG. 2D) to which inputs are input are formed, and these connection terminals 114 are electrically connected to the circuit patterns 112 through the via holes 116 penetrating the printed circuit board 110. Is connected.
또한, 인쇄회로기판(110)의 상부면 중앙부분에는 반도체 칩(130)이 실장되는 칩 실장영역(118)이 형성되는데, 칩 실장영역(118)은 보통 칩 온 보드 패키지(100)의 전체 높이를 낮추기 위하여 소정깊이를 갖는 캐비티 가공이 이루어진다.In addition, a chip mounting region 118 in which the semiconductor chip 130 is mounted is formed at the center portion of the upper surface of the printed circuit board 110, and the chip mounting region 118 is usually the overall height of the chip on board package 100. Cavity processing having a predetermined depth is made to lower the temperature.
그리고, 반도체 칩(130)의 상부면에는 회로패턴들(112)로부터 전달된 전기적 신호가 입력되는 본딩패드들(132)이 복수개 형성되는데, 본딩패드들(112)과 회로패턴들(112)의 일단에 도전성 와이어(140)가 본딩되어 반도체 칩(130)과 인쇄회로기판(110)을 적기적으로 연결시킨다.In addition, a plurality of bonding pads 132 to which electrical signals transmitted from the circuit patterns 112 are input are formed on the upper surface of the semiconductor chip 130, wherein the bonding pads 112 and the circuit patterns 112 are formed. The conductive wire 140 is bonded at one end to timely connect the semiconductor chip 130 and the printed circuit board 110.
이와 같이 구성된 칩 온 보드 패키지의 제조 방법을 첨부된 도면 도 2a 내지 도 2d를 참조하여 설명하면 다음과 같다.A method of manufacturing the chip on board package configured as described above will be described with reference to FIGS. 2A through 2D.
먼저, 도 2a에 도시된 바와 같이 인쇄회로기판(110)의 중앙부분에 형성된 칩 실장영역(118)의 기저면에 절연성 재질의 접착제(120)를 부착시키고, 접착제(120)의 상부면에 반도체 칩(130)을 접착시킴으로써, 인쇄회로기판(110)과 반도체 칩(130)을 상호 부착한다.First, as illustrated in FIG. 2A, an insulating adhesive 120 is attached to a base surface of a chip mounting region 118 formed at a central portion of the printed circuit board 110, and a semiconductor chip is attached to an upper surface of the adhesive 120. By adhering the 130 to each other, the printed circuit board 110 and the semiconductor chip 130 are attached to each other.
이후에 도 2b에 도시된 바와 같이 금 또는 알루미늄과 같이 전도성이 뛰어난 재질로 형성된 도전성 와이어(140)의 일단을 반도체 칩(130)에 형성된 각 본딩패드들(132)에 접속시키고, 도전성 와이어(142)의 타단은 반도체 칩(130)과 인접한 회로패턴(112)의 일단에 본딩시켜 반도체 칩(130)과 인쇄회로기판(110)을 전기적으로 연결시킨다.After that, as shown in FIG. 2B, one end of the conductive wire 140 formed of a material having excellent conductivity such as gold or aluminum is connected to each of the bonding pads 132 formed on the semiconductor chip 130, and the conductive wire 142 The other end of) is bonded to one end of the circuit pattern 112 adjacent to the semiconductor chip 130 to electrically connect the semiconductor chip 130 and the printed circuit board 110.
이어, 도 2c에 도시된 바와 같이 도전성 와이어(140)에서 바깥쪽으로 소정간격 이격된 지점에 코팅노즐을 이용하여 인쇄회로기판(110)의 테두리를 따라 코팅수지로 댐라인을 그리고 수십초 동안 경화공정을 진행하여 소정높이를 갖는 댐(150)을 형성한다.Subsequently, as shown in FIG. 2C, a dam line is formed with a coating resin along the edge of the printed circuit board 110 using a coating nozzle at a point spaced outwardly from the conductive wire 140, and then hardened for several tens of seconds. Proceeding to form a dam 150 having a predetermined height.
이때, 코팅 노즐로 그린 댐라인은 인쇄회로기판과 대응되는 형상의 링이되고, 경화공정에서는 댐라인을 이루는 코팅수지가 흘러내지지 않을 정도로만 경화시키면 되는데 그 시간은 대략 30초정도이다.At this time, the dam line drawn by the coating nozzle becomes a ring of a shape corresponding to the printed circuit board, and in the curing process, only the coating resin forming the dam line does not flow out, but the time is about 30 seconds.
계속해서, 댐(150)을 형성할 때 사용된 코팅수지와 점도가 동일한 코팅수지로 도 2d에 도시된 바와 같이 댐(150)의 내부에 채워 반도체 칩(130)과 도전성 와이어(140) 및 도전성 와이어(140)가 연결된 회로패턴들(112)의 소정부분을 에폭시 수지로 감싼다.Subsequently, the semiconductor chip 130 and the conductive wire 140 and the conductive material are filled with the coating resin having the same viscosity as the coating resin used when forming the dam 150, as shown in FIG. 2D. Predetermined portions of the circuit patterns 112 to which the wire 140 is connected are wrapped with an epoxy resin.
여기서, 코팅공정은 댐라인을 그릴 때 사용된 코팅노즐을 이용하여 댐(150) 쪽에서 반도체 칩(130) 쪽으로 나선형을 그리면서 반도체 칩(130)과 도전성 와이어(140) 및 회로패턴들(112)을 덮는다.Here, in the coating process, the semiconductor chip 130, the conductive wire 140, and the circuit patterns 112 are spiraled from the dam 150 side toward the semiconductor chip 130 using the coating nozzle used to draw the dam line. To cover.
이와 같은 코팅공정에서 인쇄회로기판(110)의 소정영역에 형성된 댐(150)이 점도가 낮은 에폭시 수지의 흐름을 방지하기 때문에 에폭시 수지가 넓게 퍼지지 못하고 소정높이를 갖는 정확한 몰딩 형상을 이룬다.In this coating process, since the dam 150 formed in the predetermined region of the printed circuit board 110 prevents the flow of the epoxy resin having a low viscosity, the epoxy resin does not spread widely but forms an accurate molding shape having a predetermined height.
이어, 댐(150)의 내부를 채운 코팅수지, 예를 들어 에폭시 수지를 약 6시간 정도 경화시킴으로써 반도체 칩(130)과 도전성 와이어(140) 및 인쇄회로기판(110)의 소정부분을 외부환경으로부터 보호하는 봉지체(160)를 형성한다.Subsequently, the coating resin filling the inside of the dam 150, for example, an epoxy resin, is cured for about 6 hours, thereby allowing a predetermined portion of the semiconductor chip 130, the conductive wire 140, and the printed circuit board 110 to be removed from the external environment. The encapsulation body 160 is protected.
바람직하게, 댐(150)을 형성하는 코팅수지의 점도는 봉지체(160)를 형성하는 코팅수지의 점도와 동일하거나 약단 높다.Preferably, the viscosity of the coating resin forming the dam 150 is the same as or slightly higher than that of the coating resin forming the encapsulation body 160.
또한, 코팅수지가 퍼지는 것을 방지하기 위해서 댐의 높이를 인쇄회로기판의 높이보다 약간 높게 형성한다.In addition, the height of the dam is formed slightly higher than the height of the printed circuit board to prevent the coating resin from spreading.
이와 같이 반도체 칩(130)과 도전성 와이어(140) 및 회로패턴(112)의 소정부부를 보호하기 위한 봉지체(160)가 형성되면 봉지체(160)의 상부면에 제품의 사양 및 제조회사의 로고를 새기는 마킹공정을 진행함으로써, 칩 온 보드 패키지(100)의 조립공정을 완료한다.As such, when the encapsulation member 160 is formed to protect the semiconductor chip 130, the conductive wire 140, and the predetermined portion of the circuit pattern 112, the specification of the product and the manufacturer's By proceeding the marking process to inscribe the logo, the assembly process of the chip on board package 100 is completed.
상술한 바와 같이 봉지체를 형성하는 단계에서 코팅수지를 이용하여 인쇄회로기판과 동일한 형상의 댐라인을 그리고 댐라인을 이루는 코팅수지를 약 30초 정도 경화시켜 댐을 형성함으로써, 원하는 높이의 댐을 쉽게 형성할 수 있다.As described above, in the step of forming the encapsulation body, the dam line having the same shape as the printed circuit board and the coating resin forming the dam line are cured for about 30 seconds to form a dam, thereby forming a dam having a desired height. It can be easily formed.
따라서, 인쇄회로기판을 제작하는 공정 중에 댐을 형성하는 것보다 인쇄회로기판을 반도체 칩을 실장하는 공정중에서 댐을 형성하는 것이 훨씬 쉽고 기존에 코팅공정을 진행할 때 사용되던 코팅노즐을 사용하기 때문에 별도로 추가되는 설비가 없다.Therefore, it is much easier to form a dam in the process of mounting a semiconductor chip to a printed circuit board than to form a dam in the process of manufacturing a printed circuit board, and since the coating nozzle used in the conventional coating process is used separately, There is no facility added.
이상에서 설명한 바와 같이 코팅수지를 이용하여 봉지체를 형성하는 공정에서 인쇄회로기판에 댐을 형성할 경우, 인쇄회로기판의 제작공정에서 댐을 형성하는 것보다 원가 및 댐형성 시간을 절감할 수 있는 효과가 있다.As described above, when the dam is formed on the printed circuit board in the process of forming the encapsulation using the coated resin, the cost and dam formation time can be reduced than the dam is formed in the manufacturing process of the printed circuit board. It works.
또한, 인쇄회로기판에 반도체 칩을 실장하는 공정 중에서 댐이 형성되기 때문에 소정의 수지가 넓게 퍼지지 못함으로써 소정높이를 갖는 정확한 봉지체 형상을 이기 때문에 봉지체의 상부면을 갈아내는 그라인딩 공정을 생략할 수 있어 제품의 생산성 및 신뢰성이 향상될 수 있는 효과가 있다.In addition, since the dam is formed in the process of mounting the semiconductor chip on the printed circuit board, the grinding process for grinding the upper surface of the encapsulation is omitted since the resin is not formed wide and thus has an accurate encapsulation shape having a predetermined height. There is an effect that can improve the productivity and reliability of the product.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990028848A KR20010010131A (en) | 1999-07-16 | 1999-07-16 | Method for fabricating chip on board package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990028848A KR20010010131A (en) | 1999-07-16 | 1999-07-16 | Method for fabricating chip on board package |
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| Publication Number | Publication Date |
|---|---|
| KR20010010131A true KR20010010131A (en) | 2001-02-05 |
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| KR1019990028848A KR20010010131A (en) | 1999-07-16 | 1999-07-16 | Method for fabricating chip on board package |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999368B2 (en) | 2008-09-29 | 2011-08-16 | Samsung Electronics Co., Ltd. | Semiconductor package having ink-jet type dam and method of manufacturing the same |
| KR20150059479A (en) * | 2013-11-22 | 2015-06-01 | 인제대학교 산학협력단 | Enhancing method texture properties and shelf life of glutinous rice cake by high hydrostatic pressure treatment of gelatinized glutinous rice dough |
-
1999
- 1999-07-16 KR KR1019990028848A patent/KR20010010131A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999368B2 (en) | 2008-09-29 | 2011-08-16 | Samsung Electronics Co., Ltd. | Semiconductor package having ink-jet type dam and method of manufacturing the same |
| KR20150059479A (en) * | 2013-11-22 | 2015-06-01 | 인제대학교 산학협력단 | Enhancing method texture properties and shelf life of glutinous rice cake by high hydrostatic pressure treatment of gelatinized glutinous rice dough |
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