KR20010002748A - Clock signal generator using phase locked loop who compensate for phase delay by variation of temperature - Google Patents

Abstract

PURPOSE: A clock signal generator using a phase locked loop which compensates a phase delay due to temperature variation is provided, which is capable of generating a clock signal whose phase is not changed by a variation in temperature. CONSTITUTION: A clock signal generator using a phase locked loop which compensates a phase delay due to temperature variation includes a frequency/phase difference detector(12) for detecting frequency and phase differences between a temperature-corrected reference clock signal and a frequency-divided signal, a voltage-controlled oscillator(14) for generating an oscillating signal that oscillates having a frequency and phase corresponding to the differences, and a phase shifter(16) for shifting the oscillating signal into a plurality of phases to generate shifted signals, selecting one of the shifted signals to generate it as a clock signal and selecting one of the shifted signals to generates it as an input signal of a frequency divider(20). The clock signal generator also has the frequency divider for frequency-dividing the input signal to generate the frequency-divided signal, and a temperature compensating unit(10) for receiving an external reference clock signal without respect to temperature variation to delay it by the delay characteristic of the frequency divider according to the temperature characteristic and generating the delayed signal as the temperature-corrected reference clock signal.

Description

Clock signal generator using phase locked loop who compensate for phase delay by variation of temperature}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generator using a phase locked loop, and in particular, a phase synchronization for compensating for a phase delay caused by a temperature change to compensate for a change in the phase of a clock signal due to a delay characteristic caused by a temperature change. A clock signal generator using a loop.

For example, in order to accurately recover a video signal on an LCD monitor, it depends on how accurately an analog to digital converter (ADC) samples the input analog video signal. Sampling of the incoming analog video signal takes place on the rising or falling edge of the sampling clock. If this sampling edge is inconsistent and constantly changing due to external or internal factors, it will eventually sample the wrong analog input. There are many factors that influence this phase change, but the factor caused by temperature change is the most serious. For example, when the circuit is operated for a long time, the junction temperature of the chip increases, and the edge of the sampling clock signal of the ADC optimized at the beginning of the ADC is gradually stretched by the delay of the internal gates, thereby changing the phase. In other words, the ADC cannot sample the video signal at the correct sampling point due to the sampling clock signal whose phase is changed according to the temperature change. As a result, the image quality of the LCD monitor is significantly degraded.

As such, for accurate operation of all circuits that must operate in synchronization with clock signals independent of temperature changes, the clock signal generator compensates for temperature changes so that the phase of the clock signal does not change with temperature changes. very important.

The technical problem to be achieved by the present invention is to compensate for the delay characteristics of the temperature change, using a phase-locked loop to compensate for the phase delay caused by the temperature change that can generate a clock signal that does not change the phase of the clock signal according to the temperature change To provide a clock signal generator.

1 is a diagram illustrating an embodiment of a clock signal generator using a phase locked loop to compensate for a phase delay caused by temperature change according to the present invention.

2 (a) to 2 (c) are diagrams showing input / output waveform diagrams of respective units in the apparatus shown in FIG.

In order to achieve the above object, a clock signal generator using a phase-locked loop for compensating the phase delay caused by the temperature change according to the present invention is a frequency / phase difference detector for detecting the frequency and phase difference between the temperature-corrected reference clock signal and the divided signal A voltage controlled oscillator generating an oscillating signal having an oscillation signal having a frequency and phase corresponding to a frequency / phase difference generated by a phase difference detector, and generating shifted signals by shifting the oscillation signal into a plurality of phases, and corresponding to the phase control data One of the shifted signals is generated as a clock signal, and one of the shifted signals is generated as a divider input signal and has a predetermined delay characteristic according to the temperature change. Is dispensed at a predetermined rate to generate a frequency divider signal. The delay characteristic is the same as the frequency divider, and inputs a reference clock signal input from outside regardless of temperature change, delays the reference clock signal by the delay characteristic of the frequency divider according to the temperature characteristic, and converts the delayed signal into a temperature compensated reference clock. And a first temperature compensator which is generated as a signal.

Hereinafter, a clock signal generator using a phase locked loop for compensating a phase delay caused by a temperature change according to the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating an embodiment of a clock signal generator using a phase locked loop to compensate for a phase delay caused by temperature change according to the present invention. The clock signal generator using the phase locked loop according to the present invention includes a first temperature compensator 10, a frequency / phase difference detector 12, a voltage controlled oscillator 14, a phase shifter 16, and a multi clock signal generator 18. And a divider 20 and a second temperature compensator 22, and the clock signal generated by the multi-clock signal generator 18 is an analog-to-digital converter (ADC) 24. It is used as a sampling clock signal. That is, the clock signal generator using the phase locked loop shown in FIG. 1 is a sampling clock signal generator that generates a sampling clock signal for the ADC 24.

2 (a) to 2 (c) are diagrams showing input / output waveform diagrams of respective units in the apparatus shown in FIG. 1, and FIG. 2 (a) shows a video signal input to the ADC 24, and FIG. b) shows the oscillation signal Fv generated by the voltage controlled oscillator 14, and FIG. 2 (c) shows the clock signal CLK generated by the phase shifter 16. As shown in FIG. Here, the video signal shown in FIG. 2A represents a signal obtained by analog conversion of a digital video signal by a video card in a video signal processing process.

1 and 2, the frequency / phase difference detector 12 detects the frequency and phase difference between the temperature-corrected reference clock signal Fr_T and the divided signal Fv_d. The voltage controlled oscillator 14 is shown in FIG. 2 (b), having a frequency and phase corresponding to the frequency / phase difference generated by the frequency / phase difference detector 12 and oscillating with a duty cycle of 50%. The oscillation signal Fv is generated. The phase shifter 16 generates a signal shifted in phase of the oscillation signal Fv corresponding to the phase control data DATA. For example, the phase shifter 16 may generate 48 phase shifted signals from the oscillation signal Fv, and select one of the 48 phase shifted signals corresponding to the phase control data DATA to clock the signal. It occurs as a signal CK. In addition, one of the signals shifted in phase in step 48 is fixedly selected and output to the divider 20 as the divider input signal D_IN. That is, the phase shifter 16 is shown in FIG. 2C such that the falling (or rising) edge of the clock signal CK is located at the optimum sampling point P in response to the phase control data DATA. Likewise, the phase of the oscillation signal Fv is shifted.

The divider 20 has a predetermined delay characteristic according to temperature change, and divides the divider input signal D_IN generated by the phase shifter 16 at a predetermined rate to generate the divided signal Fv_D. The first temperature compensator 10 has the same delay characteristic according to the temperature change as the frequency divider 20 and inputs a reference clock signal Fr input from the outside regardless of the temperature change, and divides it according to the temperature characteristic. The reference clock signal Fr is delayed by the delay characteristic of 20, and the delayed signal is output to the frequency / phase difference generator 12 as the temperature corrected reference clock signal Fr_T.

As such, the frequency divider signal Fv_D input to the frequency / phase difference detector 12 by the frequency divider 20 which is sensitive to the temperature change delays the phase of the reference clock signal Fr as much as the temperature changes. Therefore, it is possible to compensate the phase delay delayed in the divider 20 by the temperature change.

On the other hand, the multi-clock signal generator 18 may be placed behind the phase shifter 16. The multi-clock signal generator 18 has a predetermined delay characteristic according to temperature change, variously adjusts the duty of the signal generated by the phase shifter 16, and adjusts the duty-adjusted signals to the clock signals CK1, CK2, and the like. CKn). That is, the signal generated by the phase shifter 16 has a duty cycle of 50% and is adjusted to the duty cycle required by the user or the system. The second temperature compensator 22 has the same delay characteristic according to the temperature change as the multi-clock signal generator 18 and is connected between the phase shifter 16 and the divider 20. The second temperature compensator 22 inputs the divider input signal D_IN generated by the phase shifter 16 to output the divider input signal D_IN as much as the delay characteristic of the multi-clock signal generator 18 according to the temperature characteristic. The delayed and delayed signal is output to the divider 20 as a temperature corrected divider input signal.

The ADC 24 inputs the video signal IN_A shown in Fig. 2A and at the falling (or rising) edge of the clock signal generated by the multi-clock signal generator 18 (or the phase shifter 16). The input video signal IN_A is sampled, and the sampled result is output to the output terminal OUT as a digital signal.

As a result, when a clock signal is generated using a phase locked loop, first and second parts having the same delay characteristics as those of the frequency divider 20 and the multi-clock signal generator 18 which are highly affected by temperature. The temperature compensators 10 and 22 can prevent the sampling clock signal for the ADC 24 from being phase-shifted with temperature. If the phase delay of the sampling clock signal according to the temperature change is not corrected, the ADC 24 fails to sample the video signal at the optimal sampling point P shown in FIG. 2 and the wrong signal at the unwanted point P '. Sampling may eventually cause a significant decrease in image quality.

In the above, the clock signal generator using a phase locked loop for compensating the phase delay caused by the temperature change according to the present invention has been described as an example. However, the clock signal generator operates in synchronization with the clock signal independent of the temperature change as well as the ADC. Applicable to clock signal generators for all circuits that must.

In addition, the present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, the clock signal generator using a phase locked loop that compensates for the phase delay caused by the temperature change according to the present invention has the same delay characteristic as the delay characteristic caused by the temperature change of the frequency divider and the multi-clock signal generator. The first and second temperature compensators have an effect of preventing the phase of the clock signal from being delayed by the divider and the multi-clock signal generator when the temperature changes.

Claims (2)

A frequency / phase difference detector for detecting a frequency and a phase difference between the temperature corrected reference clock signal and the divided signal; A voltage controlled oscillator for generating an oscillation signal oscillating with a frequency and a phase corresponding to a frequency / phase difference generated by the frequency / phase difference detector; Shifting the oscillation signal to a plurality of phases to generate shifted signals, selecting one of the shifted signals to generate a clock signal according to phase control data, and selecting one of the shifted signals to generate a shifted signal. A phase shifter generated as a periodic input signal; A divider having a predetermined delay characteristic according to temperature change and dividing the divider input signal at a predetermined rate to generate the divider signal; And The delay characteristic according to the temperature change is the same as the frequency divider, and inputs a reference clock signal input externally independent of the temperature change, delaying the reference clock signal by the delay characteristic of the frequency divider according to the temperature characteristic, And a first temperature compensator for generating a signal as the temperature corrected reference clock signal. The clock signal generator of claim 1, wherein the clock signal generator employs a phase locked loop for temperature compensation. A multi-clock signal generator having a predetermined delay characteristic according to a temperature change, adjusting the duty of the clock signal generated by the phase shifter to various duty, and generating the duty-adjusted signals as first to nth clock signals; And A delay characteristic according to a temperature change is the same as that of the multi clock signal generator, and is connected between the phase shifter and the divider, and the divider input signal is inputted so that the delay characteristic of the multi clock signal generator according to the temperature characteristic is equal to the delay characteristic. And a second temperature compensator for delaying the period input signal and outputting the delayed signal to the frequency divider as a temperature-corrected frequency divider input signal. Signal generator.