KR20010001585A - Method for driving Address Electrode in Plasma Display Panel &Apparatus therefor - Google Patents

Abstract

PURPOSE: A method and apparatus is provided to improve luminance of screen and prevent disconnection of or damage to an address driving circuit. CONSTITUTION: A method is characterized in that the rising time of the address pulse becomes short during the rising section of the address pulse being applied to an address electrode during an address period, and an electric potential of the address electrode is delayed by a resistance element and pulled down to a ground during a falling section of the address pulse. An apparatus comprises a shift register(161) for receiving video data in accordance with the control signal synchronized with a predetermined erase scanning pulse, and sequentially shifting the received data; a latch unit(163) of latching for a predetermined time the data output from the shift register; a switching unit(165) connected between a high voltage(Vh) and a ground(GND) and which generates an address pulse in response to the data output from the latch unit; and a delay unit(167) connected between a common contact of the switching unit and an address electrode(X1-Xn) and which controls the falling time of the pulse to be longer than the rising time of the pulse when the high voltage pulse of the address electrode is pulled down to the ground.

Description

Method for driving address electrode of plasma display panel and apparatus therefor {Method for driving Address Electrode in Plasma Display Panel & Apparatus therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display, which is one of flat panel displays, and specifically, delays a pull-down voltage of an address electrode at a falling time of a pulse applied to an address electrode of a panel during an address period. The present invention relates to a data driving method of a plasma display panel which prevents the wall charges in a cell from disappearing, and a device thereof.

For example, a variety of methods are known for the construction of a plasma display panel (hereinafter referred to as a 'PDP'). In order to achieve a thin shape, a discharge glass is enclosed around the front glass substrate and the rear glass substrate to accommodate discharge gas. It is often employed to construct an airtight container, and the front and rear glass substrates are usually made of low-cost soda-lime glass.

In a color PDP having a small number of display cells, a spacer is used to prevent error discharge or color penetration between adjacent cells, or to withstand pressure differences between panels and to define a distance between discharge electrodes. A partition wall is formed between the front and rear glass substrates, and the display cell is formed in a space surrounded by the partition wall and the front and rear glass substrates. Phosphor is coated on the inner surface of the display cell, and the phosphor generates visible light of each color by ultraviolet rays generated by the discharge.

In a color PDP having a fine number of display cells capable of displaying an image, a rectangular cell array in which cells and electrodes are easily formed is usually employed.

Discharge electrodes are arranged in a row and a column of the panel, and cells are formed at the intersections of the horizontal and vertical electrodes.

In the PDP, a discharge is obtained by adjusting a voltage applied between a horizontal electrode and a vertical electrode of a cell constituting a pixel, and the amount of discharged light is adjusted by changing the number of discharges in the cell.

1 is a diagram illustrating a plasma display panel and an X-side address driving circuit according to the prior art, and the drawings are shown for convenience, and in fact, the rows and columns of the Y-side scan electrode, the Z-side sustain electrode, and the X-side address electrode are shown in FIG. It is installed opposite to the same drawing.

As shown in the figure, scan electrodes Y1 to Ym and Z side sustain electrodes Z1 to Zm are formed on the vertical side of the panel 10, and address electrodes X1 to Zm on the horizontal side of the panel 10. As shown in FIG. Xn) is formed.

Cells 15 are formed in a space where the vertical scan electrodes Y1 to Ym and the sustain electrodes Z1 to Zm and the horizontal address electrodes X1 to Xn cross at right angles. In addition, the sustain electrodes Z1 to Zm on the vertical side receive a sustain pulse supplied from the Z-side sustain drive circuit 30, and the scan electrodes Y1 to Ym on the vertical side are independently separated for each electrode, and thus the Y-side. The scan driving circuit 20 is configured to receive an erase scan pulse, a sustain pulse, and a line erase pulse, and the address electrodes X1 to Xn on the horizontal side are configured to receive an X-side address driving circuit ( 40, 45, and an address pulse synchronized with the erase scan pulse.

The output terminal 41 of the X-side address driver circuit 40 is connected in series between the high voltage Vh and the ground GND, and the potentials of the address electrodes X1 to Xn are converted to high voltage according to the input address pulse P. The first switching element Q1 and the second switching element Q2 are pulled up to (Vh) or pulled down to ground (GND).

The X-side address driver circuits 40 and 45 receive the address data applied from the outside according to a predetermined control signal and receive the first switching element Q1 and the second switching element according to the predetermined address driving signal processed. Q2) is operated to apply the high voltage Vh for the address to the address electrodes X1 to Xn of the specific cell.

FIG. 2 is a waveform diagram illustrating voltage levels applied to unit electrodes of the X side to the Z side according to the address period of FIG. 1, and FIG. As a unit cell shown to explain the disappearance of the present invention, the following description is made with reference to FIG. 1.

In the address period, pulses as shown in FIG. 2 are applied to the address electrodes X1 to Xn, the scan electrodes Y1 to Ym, and the sustain electrodes Z1 to Zm. A high voltage is applied to the address electrode, and a low voltage is applied to the scan electrode. A high voltage of a pulse lower than that of the address electrode is applied to the sustain electrode.

For example, a voltage of 90 mA is applied to the address electrodes X1 to Xn, a voltage of -160 mA is applied to the scan electrodes Y1 to Ym, and a voltage of 25 mA is applied to the sustain electrodes Z1 to Zm, respectively. At the rising time (the point of time) of the pulses applied to the address electrode and the scan electrode, write discharge occurs, and at the time of the right time after that, wall charges are formed in the address X and the scan electrode Y in the cell as shown in FIG.

The X-side address driver circuit of the PDP according to the prior art described above has a voltage drop of the address electrodes X1 to Xn and a scan electrode Y1 to Xn at the time when the pulse applied to the address electrodes X1 to Xn falls. The voltage surge of Ym) may cause self erase discharge in the cell space 17. Therefore, the wall charges formed on the address electrode X and the scan electrode Y are combined with each other to form a wall. As a part of the electric charges disappears, the luminance (brightness) of the screen may be lowered due to the lack of wall charges in the subsequent sustain period.

In addition, by directly driving the address electrodes of the panel 10 from the output terminal 41 of the X-side address driver circuit 40, the rise and fall times of the address pulses are short, and the X-side address driver circuit when abnormal discharge occurs in the panel 10. The high voltage is induced toward the output terminal 41 of the 40 so that the first switching element Q1 and the second switching element Q2 in the driving circuit are short-circuited, and the rise and fall time of the address pulse is fast. Therefore, a lot of electromagnetic waves (EMi) are also generated, which has a detrimental effect on the human body. Since the fall time of the address pulse is short, wall charges formed on the address electrode and the scan electrode may be discharged again when the pulse falls, so that an error occurs during address discharge. Miswriting has always been a problem.

Accordingly, an object of the present invention is to have a constant slope for the time that the high voltage of the address electrode pulls down to the X-side address driver circuit at the time of falling pulses applied to the address electrode and the scan electrode of the panel during the address period. The discharge of the plasma display panel prevents the wall charge in the cell from disappearing and prevents the short circuit and damage of the switching element by preventing the current and voltage of the peak value generated when the high voltage of the address electrode is discharged to the ground. The present invention provides a method and an apparatus for driving an electrode.

1 is a diagram illustrating an X-side address driving circuit of a plasma display panel according to the related art.

FIG. 2 is a timing diagram illustrating voltage waveforms applied to unit electrodes of the X side to the Z side according to the address period of FIG. 1.

3 is a unit cell shown for explaining the disappearance of wall charges in the address period of FIG.

4 is a diagram illustrating a plasma display panel and an X-side address driving circuit according to the present invention;

FIG. 5 is a timing diagram illustrating voltage waveforms applied to unit electrodes of the X side to the Z side according to the address period of FIG. 4.

*** Explanation of symbols for the main parts of the drawing ***

100: plasma display panel 110: cell

120: Y side scan drive circuit 140: Z side sustain drive circuit

160, 170: X-side address driver circuit 161: shift register

163: latch portion 165: input / output switch portion

167: resistance means (delay means) Y1 to Ym: scan electrode

Z1 to Zm: sustain electrode X1 to Xn: address electrode

The address electrode driving method of the present invention for achieving the above object is, in the addressing method of the plasma display panel for applying the address pulse synchronized with the erase scan pulse of the scan electrode to the address electrode in accordance with the input image data :

(1) In the rising period of the address pulse applied to the address electrode during the address period, the rising time of the address pulse is shortened,

(2) In the falling section of the address pulse, the potential of the address electrode is delayed for a predetermined time due to the resistance element and pulled down to the ground, so that the fall time of the address pulse is controlled to be longer than the rising time.

In addition, the address electrode driving apparatus of the present invention for achieving the above object comprises: a shift register for receiving the image data in accordance with a control signal synchronized with a predetermined erase scan pulse, temporarily storing the image data, and then shifting them sequentially;

Storage means for latching data output from the shift register for a predetermined time;

A plurality of switching means connected between a high voltage and ground and generating an address pulse in response to data output from the storage means; And

When the high voltage pulse of the address electrode is pulled down to the ground after being connected between the common contact and the address electrode of the plurality of switching means, the switching means is applied to the address electrode a high voltage pulse for the address output through the common contact And delay means for adjusting the fall time of the pulse to be longer than the rise time of the pulse.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 is a diagram illustrating a plasma display panel and an X-side address driver circuit according to the present invention, including a panel 100 including a plurality of cells 110, a Y-side scan driver circuit 120, and a Z-side sustain driver circuit 140. And the X-side address driver circuits 160 and 170.

In the panel 100, scan electrodes Y1 to Ym, sustain electrodes Z1 to Zm, and address electrodes X1 to Xn are disposed on the upper and lower substrates, respectively. Cells 110 functioning as discharge spaces to which red, green, and blue phosphors are applied are formed.

That is, the scan electrodes Y1 to Ym and the sustain electrodes Z1 to Zm are formed on the upper substrate of the panel 100, and the address electrodes X1 to Xn are formed on the lower substrate of the panel 100, and the scan electrodes are formed on the lower substrate of the panel 100. The cells 110 are formed at a portion where (Y1 to Ym), the sustain electrodes Z1 to Zm, and the address electrodes X1 to Xn cross at right angles.

In addition, the Y-side scan driving circuit 120 generates an erase scan pulse used to scan the screen to the scan electrodes Y1 to Ym and line erase pulses to stop the discharge of the discharged cell 110. It is configured to apply to the scan electrodes Y1 to Ym at a time, and the Z-side sustain drive circuit 140 generates a sustain pulse for maintaining the discharge of the cell 110, and at the appropriate time, the sustain electrodes Z1 to Zm. And the X-side address driver circuits 160 and 170 receive and latch the data R, G, and B for screen configuration according to an external control signal, and then scan the Y-side in the address period. A write pulse, that is, an address pulse synchronized with the erase scan pulse of the drive circuit 120, is generated and applied to the address electrodes X1 to Xn.

The X-side address driver circuit 160 receives and temporarily stores image data according to a control signal (control) synchronized with a predetermined erase scan pulse, and then sequentially shifts the shift register 161 and a shift register. The latch unit 163 for latching the data output from the 161 for a predetermined time, and the high voltage Vh for the address in response to the data output from the latch unit 163 provided between the high voltage Vh and the ground GND. And an input / output switch unit 165 for alternately switching the ground voltage GND and the common contact of the input / output switch unit 165 and the address electrodes X1 to Xn to be output through the input / output switch unit 165. Resistance means 167 for applying a high voltage Vh for the address to the address electrodes X1 to Xn and pulling it down with a predetermined delay time when the high voltage of the address electrodes X1 to Xn is discharged to the ground voltage GND. Consisting of There.

In addition, the input / output switch unit 165 of the X-side address driver circuit 160 is connected in series between the high voltage Vh and the ground GND and responds in response to data pulses output from the latch unit 163. The resistance means 167 comprises a first switching element Q1 and a second switching element Q2 that pulls up the potential of X1 to Xn to a high voltage Vh or pulls down to a ground voltage GND. It consists of a forward diode (D) connected in series between the common contact of the first switching element (Q1) and the second switching element (Q2) and the address electrodes (X1 to Xn) and a resistor (R) connected in parallel to the forward diode. It is.

The X-side address driver circuit 160 configured as described above receives the image data R · G · B applied from the outside in accordance with a predetermined control signal (control) and input / output switch unit 165 according to the signal pulses processed. Of the first switching device Q1 is turned on and outputs the high voltage Vh output through the first switching device to the address electrodes X1 to Xn of the specific cell through the diode D, and then the address electrode. The high voltage (Vh) applied to (X1 to Xn) is pulled down to the ground (GND) through the current path of the resistance element R and the second switching element (Q2) of the X-side address driver circuit 160, The pull-down time is somewhat dependent on the size of the resistor, and the optimal resistance value can be selected to match the scan and sustain pulse timings.

As shown in the drawing, the vertical scan electrodes Y1 to Ym are independently separated for each electrode to receive erase scan pulses, sustain pulses, line erase pulses, and the like from the Y-side scan driver circuit 120. The sustain electrodes Z1 to Zm receive the sustain pulses supplied from the Z side sustain driver circuit 140, and the horizontal address electrodes X1 to Xn receive the screen configuration from the X side address driver circuits 160 and 170. Receive data for

If the specific cells X1, Y1, and Z1 are to be discharged, an address pulse is input from the X-side address driver circuit 160 to the address electrode X1, and an erase scan pulse is synchronized with the address pulse to scan electrodes ( When input to Y1), the voltage between the address electrode and the scan electrode becomes higher than the threshold voltage necessary to cause the discharge, and the cell discharge occurs.

FIG. 5 is a waveform diagram illustrating voltage levels applied to unit electrodes of the X side to the Z side according to the address period of FIG. 4. Referring to FIG. 4, FIG.

In the address period, the X-side address driver circuits 160 and 170, the Y-side scan driver circuit 120, and the Z-side sustain driver circuit 140 are the address electrode X, the scan electrode Y, and the sustain electrode Z, respectively. By generating and supplying pulses as shown in FIG. 5, a high voltage pulse is applied to the address electrode X, a low voltage pulse is applied to the scan electrode Y, and a high voltage pulse lower than the address electrode is applied to the sustain electrode. do.

For example, a voltage of 90 kV is applied to the address electrode X, a voltage of -160 kV is applied to the scan electrode Y, and a voltage of 25 kV is applied to the sustain electrode Z, respectively. At the point of time?, The voltage between the address electrode X and the scan electrode Y becomes equal to or higher than the threshold voltage necessary for causing the discharge, and a write discharge occurs immediately after that. At the point of time, wall charges are formed on each electrode in the cell.

Subsequently, at the voltage discharge point of the address electrode X and the scan electrode Y, the discharge point of the address electrode X is earlier than the discharge point of the scan electrode Y, and the resistor R Depending on the resistance value of) has a certain slope (기울 ~ ㉰) and gently discharge to the ground.

That is, as shown in FIG. 4, a diode D and a resistor R are disposed between the common output contact of the switch unit 165 and the address electrodes X1 to Xn at the output terminal of the X-side address driver circuit 160. When supplying the waveform to the 100, the high voltage Vh is supplied to the address electrode X1 through the current path of the first switching element Q1 and the diode D, and the high voltage Vh of the address electrode X1 is supplied. When pulled down to the ground (GND), the discharge time to the ground (GND) through the current path of the resistance element (R) and the second switching element (Q2), so the fall time of the pulse is long as shown in the waveforms Delayed with a constant slope over time.

In addition, when an abnormal discharge occurs in the panel 100, the diode D and the resistor R prevent the peak current and the peak voltage, so that the switching elements Q1 and Q2 of the output terminal 165 are not damaged and are lowered. Since the time is long, the problem of miswriting during address discharge can be prevented.

On the other hand, as a comparative example, in the conventional technique, the switching elements Q1 and Q2 located at the output terminal 41 of the X-side address driver circuit 40 drive the address electrodes X1 to Xn of the panel 10 directly. On the contrary, in the present invention, the address electrode is connected by connecting the diode D and the resistor R in parallel between the common contact of the switching elements Q1 and Q2 positioned at the output terminal 165 and the address electrodes X1 to Xn. Drive.

In the embodiment of the present invention, the input / output switch unit 165 and the resistance means 167 are shown only for a unit cell for convenience, and the X2 address electrode to the Xn address electrode are configured as the driving circuit as in the embodiment, and the resistance means is also provided. Although illustrated as a diode and a resistor, it is obvious that the present invention may be implemented by various modifications such as a buffer or a delay element by those skilled in the art.

Such modified embodiments should not be individually understood from the technical spirit or the prospect of the present invention, and such modified embodiments should fall within the claims appended to the present invention.

Therefore, in the present invention, by installing a diode and a resistor in parallel at the output terminal of the X-side address driving circuit, the waveform is supplied through the diode when supplying the waveform to the address electrode, and pulled down through the resistor when the high voltage of the address electrode is discharged to ground. As the fall time of the address electrode increases, the brightness of the screen can be improved by preventing the wall charges from disappearing due to unnecessary discharge of the cell.In the case of abnormal discharge in the panel, the diode and the resistor block the peak current and the peak voltage. This prevents short circuit or damage to the address driver circuit.

Claims (3)

In an addressing method of a plasma display panel in which an address pulse synchronized with an erase scan pulse of a scan electrode is applied to an address electrode according to input image data, and scans a corresponding cell: (1) In the rising period of the address pulse applied to the address electrode during the address period, the rising time of the address pulse is shortened, (2) In the falling section of the address pulse, the potential of the address electrode is delayed for a predetermined time due to the resistance element and pulled down to ground, so that the fall time of the address pulse is controlled to be longer than the rise time. Address electrode driving method. A shift register configured to receive image data according to a control signal synchronized with a predetermined erase scan pulse, temporarily store the image data, and to sequentially shift the image data; Storage means for latching data output from the shift register for a predetermined time; A plurality of switching means connected between a high voltage and ground and generating an address pulse in response to data output from the storage means; And When the high voltage pulse of the address electrode is pulled down to the ground after being connected between the common contact and the address electrode of the plurality of switching means, the switching means is applied to the address electrode a high voltage pulse for the address output through the common contact And delay means for adjusting the fall time of the pulse to be longer than the rise time of the pulse. The method of claim 2, The delay means, A diode connected in series with a current path between the common contact of the plurality of switching elements and the address electrode to apply a high voltage for an address to the address electrode; And And a resistance element connected in parallel to the diode and delaying the potential of the address electrode for a predetermined time and pulling down to a ground voltage.