KR20000066706A - Chaos multiple value obtaining method of digital data - Google Patents

Abstract

PURPOSE: A method for acquiring a chaos multi-value of a digital data is provided to use an AD converter as a quantizer in a loop of one dimensional chaos generation mapping circuit, the DA converter and a nonlinear AD converter. CONSTITUTION: A chaos multi-value acquirement method comprises steps of making a loop by connecting a DA converter and a nonlinear AD converter to one dimensional chaos generation mapping circuit, acquiring a digitally coded multi-value from outputs of the AD converter, sampling analog outputs of the one dimensional mapping circuit by using an external clock to determine an operating speed of IC cells acquiring the multi-value and constructing a nonlinear quantizer with the DA converter and the nonlinear AD converter. The nonlinear characteristics of the AD converter can be designed with a channel capacitance of a MOS transistor in the process of designing an IC mask of the AD converter. The AD converter can be varied with a resolution, in general from 6 bit to 16 bit.

Description

Chaos multi-value acquisition method of digital data {CHAOS MULTIPLE VALUE OBTAINING METHOD OF DIGITAL DATA}

The present invention relates to a method for acquiring chaotic multivalues of digital data.

Today, there is a limit to the development of computers that adopt binary, or two, binary values. The number of transistors per function is enormous, leaving little room for investment in not only improving computational power but also improving memory capacity.

Binary 32-bit CPUs calculate a combination of 2 ³² = 10 ⁹ in one unit. However, this unit is so small that the computational power is limited. The limitation of memory is that all information is represented in a bit string. In order to store 1 bit, 1 MOS transistor and 1 capacity are required for DRAM and 4 MOS transistor flip-flop for SRAM. As circuits are required, the number of elements is inevitably increased in proportion to the increase in information.

For example, suppose you have replaced a binary number with 64 digits and 64 64 hexadecimal cells. 64 ⁶⁴ = 4.0 × 10 ¹¹⁵ combinations can be calculated in one unit. It is also a memory cell of the same combination. This can dramatically improve your computing power and memory capacity.

Efforts to make two-valued (quad-number) have been attempted in semiconductor memory, which is mainly achieved by the Wahe Process technology, such as adjusting the voltage of MOS transistors by ion implantation. However, the reality is that the amount of 2 to 4 does not contribute much to the improvement of computer computing power and memory capacity.

In addition, in an integrated circuit cell in which a chaos-generated one-dimensional mapping circuit, a linear analog-to-digital converter, and a linear digital-to-analog converter are looped, a technique of stably acquiring multiple values in a linear quantizer has also been made. For example, if a 6-bit linear analog-to-digital converter and a 12-bit linear digital-to-analog converter are used, the quantizer will define 64 quantums, but the actual acquisition period is up to 20. However, compared to the number of elements constituting the cell, it is inevitably small.

Accordingly, the present invention has been made in view of the above-mentioned situation, and the chaotic value of digital code capable of acquiring a large value of stability with as few elements as possible in order to improve the computing power of a computer and increase the storage capacity. The purpose is to provide a method of acquisition. That is, it is an object of the present invention to obtain more values than the number of transistors constituting the cell.

The present invention is to solve the problem that the number of combinations calculated as compared to the number of elements constituting the cell as described above.

In other words, the computing unit of today's 32-bit binary central processing unit (CPU) is like an abacus with 32 beads in a row. Accordingly, in order to carry out the four arithmetic operations of the addition and subtraction system, it is inevitable to always raise and lower the number of digits. Therefore, in order to improve the computing power of the computer and increase the memory capacity, it is necessary to increase the vertical beads.

Humans have 10 fingers, and they use the decimal arithmetic rule. The abacus has one or five marbles and four or five marbles in a row. In an artificial computer, the larger the number of beads in a column, the more arithmetic that employs a larger radix.

In order to realize a large radix, that is, a large multivalue (multiple number) with an integrated circuit cell, it is not meaningful to increase the number of transistors in proportion.

The orbital stability of nonlinear circuits is ensured by performing nonlinear quantization as linearizing its propagation characteristics. The present invention relates to an integrated circuit cell in which the input / output transfer characteristics of a chaotic-generated one-dimensional mapping circuit, which is a nonlinear function, is changed back to nonlinearity and a linearized transfer characteristic is obtained.

It can also be said to stabilize the trajectory and to obtain multi-values by equalizing the distribution of the internal states of each sugar.

The present invention applies the following configuration.

The chaotic generation one-dimensional mapping circuit can be composed of six MOS transistors (three PMOS and three NMOS). Alternatively, three MOS transistors may be used. This is the circuit synthesis result of CMOS circuit which shows increasing and decreasing functions.

By measuring the static input and output propagation characteristics of the chaotic generating one-dimensional mapping circuit, it is possible to understand the chaotic dynamic pattern and to design the channel conductance which is the center of each MOS transistor.

The higher the state determination precision of the chaotic generation one-dimensional mapping circuit, the better. Although it is impossible to measure directly, empirically, it is assumed that the resolution accuracy of the output is 10 ^-8 V when V _DD = 5.0V.

The absence of an amplifier in the chaotic generation one-dimensional mapping circuit is important for maintaining high state determination accuracy. This is an integrated circuit configuration in which noise is not amplified.

A nonlinear analog-to-digital converter and a digital-to-analog converter are connected in a loop to a chaotic generating one-dimensional mapping circuit, and multiple values are obtained from the output of the analog-to-digital converter. The obtained injury is digitally coded. The digital code is contained in general purpose computer memory.

An analog-to-digital converter samples the analog output of the desired one-dimensional mapping circuit with an external clock (usually supplied by a computer). The sampling value is 1 s, which determines the operating speed of the integrated circuit cell that acquires the multivalue.

Nonlinear analog-to-digital converters and digital-to-analog converters make up nonlinear quantizers. The nonlinear propensity is given by the channel conductance of the MOS transistors during the integrated circuit mask design of the analog-to-digital converter.

The analog-to-digital converter design can be either sequential conversion type or sequential comparison type. The design method can be chosen according to the required resolution, and resolution is usually 6 to 16 bits.

A 6-bit quantizer has 2 ⁶ = 64 quantums, and a 16-bit quantizer has 2 ¹⁶ = 65536 quantums.

(Example)

In Table 1, the resolution of 6 to 16 bits is the quantization resolution of the nonlinear quantizer. The multivalued values are multivalued values that can be obtained in ideal cases at each resolution.

Relationship between nonlinear quantization resolution, obtainable multivalue, and number of elements making up a cell Resolution (bits) Hurt The number of elements 6 64 138 8 256 182 10 1024 226 12 4096 270 14 16384 314 16 65636 368

Ideal multivalue acquisition is simple at low resolution. In order to obtain ideal multi-value at high resolution, the precision of the quantization (boundary line) of the quantizer must be higher than that equivalent to the state determination precision.

In general, at low resolutions, the precision of the quantization of the quantizer cannot require a level of state determination precision. Even if the distinction between the two is ambiguous, an almost ideal injury can be obtained.

When designing the mask of an integrated circuit, the nonlinear propensity of the nonlinear analog-to-digital converter is given by the channel conductance of the MOS transistor, that is, the ratio W / L of the width and length of the channel. The microfabrication technology of the integrated circuit fabrication process has the characteristic that it can precisely impart the same propensity to MOS transistors of the same specification.

The number of elements in Table 1 is an example of the sum of the number of MOS transistors constituting the one-dimensional mapping circuit, the number of MOS transistors constituting the nonlinear analog / digital converter and the digital / analog converter. It is noteworthy that the number of MOS transistors constituting the one-dimensional mapping circuit is six and does not depend on the resolution of the quantizer. The number of MOS transistors constituting the quantizer increases when the resolution of the quantizer is improved, but the increase rate is small.

In Table 1, 138 MOS transistors are required to acquire 64 values with 6-bit analog / digital to digital / analog. In 8-bit analog / digital-digital / analog, 182 MOS transistors are sufficient to acquire 256 values. In other words, a larger value than the number of MOS transistors constituting the cell can be said.

If the resolution is 8 bits or more, the larger the resolution, the smaller the number of MOS transistors, and the larger the multivalue can be obtained. In order to obtain large multi-values with high resolution, a high-precision quantizer must be realized in an integrated circuit.

The integrated circuit cell according to the multi-value acquisition method of the present invention provides a much larger value (base) than the number of MOS transistors constituting. By using a plurality of these cells to form arithmetic operation circuits (ALUs), the computing power of digital computers can be dramatically improved.

Compared with general-purpose DRAMs and SRAMs that are line memories, integrated circuit cells by the multi-value acquisition method of the present invention are also multi-value memory cells that are much larger than the number of MOS transistors constituting. It is the underlying technology that contributes to improving digital computer skills.

Claims (1)

Stable multi-value acquisition with chaos-generated one-dimensional mapping circuit, analog / digital converter, and digital / analog converter in a loop A nonlinear analog-to-digital converter is adopted as a quantizer to output a stable multivalue and to obtain a multivalue having greater stability than the number of elements constituting a cell.