KR20000045349A - Method for fabricating mos field effect transistor - Google Patents
Method for fabricating mos field effect transistor Download PDFInfo
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- KR20000045349A KR20000045349A KR1019980061907A KR19980061907A KR20000045349A KR 20000045349 A KR20000045349 A KR 20000045349A KR 1019980061907 A KR1019980061907 A KR 1019980061907A KR 19980061907 A KR19980061907 A KR 19980061907A KR 20000045349 A KR20000045349 A KR 20000045349A
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- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000005669 field effect Effects 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000011229 interlayer Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 125000006850 spacer group Chemical group 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
- 238000007517 polishing process Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 4
- 239000010408 film Substances 0.000 claims 21
- 239000010409 thin film Substances 0.000 claims 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 13
- 238000005498 polishing Methods 0.000 abstract 2
- 238000002513 implantation Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자의 모스전계효과 트렌지스터(metal-oxide-silicon field effect transistor) 제조방법에 관한 것으로, 특히 소오스/드레인영역을 스택형으로 형성하고, 상기 소오스/드레인영역의 측벽에 절연막 스페이서를 형성하여 게이트 전극과 소오스/드레인영역이 오버랩되는 것을 방지하여 쇼트채널이펙트(short channel effect)에 의한 페일을 감소시켜 소자의 특성을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a metal-oxide-silicon field effect transistor of a semiconductor device. In particular, a source / drain region is formed in a stack, and an insulating layer spacer is formed on sidewalls of the source / drain region. The present invention relates to a method of preventing a gate electrode from overlapping with a source / drain region, thereby reducing fail due to a short channel effect, thereby improving device characteristics.
일반적으로, P형 또는 N형 반도체기판에 N 또는 P형 불순물로 형성되는 PN접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다.In general, a PN junction formed of an N or P-type impurity on a P-type or N-type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region.
따라서, 채널의 폭이 감소된 반도체소자에서는 확산영역으로 부터의 측면확산에 의한 쇼트채널이펙트를 방지하기 위하여 접합 깊이를 얕게 형성해야 한다.Therefore, in a semiconductor device having a reduced channel width, the junction depth must be shallow in order to prevent short channel effects due to side diffusion from the diffusion region.
종래기술에 따른 모스 전계효과 트랜지스터의 제조방법은 다음과 같다.A method of manufacturing a MOS field effect transistor according to the prior art is as follows.
먼저, 반도체기판 상부에 소자분리를 위한 소자분리절연막을 형성한 다음, 전 체표면 상부에 게이트 절연막 및 다결정실리콘층을 형성한다.First, a device isolation insulating film for device isolation is formed on the semiconductor substrate, and then a gate insulating film and a polysilicon layer are formed on the entire surface.
다음, 게이트 전극 마스크를 식각마스크로 사용하여 상기 다결정실리콘층 및 게이트 절연막을 식각하여 게이트 전극을 형성한다.Next, the polysilicon layer and the gate insulating layer are etched using a gate electrode mask as an etching mask to form a gate electrode.
그 다음, 상기 게이트 전극의 양측 반도체기판에 저농도의 불순물을 이온주입시켜 엘.디.디.(lightly doped drain, LDD)영역을 형성한다.Next, a low concentration of impurities are implanted into both semiconductor substrates of the gate electrode to form a lightly doped drain (LDD) region.
그리고, 전체표면 상부에 절연막을 형성한 다음, 전면식각하여 상기 게이트 전극의 측벽에 절연막 스페이서를 형성한다.Then, an insulating film is formed over the entire surface and then etched to form an insulating film spacer on the sidewall of the gate electrode.
그 후, 상기 절연막 스페이서의 양쪽 반도체기판에 고농도의 불순물을 이온주입하여 소오스/드레인영역을 형성하여 모스 전계효과 트랜지스터를 형성한다.Thereafter, a high concentration of impurities are implanted into both semiconductor substrates of the insulating film spacer to form a source / drain region to form a MOS field effect transistor.
상기와 같은 종래기술에 따른 반도체소자의 모스 전계효과 트렌지스터 제조방법은, 게이트 전극과 소오스/드레인영역의 가장자리가 중첩되는 부분에서 게이트 전극과 소오스/드레인전극의 전압차이에 의해서 공핍영역이 형성되어 강한 전기장이 발생되어 터널링(tunneling)현상이 유발되고 이로 인하여 GIDL(gate induced drain leakage)현상이 발생하고, 상기 소오스/드레인영역과 웰의 농도차이에 의해 공핍영역의 폭(delpetion width)이 증가하여 펀치쓰루(punchthrough)현상이 발생하며, 게이트 전극의 길이를 줄이는 방법을 사진공정에 의존하고 있으므로 현재 기술로는 0.15㎛ 이하로 조절하는 것이 어렵다. 또한 이때 채널 농도와 소오스/드레인영역의 농도차이에 의해 서피스 펀치쓰루(surface punchthrough)현상이 증가하는 문제점이 있다.In the method of manufacturing a MOS field effect transistor of a semiconductor device according to the related art, a depletion region is formed by a voltage difference between a gate electrode and a source / drain electrode at a portion where the edges of the gate electrode and the source / drain region overlap each other. An electric field is generated to cause tunneling, resulting in GIDL (gate induced drain leakage), and the depth of the depletion region increases due to the difference in concentration between the source / drain region and the well. Through-through occurs and the method of reducing the length of the gate electrode is dependent on the photographic process, so it is difficult to control the current technology to 0.15 μm or less. In addition, there is a problem in that surface punchthrough is increased due to a difference in channel concentration and a difference between source and drain regions.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 소오스/드레인전극을 스택형으로 형성하되, 그 상부 및 측벽에 절연막을 형성하고, 상기 소오스/드레인전극 사이에 게이트 전극을 형성하여 상기 소오스/드레인전극과 게이트 전극이 중첩되는 부분이 형성되지 않게 함으로써 쇼트채널에 의해 발생되는 페일을 감소시켜 소자의 특성 및 신뢰성을 향상시키는 반도체소자의 모스 전계효과 트렌지스터 제조방법을 제공하는데 그 목적이 있다.In order to solve the above-mentioned problems of the prior art, the source / drain electrodes are formed in a stack shape, an insulating film is formed on the upper and sidewalls thereof, and a gate electrode is formed between the source / drain electrodes to form the source / drain electrodes. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a MOS field effect transistor of a semiconductor device, in which a portion generated by a short channel is reduced by preventing overlapping of the drain electrode and the gate electrode, thereby improving device characteristics and reliability.
도 1a 내지도 1f 는 본 발명의 제1실시예에 따른 반도체소자의 모스 전계효과 트렌지스터 제조방법을 도시한 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a MOS field effect transistor of a semiconductor device according to a first embodiment of the present invention.
도 2a 내지 도 2g 는 본 발명의 제2실시예에 따른 반도체소자의 모스 전계효과 트렌지스터 제조방법을 도시한 단면도.2A to 2G are cross-sectional views illustrating a method of manufacturing a MOS field effect transistor of a semiconductor device according to a second embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11, 31 : 반도체기판 12, 32 : 소자분리절연막11, 31: semiconductor substrate 12, 32: device isolation insulating film
13, 37 : 층간절연막 14, 35 : 제1감광막 패턴13, 37: interlayer insulating film 14, 35: first photosensitive film pattern
15, 33 : 소오스/드레인용 도전층 16, 34 : 절연막15, 33: source / drain conductive layers 16, 34: insulating film
17, 38 : 제2감광막 패턴 18, 36 : 절연막 스페이서17, 38: second photosensitive film pattern 18, 36: insulating film spacer
19, 39 : 게이트 절연막 20, 40 : 게이트 전극용 도전층19, 39: gate insulating film 20, 40: conductive layer for gate electrode
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 모스 전계효과 트렌지스터 제조방법은,Method of manufacturing a MOS field effect transistor of a semiconductor device according to the present invention for achieving the above object,
소자분리절연막이 형성되어 있는 반도체기판 상부에 소오스/드레인영역으로 예정되는 부분을 노출시키는 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film overlying the semiconductor substrate on which the device isolation insulating film is formed, exposing a portion intended as a source / drain region;
전체표면 상부에 소오스/드레인용 도전층을 형성한 다음, 상기 소오스/드레인용 도전층을 평탄화시키는 제1화학적 기계적 연마공정과,A first chemical mechanical polishing process of forming a source / drain conductive layer on the entire surface, and then planarizing the source / drain conductive layer;
상기 소오스/드레인용 도전층 상부에 불순물을 이온주입하여 스택형 소오스/드레인전극을 형성하는 공정과,Forming a stacked source / drain electrode by ion implanting impurities on the source / drain conductive layer;
전체표면 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
게이트 전극으로 예정되는 부분을 노출시키는 게이트 전극 마스크를 식각마스크로 사용하여 상기 제2층간절연막과 제1층간절연막을 제거하여 상기 반도체기판을 노출시키는 공정과,Exposing the semiconductor substrate by removing the second interlayer insulating film and the first interlayer insulating film by using a gate electrode mask that exposes a predetermined portion as a gate electrode as an etching mask;
상기 노출된 반도체기판에 채널 Vt 임플란트공정을 실시한 다음, 상기 제2층간절연막과 스택형 소오스/드레인전극의 측벽에 절연막 스페이서를 형성한 후, 게이트 절연막을 형성하는 공정과,Performing a channel Vt implant process on the exposed semiconductor substrate, forming an insulating film spacer on sidewalls of the second interlayer insulating film and the stacked source / drain electrodes, and then forming a gate insulating film;
전체표면 상부에 게이트 전극용 도전층을 형성한 다음, 평탄화시켜 상기 스택형 소오스/드레인전극 사이를 매립하되, 상기 소오스/드레인전극과 중첩되지 않는 게이트 전극을 형성하는 제2화학적 기계적 연마공정을 포함하는 것을 제1특징으로 한다.A second chemical mechanical polishing process for forming a gate electrode conductive layer on the entire surface and then planarizing the gap between the stacked source / drain electrodes to form a gate electrode that does not overlap the source / drain electrodes Let it be a 1st characteristic to do.
또한, 이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 모스 전계효과 트렌지스터 제조방법은,In addition, the method of manufacturing a Mohs field effect transistor of a semiconductor device according to the present invention for achieving the above object,
소자분리절연막이 형성되어 있는 반도체기판 상부에 소오스/드레인용 도전층과 제1층간절연막의 적층구조를 형성하는 공정과,Forming a stacked structure of a source / drain conductive layer and a first interlayer insulating film on the semiconductor substrate on which the device isolation insulating film is formed;
소오스/드레인영역으로 예정되는 부분을 보호하는 소오스/드레인전극 마스크를 식각마스크로 상기 적층구조를 식각하여 스택형 소오스/드레인전극을 형성하는 공정과,Forming a stacked source / drain electrode by etching the stack structure using a source / drain electrode mask protecting a portion intended to be a source / drain region as an etch mask;
상기 스택형 소오스/드레인전극의 측벽에 절연막 스페이서를 형성한 다음, 상기 반도체기판에 채널 Vt 임플란트하는 공정과,Forming an insulating film spacer on sidewalls of the stacked source / drain electrodes and then implanting a channel Vt into the semiconductor substrate;
전체표면 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
게이트 전극으로 예정되는 부분을 노출시키는 게이트 전극 마스크를 식각마스크로 사용하여 상기 제2층간절연막을 제거하여 상기 반도체기판을 노출시킨 다음, 게이트 절연막을 형성하는 공정과,Exposing the semiconductor substrate by removing the second interlayer insulating film using a gate electrode mask that exposes a portion intended to be a gate electrode as an etching mask, and then forming a gate insulating film;
전체표면 상부에 게이트 전극용 도전층을 형성한 다음, 화학적 기계적 연마공정을 실시하여 상기 스택형 소오스/드레인전극 사이를 매립하되, 상기 스택형 소오스/드레인전극과 중첩되지 않는 게이트 전극을 형성하는 공정을 포함하는 것을 제2특징으로 한다.Forming a conductive layer for the gate electrode on the entire surface, and then performing a chemical mechanical polishing process to fill the gap between the stacked source / drain electrode, but to form a gate electrode that does not overlap with the stacked source / drain electrode It includes as a second feature.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1g 는 본 발명의 제1실시예에 따른 반도체소자의 모스 전계효과 트렌지스터 제조방법을 도시한 단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing a MOS field effect transistor of a semiconductor device according to a first embodiment of the present invention.
먼저, 반도체기판(11)에서 소자분리영역으로 예정되는 부분에 소자분리절연막(12)을 형성하고, 전체표면 상부에 제1층간절연막(13)을 형성한다.First, a device isolation insulating film 12 is formed on a portion of the semiconductor substrate 11 that is intended as a device isolation region, and a first interlayer insulating film 13 is formed over the entire surface.
다음, 상기 제1층간절연막(13) 상부에 소오스/드레인영역으로 예정되는 부분을 노출시키는 제1감광막 패턴(14)을 형성한다. (도 1a, 도 1b참조)Next, a first photoresist pattern 14 is formed on the first interlayer insulating layer 13 to expose a portion of the source / drain region. (See FIG. 1A, FIG. 1B)
그 다음, 상기 제1감광막 패턴(14)을 식각마스크로 사용하여 상기 제1층간절연막(13)을 식각하여 상기 반도체기판(11)을 노출시킨다.Next, the first interlayer insulating layer 13 is etched using the first photoresist pattern 14 as an etching mask to expose the semiconductor substrate 11.
다음, 전체표면 상부에 소오스/드레인용 도전층(15)을 형성한다. 상기 소오스/드레인용 도전층(15)은 다결정실리콘층을 사용하여 형성한다.Next, a source / drain conductive layer 15 is formed over the entire surface. The source / drain conductive layer 15 is formed using a polysilicon layer.
그 다음, 상기 소오스/드레인용 도전층(15)을 화학적 기계적 연마공정으로 평탄화시켜 소오스/드레인전극을 형성한다.Next, the source / drain conductive layer 15 is planarized by a chemical mechanical polishing process to form a source / drain electrode.
그 후, 상기 구조 전표면에 제2층간절연막(16)을 형성한 다음, 상기 제2층간절연막(16) 상부에 게이트 전극으로 예정되는 부분을 노출시키는 제2감광막 패턴(17)을 형성한다. (도 1d참조)Thereafter, a second interlayer insulating film 16 is formed on the entire surface of the structure, and then a second photoresist film pattern 17 is formed on the second interlayer insulating film 16 to expose a portion intended as a gate electrode. (See FIG. 1D)
다음, 상기 제2감광막 패턴(17)을 식각마스크로 사용하여 상기 제2층간절연막(16)과 제1층간절연막(13)을 식각하여 상기 반도체기판(11)을 노출시킨다.Next, the second interlayer dielectric layer 16 and the first interlayer dielectric layer 13 are etched using the second photoresist layer pattern 17 as an etching mask to expose the semiconductor substrate 11.
그 다음, 전체표면 상부에 절연막을 형성한 후, 전면식각공정을 실시하여 상기 제2층간절연막(16)과 스택형 소오스/드레인전극의 측벽에 절연막 스페이서(18)를 형성한다. 이때, 상기 절연막 스페이서(18)는 상기 스택형 소오스/드레인전극과 후속공정으로 형성될 게이트 전극이 중첩되지 않도록 하기 위하여 형성한다.Next, after the insulating film is formed over the entire surface, an entire surface etching process is performed to form the insulating film spacer 18 on the sidewalls of the second interlayer insulating film 16 and the stacked source / drain electrodes. In this case, the insulating layer spacer 18 is formed so that the stacked source / drain electrodes do not overlap with the gate electrode to be formed in a subsequent process.
그 후, 상기 반도체기판(11)에 보론(boron) 또는 인(phosphorous)을 도즈로 사용하여 채널 Vt 임플란트공정을 실시한다. (도 1e참조)Subsequently, a channel Vt implant process is performed using boron or phosphorous as a dose to the semiconductor substrate 11. (See FIG. 1E)
다음, 전체표면 상부에 게이트 전극용 도전층(20)을 형성한다. (도 1f참조)Next, the conductive layer 20 for the gate electrode is formed on the entire surface. (See FIG. 1F)
그 다음, 상기 게이트 전극용 도전층(20)을 화학적 기계적 연막공정으로 평탄화시켜 상기 스택형 소오스/드레인전극의 사이를 매립하는 게이트 전극을 형성한다. (도 1g참조)Next, the gate electrode conductive layer 20 is planarized by a chemical mechanical film forming process to form a gate electrode that fills the gap between the stacked source / drain electrodes. (See Figure 1g)
본 발명의 제2실시예에 대하여 살펴보면 다음과 같다.Looking at the second embodiment of the present invention.
도 2a 내지 도 2g 는 본 발명의 제2실시예에 따른 반도체소자의 모스 전계효과 트랜지스터의 제조방법을 도시한 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a MOS field effect transistor of a semiconductor device according to a second embodiment of the present invention.
먼저, 반도체기판(31)에서 소자분리영역으로 예정되는 부분에 소자분리절연막(32)을 형성하고, 전체표면 상부에 소오스/드레인용 도전층(33)과 제1층간절연막(34)의 적층구조를 형성한다.First, a device isolation insulating film 32 is formed on a portion of the semiconductor substrate 31 that is intended as a device isolation region, and the stacked structure of the source / drain conductive layer 33 and the first interlayer insulating film 34 is formed over the entire surface. To form.
다음, 상기 제1층간절연막(34) 상부에 소오스/드레인영역으로 예정되는 부분을 보호하는 제1감광막 패턴(35)을 형성한다. (도 2a, 도 2b참조)Next, a first photoresist layer pattern 35 is formed on the first interlayer insulating layer 34 to protect a portion of the source / drain region. (See FIG. 2A, FIG. 2B)
그 다음, 상기 제1감광막 패턴(35)을 식각마스크로 상기 적층구조를 식각하여 스택형 소오스/드레인전극을 형성하고, 상기 제1감광막 패턴(35)을 제거한다.Next, the stacked structure is etched using the first photoresist pattern 35 as an etch mask to form a stacked source / drain electrode, and the first photoresist pattern 35 is removed.
그 후, 상기 반도체기판(31)에 보론 또는 인을 도즈로 사용하여 채널 Vt 임플란트공정을 실시한다. (도 2c참조)Thereafter, the semiconductor substrate 31 is subjected to a channel Vt implant process using boron or phosphorus as a dose. (See FIG. 2C)
다음, 전체표면 상부에 절연막을 형성한 후 전면식각공정을 실시하여 상기 적층구조의 측벽에 절연막 스페이서(36)를 형성한다.Next, an insulating film is formed on the entire surface, and then an entire surface etching process is performed to form an insulating film spacer 36 on the sidewall of the stacked structure.
그 다음, 전체표면 상부에 상기 제1층간절연막(34)와 절연막 스페이서(36)와 식각선택비차이를 갖는 제2층간절연막(37)을 형성한다.Next, a second interlayer insulating film 37 having an etching selectivity difference between the first interlayer insulating film 34 and the insulating film spacer 36 is formed on the entire surface.
다음, 상기 제2층간절연막(37) 상부에 게이트 전극으로 예정되는 부분을 노출시키는 제2감광막 패턴(38)을 형성한다.Next, a second photoresist layer pattern 38 is formed on the second interlayer insulating layer 37 to expose a portion of the second interlayer insulating layer 37.
그 다음, 상기 제2감광막 패턴(38)을 식각마스크로 사용하여 상기 제2층간절연막(37)을 식각하여 상기 반도체기판(31)을 노출시킨 후, 상기 제2감광막 패턴(38)을 제거한 다음, 상기 노출된 반도체기판(31)에 게이트 절연막(39)을 형성한다. (도 2e참조)Next, the second interlayer insulating layer 37 is etched using the second photoresist pattern 38 as an etch mask to expose the semiconductor substrate 31, and then the second photoresist pattern 38 is removed. The gate insulating layer 39 is formed on the exposed semiconductor substrate 31. (See Figure 2E)
다음, 상기 구조 전표면에 게이트 전극용 도전층(40)을 형성한다.Next, the conductive layer 40 for the gate electrode is formed on the entire surface of the structure.
그 다음, 상기 게이트 전극용 도전층(40)을 화학적 기계적 연마공정으로 평탄화시켜 상기 스택형 소오스/드레인전극 사이를 매립시키는 게이트 전극을 형성한다. (도 2g참조)Next, the gate electrode conductive layer 40 is planarized by a chemical mechanical polishing process to form a gate electrode that fills the gap between the stacked source / drain electrodes. (See Fig. 2g)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 모스 전계효과 트렌지스터 제조방법은, 소오스/드레인전극을 스택형으로 형성하고, 상기 소오스/드레인전극의 측벽에 절연막 스페이서를 형성한 다음 상기 소오스/드레인전극 사이에 매립되는 게이트 전극을 형성하여 상기 소오스/드레인전극과 상기 게이트전극이 서로 중첩되지 않도록함으로써 쇼트채널에 의해 DIBL현상이 발생하는 것을 방지하고, 상기 소오스/드레인전극과 게이트 전극이 서로 중첩되어 발생하는 GIDL현상을 방지하며, 소오스전극과 드레인전극이 서로 떨어져 있으므로 펀치쓰루현상이 발생하지 않고, 유효 채널 길이가 감소되어 전류구동능력이 향상되어 소자의 고속화를 가능하고 그에 따른 소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing the MOS field effect transistor of the semiconductor device according to the present invention, the source / drain electrodes are formed in a stack, an insulating film spacer is formed on the sidewalls of the source / drain electrodes, and the source / drain electrodes are formed. By forming a gate electrode buried between the source / drain electrodes and the gate electrode so as not to overlap each other, the generation of the DIBL phenomenon by the short channel is prevented, and the source / drain electrode and the gate electrode overlap each other. It prevents the GIDL phenomenon, and because the source electrode and the drain electrode are separated from each other, the punch-through phenomenon does not occur, the effective channel length is reduced, and the current driving ability is improved, which enables the device to be speeded up, thereby improving the characteristics and reliability of the device. There is an advantage to improve.
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