KR20000038387A - Method for forming virtual path for pin test of fpga - Google Patents

Abstract

PURPOSE: A virtual path forming method is provided to reduce the number of sockets for a pin test and save the expenses by forming a virtual path between FPGA chips not connected to an interface socket. CONSTITUTION: An FPGA array(200) is constituted with plural FPGA chips(FPGA0, FPGA1, FPGA2, FPGA3, FPGA4, FPGA5). The FPGA chips and the host(100) are interconnected by the interface part(220). The interface part(220) is connected to the host(100) to transmit n data bits simultaneously. Connection paths(a, b, c, d, e) are formed between blocks mapped on the respective FPGA chips according to a design circuit downloaded from the host(100). The connection paths(a, d) of the respective connection paths are connected to pins(t1, t2) of the pins of the interface socket(220), respectively.

Description

How to create a virtual path for F.P.U pin test

The present invention relates to a virtual path forming method for an FPGA pin test, and more particularly, to test pins of FPGA chips constituting the FPGA emulation system, which is not connected to an interface socket connecting a host and the FPGA emulator system. The present invention relates to a method for forming a virtual path for a pin test of an FPGA that forms and routes a virtual path between FPGA chips.

Field Programmable Gate Array (FPGA), the basis of logic emulators for verifying designed circuits, can emulate complex logic designs at clock rates four to six times faster than high-speed software simulators. An FPGA-based emulator is a heterogeneous network of purpose-built processors, with each FPGA processor individually designed to run jointly with a partition of the entire simulated circuit. Such FPGA logic emulation systems have been developed for complex designs ranging from thousands to tens of thousands of gates. Indeed, the software for the system is considered the most complex component. Emulation systems have been developed to interconnect FPGAs in two-dimensional mesh and partial crossbar topologies. In addition, a structured approach for the connection has been developed. In addition to the above structural approach, another approach uses a combination of the nearest element and crossbar connection. The logical partition is actually wired to the FPGAs according to the partition placement.

A conventional FPGA logic emulation system 5 is shown in FIG. The FPGA logic emulation system 5 can be achieved by interconnecting an array of FPGAs according to a logic design. This array is wired directly to the host 2 capable of downloading the designed circuit and the destination system 8 for logic design. Memory element 6 may be connected to array 10 of FPGAs. The host can be a PC or a workstation.

An emulation example of the FPGA logic emulation system 5 having the above configuration is shown in FIG. 2. In FIG. 2, reference numeral 10 denotes a host and 20 denotes an FPGA array. The FPGA array 20 is composed of a plurality of FPGA chips (FPGA0, FPGA1, FPGA2, FPGA3, FPGA4, FPGA5). Each FPGA chip is placed in accordance with the logic design downloaded from the host 10. The FPGA chips and the host 10 are interconnected by an interface unit 22. The interface unit 22 is connected to the host 10 to simultaneously transmit n data bits.

After the placement is completed, a pin test is performed to check whether the pins of the respective FPGA chips operate normally. A conventional pin test method is shown in FIG. This is the result of the CAD tool used for conventional FPGA routing. That is, by the CAD tool, FPGA0 has a path b connected to FPGA1, and the FPGA1 has a path c connected to FPGA2. Apart from this, FPGA3 has a path a which is connected to the first pin t1 of the interface section 22. FPGA4 has a pass e connected to FPGA5. FPGA5 has a path d connected to the second pin t2 of the interface unit 22. The host 10 may directly test paths a and d directly connected to the pins t1 and t2 of the interface unit 22. However, b, c, and e that are not directly connected to the interface unit 22 cannot be tested using the CAD tool. Accordingly, test sockets TS1, TS2, TS3, and TS4 capable of testing pins of respective FPGA chips have been conventionally used. That is, FPGA chips that do not have a path directly connected to the pins t1 and t2 of the interface unit 22, for example, the pins of FPGA0, FPAG1, FPGA 2, and FPGA4 may be connected to the host 10. The sockets TS1, TS2, TS3, and TS4 were used to test whether they operate normally.

However, the conventional virtual path forming method for the FPGA pin test as described above has the following problems. Since 200 to 400 pins exist in each FPGA chip, the number of pins of the test sockets TS1, TS2, TS3, and TS4 must be equal to or greater than the number of pins of the FPGA to check all the pins. As a result, a test socket is expensive and time-consuming to test pins of each FPGA chip of an FPGA emulation array in which a plurality of FPGA chips are arranged. In other words, the overhead of the test socket is large.

Therefore, the present invention has been invented to solve the above-mentioned problems, and a first object of the present invention is to provide a virtual path forming method for FPGA pin test that can reduce the overhead of the test socket.

A second object of the present invention is to provide a virtual path forming method for FPGA pin test that can shorten the time for inspecting pins formed on a plurality of FPGA chips.

In order to achieve the above object, the method for forming a virtual path for FPGA pin test according to the present invention includes: finding an FPGA (D-FPGA) directly connected to an interface socket (ST1); Selecting one of the D-FPGAs (ST2); Searching for pins not used in a placement among the plurality of pins of the selected D-FPGA and selecting one of them (STP); Finding an FPGA (I-FPGA) not directly connected to the interface socket from the FPGA array (ST4); Selecting one of the I-FPGAs (ST5); Searching for pins not used in a placement among the selected I-FPGAs and selecting one of them (VP2) (ST6); Connecting a pin VP1 selected from the D-FPGA and a pin VP2 selected from the I-FPGA (ST7); And if the I-FPGA remains, the process proceeds to the ST2, and otherwise ends the virtual path formation (ST8).

1 is a block diagram of a conventional logic emulation system,

2 is a block diagram illustrating an FPGA emulation system according to a conventional routing method.

FIG. 3 is a diagram illustrating an example of using a test socket to test pins of FPGA chips of the FPGA emulation system of FIG. 2.

4 is a block diagram illustrating an FPGA emulation system in which a virtual path for pin test of an FPGA according to the present invention is formed, and

5 is a flowchart illustrating a method for forming a virtual path for pin test of an FPGA according to the present invention.

<Explanation of symbols for main parts of drawing>

100: host 200: FPGA emulation system

220: interface socket a-e: routing pass

, : Virtual Path

Hereinafter, a method of forming a virtual path for FPGA pin test according to the present invention will be described in detail with reference to FIGS. 4 and 5.

First, the FPGA chip array 200 is shown in FIG. In FIG. 4, reference numeral 100 is a host, and reference numeral 220 is an interface socket. The FPGA array 200 is composed of a plurality of FPGA chips (FPGA0, FPGA1, FPGA2, FPGA3, FPGA4, FPGA5). Each FPGA chip is placed according to the logic design downloaded from the host 100. The FPGA chips FPGA0, FPGA1, FPGA2, FPGA3, FPGA4, and FPGA5 and the host 100 are interconnected by the interface unit 220. The interface unit 220 is connected to the host 100 to simultaneously transmit n data bits. In the FPGA array 200, connection paths a, b, c, d, and e are formed between blocks mapped to respective FPGA chips according to a design circuit downloaded from the host 100. Connection paths a and d of the connection paths are connected to pins t1 and t2 of the pins of the interface socket 220, respectively.

When the placement is completed, as shown in FIG. 5, the virtual path forming method for FPGA pin test according to the present invention is performed. First, in order to form a virtual path for FPGA pin test, a step ST1 of finding an FPGA (D-FPGA) directly connected to the interface socket 220 is performed. If the D-FPGAs are found, a step ST2 of selecting one of the found D-FPGAs is performed. If one of the D-FPGAs is selected in the ST2 step, searching for unused pins in the placement among a plurality of pins held by the selected D-FPGA, and selecting one of the found pins VP1 (ST3) Perform. After the step ST3 is completed, a step (ST4) of searching for an FPGA (I-FPGA) that is not directly connected to the interface socket 220 from the FPGA array 200 is performed. When the step ST4 is completed, a step (ST5) of selecting the I-FPGA capable of forming the shortest access path with the D-FPGA selected in the step ST2 is performed among the found I-FPGAs. When the step ST5 is completed, searching for unused pins at the time of placement among the plurality of pins of the selected I-FPGA and selecting one of them (VP2) (ST6) are performed. When the step ST6 is completed, a step ST7 of connecting the pin VP1 selected from the D-FPGA and the pin VP2 selected from the I-FPGA in the ST6 step is performed. When the step ST7 is completed, one virtual path is generated. After the virtual path is generated, whether the I-FPGA chip which is not connected to the interface socket 220 or the pins of the D-FPGAs, which are not used in the placement, remains among the I-FPGAs detected in the step ST4. The checking step ST8 is performed. In step ST8, if there is a remaining I-FPGA chip, the process proceeds to step ST2 to select a new D-FPGA. However, in step ST8, if there is no remaining I-FPGA chip, virtual path formation is terminated.

The virtual paths formed in the above manner are shown in FIG. 4. FPGA chips having a connection path directly connected to the interface socket 220 are FPGA3 and FPGA5. These FPGA chips are classified as D-FPGAs. On the other hand, FPGA chips that do not have a connection path directly connected to the interface socket 220 are FPGA0, FPGA 1, FPGA2 and FPGA4. These FPGA chips are classified as I-FPGAs. A virtual path formed to test the pins of the I-FPGA chips is shown in FIG. 4. That is, an unused pin X of FPGA3 having a connection path a directly connected to pin t1 of the interface socket 220 and an unused pin of FPGA0 not connected to any pin of the interface socket 220. Virtual path between Y) Was formed. Similarly, an unused pin W of FPGA5 having a connection path d directly connected to pin t2 of the interface socket 220 and an unused pin of FPGA2 not connected to any pin of the interface socket 220. Z) virtual path between Was formed. Virtual paths formed as above And As a result, the I-FPGA chips may execute the pin test by the interface socket 220 without having a separate test socket.

Therefore, according to the method for forming the virtual path for FPGA pin test of the present invention as described above, the following effects can be obtained.

First, there is an effect of reducing the overhead of using a test socket by connecting an unused pin of the FPGA chip that is not directly connected to the interface socket and an unused pin of the FPGA chip that is directly connected to the interface socket.

Second, since the virtual path is formed to connect as many FPGA chips as possible, there is an effect of reducing the time required for using a separate test socket to check the pins of the plurality of FPGA chips.

As mentioned above, although this invention was demonstrated concretely by the above-mentioned Example, this invention is not limited to this, The deformation | transformation and improvement are possible within the range of common knowledge of a person skilled in the art.

Claims (1)

Finding an FPGA (D-FPGA) directly connected to the interface socket (ST1); Selecting one of the D-FPGAs (ST2); Searching for pins not used in a placement among the plurality of pins of the selected D-FPGA and selecting one of them (STP); Finding an FPGA (I-FPGA) not directly connected to the interface socket from the FPGA array (ST4); Selecting one of the I-FPGAs (ST5); Searching for pins not used in a placement among the selected I-FPGAs and selecting one of them (VP2) (ST6); Connecting a pin VP1 selected from the D-FPGA and a pin VP2 selected from the I-FPGA (ST7); And step ST2 if I-FPGA remains, or step ST8 otherwise terminating the virtual path formation.