KR20000035012A - Simplified cell search scheme for first and second stage - Google Patents

Abstract

PURPOSE: A wide band code division multiple access(WCDMA) is provided for a communication system and more particularly for a simplified cell search scheme for WCDMA. CONSTITUTION: A circuit for detecting a signal is designed with a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit (121) has N taps (142-146) arranged to produce a respective plurality of first tap signals from the input signal (111). A first logic circuit (130, 132, 134, 148) is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal (150) in response to the clock signal, the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps (150, 172-184) arranged to produce a respective plurality of second tap signals from the first output signal, wherein a ratio of N/M is no greater than four. A second logic circuit (186) is coupled to receive one of a true and a complement of each of the plurality of second tap signals. The second logic circuit produces a second output signal (188) in response to the one of a true and a complement of each of the plurality of second tap signals

Description

SIMPLE LIFEED CELL SEARCH SCHEME FOR FIRST AND SECOND STAGE}

FIELD OF THE INVENTION The present invention relates to wideband code division multiple access (WCDMA) for communication systems, and in particular to a simple cell search scheme for WCDMA.

Recent code division multiple access (CDMA) systems feature simultaneous transmission of different data signals over a common channel by assigning a single code to each signal. This single code matches the code of the selected receiver to determine the reception of the appropriate data signal. These other signals arrive at the receiver via multiple paths in response to ground clutter or unpredictable signal reflection. Another effect of these multiple data signals at the receiver is to cause apparent fading or a variety of received signal lengths. In general, this fading along multiple data paths can be reduced by spreading the transmitted energy over a wide bandwidth. This wide bandwidth greatly reduces fading compared to narrow bandwidth transmission modes such as frequency division multiple access (FDMA) or time division multiple access (TDMA).

Hereinafter, a next-generation bandwidth code division multiple access (WCDMA) communication system as disclosed in Spread-Spectrum Telephony with Accelerated Code Acquisition of US Patent Application No. 90 / 067,594, filed April 27, 1998, incorporated by reference It continues to emerge as a new standard. This WCDMA system is an interfering communication system having a pilot symbol that supports channel estimation techniques. These pilot symbols are transmitted as quadrature phase shift keyed (QPSK) known as data to receivers within a cell or range in a predetermined time frame. The frame may be delayed in discontinuous transmission (DTX) mode in the cell. In the case of voice traffic, transmission of user data occurs when the user speaks, but no data symbol transmission occurs when the user is silent. Likewise for packet data, user data can be sent only when the packet is ready to be silent. The frame includes not only pilot symbols but also other control symbols such as transmit power control (TPC) symbols and rate information (RI) symbols. These control symbols include multiple bits, known as chips, to distinguish from data bits. Therefore, the chip transmission time TC is equal to the symbol time rate T divided by the plurality of chips in the symbol N. The number of chips in a symbol is a diffusion coefficient.

WCDMA mobile communication systems must initially receive a signal from a remote base station to establish communication within the cell. However, initial reception is complicated by multiple unrelated signals from other base stations as well as from base stations intended for other mobile systems in the cell. In addition, the normal signal from each base station is modulated by a common scrambling code or long code that distinguishes it from neighboring base stations. The duration of these long codes typically prevents fast signal reception. Thus, the base station facilitates this initial reception by continuously transmitting a specific signal at 16 KSPS on the perch channel, in a manner very similar to a beacon. The perch channel format includes a frame with 16 time slots, each duration of 0.625 ms. Each time slot includes four common pilot symbols, four transport channel data symbols, and two search code symbols. These search code symbols include a first search code (FSC) symbol and a second search code (SSC) symbol transmitted in parallel. Since these search code symbols are not modulated by the long code, the mobile receiver does not need to observe each 512 long code for the duration of each code to receive the signal. On the other hand, spread modulation of the search code symbols of the perch channel is limited by 256 chip Gold sequences.

3A, a simplified block diagram of a conventional transmitter for transmitting first and second search codes is shown. Circuits 302 and 310 each generate a 256 cycle Hadamard sequence. Both sequences are modulated by a complement of 64 cycle Gold sequences and 3 cycle Gold sequences, generating 256 chip FSC symbols in parallel with 256 chip SSC symbols. The block diagram of FIG. 3B shows a conventional circuit for detecting the FSC symbol of FIG. 3A. The circuit receives an FSC symbol as an input signal on the read 311. The signal is periodically sampled by the serial register 321 in response to the clock signal. The circuit has 64 taps multiplexed on the pseudo noise (PN) signal to produce 64 output signals. Summer 348 sums these 64 output signals to generate a sequence of output signals at terminal 350. These output signals are loaded into the serial register 391. The signal samples from register taps 350-376 produce sample outputs that add up such that summer 386 generates a match signal MAT at read 388. In the zero time shift, the matching of the received FSC symbol and the chip of each of the gold PN sequences results in a high correlation of all 256 chips. However, any shift in the received chip of the FSC symbol for the Gold PN sequence would result in a very degraded correlation with a maximum peak of 70 chips. Thus, high correlation indicates matching or reception of FSC symbols from the base station.

The circuit shown in FIG. 3B has several problems compared to the ideal. First, a 64-chip accumulator requires 64 taps and 64 logic gates. Second, the logic gate generates 64 output signals to be combined by 64 input summers at the chip rate multiplexed by the oversampling rate. Thus, these circuit components require excess layout area and increase power consumption. The latter problem is particularly problematic in mobile communication systems.

These problems are solved by a first series circuit coupled to receive an input signal in response to a clock signal. The first series circuit has N taps arranged to generate each of the plurality of first tap signals from the input signal. The first logic circuit is coupled to receive a plurality of first tap signals, one of the N predetermined signals and a complement of the N predetermined signals. The first logic circuit generates a first output signal in response to a clock signal, a plurality of first tap signals, and a complement of one of the N predetermined signals and the N predetermined signals. The second series circuit is coupled to receive the first output signal. The second series circuit has M taps arranged to generate each of the plurality of second tap signals from the first output signal, where the N / M ratio is 4 or less. The second logic circuit is coupled to receive one of the true and complement of the plurality of second tap signals. The second logic circuit generates a second output signal in response to one of the odd and complement of each of the plurality of second tap signals.

The present invention provides a synchronization capability comparable to conventional circuits. Circuit complexity, including gate count and signal taps, as well as power consumption is greatly reduced.

1A is a simplified block diagram of a transmitter for transmitting first and second search codes according to a first embodiment of the present invention.

1B is a block diagram of a circuit for detecting the first search code of FIG. 1A according to the first embodiment of the present invention.

2A is a simplified block diagram of a transmitter for transmitting first and second search codes according to a second embodiment of the present invention.

FIG. 2B is a block diagram of a circuit for detecting the first search code of FIG. 2A according to a second embodiment of the present invention. FIG.

3A is a simplified block diagram of a conventional transmitter for transmitting first and second search codes.

3B is a block diagram of a conventional circuit for detecting the first search code of FIG. 3A.

4 is a correlation diagram of the detection circuit of FIG. 1B.

5 is a correlation diagram of the detection circuit of FIG. 2B;

6 is a correlation diagram of the detection circuit of FIG. 3B.

Fig. 7 is a correlation diagram comparing the sequences W, X, and Y of the present invention with the Lindner sequence Z.

8 is a block diagram illustrating another embodiment of a 16 symbol accumulator circuit used in the detection circuit of FIG. 2B.

<Explanation of symbols for main parts of drawing>

108: circuit

111: lead

121: serial register

130, 132, 134: XOR

131, 133, 135: output signal

142-146, 150, 172-182: tab

148: summer circuit

150: terminal

185: inverter

186: summer

191: serial register

1A is a simplified block diagram of a transmitter for transmitting first and second search codes in accordance with the present invention. Each of the circuits 102 and 110 generates a 256 cycle Hadamard sequence. Both sequences are selectively modulated by the radix or complement of the 32 cycle gold sequence Z. The radix or complement state of each 32-cycle gold sequence group represents a state such as (Z, -Z, -Z, Z, -Z, Z, Z, Z) in the gold sequence generator 108. In general, this is represented as a 256-bit sequence of M (8) groups of N (32) logic signals. Each of the exclusive OR circuits 112 and 104 modulates 256 cycle sequences in the reads 111 and 103, respectively, such that the 256 chip first search code (FSC) is in series with the 256 chip second search code (SSC) code. Generate a symbol. These FSC, SCC symbols are the coincidence signals sent by the base station to facilitate signal reception by the mobile remote station.

FIG. 1B is a block diagram of a detection circuit according to the present invention for detecting the FSC symbol of FIG. 1A. The circuit receives the FSC signal as the input signal IN on the lead 111. The signal is periodically sampled by the serial register 121 in response to the clock signal. The sample rate is preferably larger than the chip rate by oversampling rate n. The oversampling rate is preferably 2 and requires an acceptable tradeoff between accuracy, circuit complexity, and power consumption. Thus, serial register 121 has 31 * n stages for storing each successive sample of input signal IN. The serial register 121 has 32 (N) taps 142 to 146 for generating 32 respective parallel tap signals. N is 1 when each tap signal is separated by n stages or samples, and there is no oversampling. The logic circuit 32 including the 32 XOR circuits 130, 132, 134 receives the respective pseudo noise (PN) signals as well as the 32 respective tap signals, generating 32 output signals 131, 133, 135. Let's do it. This PN sequence matches the sequence sent from circuit 108, with a gold sequence being preferred. Summer circuit 148 receives the 32 output signals and sums them to generate a sequence of output signals at terminal 150 corresponding to oversampling rate n.

On read 150 these output signals are loaded into serial register 191. Serial register 191 includes 224 * n stages and 8 (M) taps 150, 172-182. Signal samples from the taps of the serial register 191 produce eight sample outputs in parallel. These eight sample output signals are selectively inverted to match the sequence inversion of the circuit 108 (FIG. 1A). For example, inverter 185 corresponds to the fifth inverted symbol in the sequence of circuit 108. Summer 186 receives the odd or complement of these tap signals and adds them to generate a coincidence signal MAT in read 188. The FSC symbol received in the zero time shift coincides with each chip of the gold PN sequence, so that all 256 chips have a high correlation. However, a shift in the received chip of the FSC symbol relative to the Gold PN sequence results in a very weak correlation with a maximum peak of 50 chips or less. Thus, high correlation indicates matching or reception of FSC symbols from the base station. The high and low correlations of the present invention are comparable to conventional detection circuits (FIG. 3B). However, the present invention clearly provides advantages by the simplicity of the circuitry and the corresponding power reduction. Embodiments of the present invention require 32 taps and 32 corresponding XOR circuits for the 32 chip accumulator circuit 120. In addition, summer circuit 148 sums only 32 signals to generate an output signal on read 150. In comparison, the conventional 64 chip accumulator shown in FIG. 3B requires 64 taps and 64 corresponding XOR circuits. The summer should sum 64 input signals. Thus, the present invention provides a substantial reduction in layout area, logic gates, and parasitic capacitances. Additional logic gates and corresponding parasitic capacitances consume more power than the present invention.

2A is a simplified block diagram of a transmitter for transmitting first and second search codes according to another embodiment of the present invention. Each of the circuits 202 and 210 generates a 256 cycle Hadamard sequence as described above. However, both sequences are selectively modulated by the radix or complement of the 16 cycle gold sequence Z. The radix or complement state of each 16 cycle gold sequence group is represented by (Z, Z, Z, -Z, Z, Z, -Z, -Z, Z, -Z, Z, -Z in the gold sequence generator circuit 208. , -Z, -Z, -Z, Z). In general, this is represented as a 256-bit sequence of M 16 groups of N 16 logic signals. The XOR circuits 212 and 204 modulate 256 cycle sequences in each of the reads 211 and 203, respectively, generating a 256 chip first search code (FSC) symbol in parallel with the 256 chip second search code (SCC) symbol. .

The detection circuit of FIG. 2B receives the FSC symbol from the transmitter of FIG. 2A as the input signal IN on the lead 211. The signal is periodically sampled at the oversampling rate n by the serial register 221 in response to the clock signal. Thus, serial register 221 has 16 (N) taps 242-246 that generate respective 16 parallel tap signals. Logic circuits comprising 16 XOR circuits 230, 232, 234 receive 16 respective pseudo noise (PN) signals as well as respective tap signals, generating 16 output signals 231, 233, 235. This PN sequence matches the sequence sent from the circuit 208, with a gold sequence being preferred. Summer circuit 248 receives the 16 output signals and sums them to generate a sequence of output signals at terminal 250 corresponding to oversampling rate n.

These output signals on read 20 are loaded into serial register 291. Serial register 291 includes 240 * n stages and 16 (M) taps 250, 272-280. Signal samples from the taps of the serial register 291 produce 16 sample outputs in parallel. These tap signals are optionally inverted as described above and then summed by summer circuit 282 to generate a coincidence signal MAT in read 288. The coincidence of each chip in the FSC symbol and the gold PN sequence received in the zero time shift represents the same high correlation of all 256 chips as in the embodiment of FIG. 1B (FIG. 5). In addition, rejection of other shifts received in the FSC symbol for the Gold PN sequence results in comparable degradation. This embodiment of the present invention provides further advantages such as the simplification of the circuit and the reduction of the corresponding power in the embodiment of FIG. 1B. This embodiment only requires 16 taps and 16 corresponding XOR circuits for the 16 chip accumulator circuit 220. In addition, summer circuit 248 only adds 16 signals to generate an output signal on read 250. Obvious features of the invention are shown in Table 1 as compared to the prior art circuit of FIG. 3B.

1b Fig 2b 3B (Prior Art) 32-chip accumulator 8-symbol accumulator 16-Chip Accumulator 16-symbol accumulator 64-chip accumulator 4-symbol accumulator Register Stage 31 * n 224 * n 15 * n 240 * n 63 * n 192 * n Register tab 32 8 16 16 64 4 XOR gate 32 0 16 0 64 0 Total length 32 8 16 16 64 4

The comparison of Table 1 shows that the embodiments of the present invention as well as the prior art have a relatively large number of register stages and corresponding delays as determined by the 256 Adama sequence. However, the embodiments of FIGS. 1B and 2B provide a clear reduction in register taps, XOR gates, and summer lengths. Reducing circuit complexity and corresponding power consumption is very useful in mobile communication systems where circuit complexity and power consumption are serious issues.

Although the present invention has been described in detail with reference to the preferred embodiments, it is obvious that it is only an example and is not intended to set a limit. For example, the detection circuit design does not have to correspond to the transmitter circuit design. The detection circuit of FIG. 2B can be used with the transmitter of FIG. 1A or 3A. When used with the transmitter of FIG. 1A, a 16 symbol accumulator circuit 290 can detect 8 symbols as half of 16 symbols, and two inverters, such as inverter 285, are applied to each tap pair corresponding to an inverted symbol. It may be necessary. As such, four adjacent taps of the detection circuit of FIG. 2B may detect one symbol from the transmitter of FIG. 3A. In each case, the PN sequence applied to the chip accumulator 220 may correspond to the appropriate portion of the transmitted sequence. In addition, the new concept of the present invention is not limited to the gold PN sequence, but may be extended to other sequences well known to those skilled in the art, such as Lindner sequences. Applicants have also found three other 16 cycle sequences, shown below, which are greatly advantageous in combination with other features of the present invention. These sequences W, X, and Y shown below are compared with Lindner sequences and Gold sequences in Table 2.

W = {-1, -1, 1, 1, 1, 1, 1, -1, 1, 1, -1, 1, -1, 1, -1, -1}

X = {1, 1, 1, 1, 1, -1, -1, 1, 1, -1, -1, 1, -1, 1, -1, -1}

Y = {1, 1, 1, 1, -1, -1, 1, 1, -1, 1, 1, -1, 1, -1, 1, -1}

correlation W X Y Lindner gold Side up 32 34 48 34 18 Average side 5.24 3.90 2.45 4.04 5.50

Referring now to FIG. 7 and Table 2, the sequences W, X, and Y are compared with the Lindner sequence. 7 represents the time shift in the chip from the ideal match. The vertical axis represents the correlation of symbols. Since the correlation of the exact match corresponding to the zero shift in the chip is omitted, the vertical scale may be adjacent to other time shift values. For example, the maximum side correlation of sequence X is 34, with an average side correlation of 3.90. This is slightly better than the average side correlation of 4.04 of the Lindner sequence with the same maximum side correlation. Alternatively, the mean side correlation of sequence Y (2.45) is much better than the Lindner sequence, but the maximum side correlation 48 is bad.

8, a block diagram of another embodiment of a 16 symbol accumulator circuit used with the detection circuit of FIG. 2B is shown. An accumulator circuit is coupled to receive a partial correlation signal on lead 250 from adder circuit 248 (FIG. 2B). Serial circuit 800 includes banks of registers 810-813 arranged to receive samples of each of the serial data, thereby receiving each sample of the serial data. Data from each register is applied to logic circuit 822 via bus 820. The PN code applied to the logic circuit 822 via the bus selectively inverts the data signal in a manner similar to the function of the inverter 285 (FIG. 2B). A summer receives each signal on bus 824 and adds it to the accumulated result on read 832. The result is stored in the accumulator-buffer circuit 830. The final result generates a coincidence signal MAT on read 834. Register accumulator circuits are very advantageous for efficiently processing serial data. It also provides programmable flexibility in register length and PN code selection. This series circuit can be used in place of the other series circuits described above. Serial circuits such as circuit buffers, addressable memories, shift registers, and digital signal processors can be applied to other embodiments of the present invention having access that is apparent to those skilled in the art.

It will be apparent to those skilled in the art that various modifications to the details of the embodiments of the invention are possible. Such changes and additional embodiments can be described as claimed below within the spirit and aspects of the invention.

TECHNICAL FIELD The present invention relates to wideband code division multiple access (WCDMA) for communication systems, and in particular to a simple cell search technique for WCDMA. In addition, the present invention provides synchronizing capability comparable to conventional circuits, thereby greatly reducing the complexity of the circuit including power consumption as well as gate count and signal taps.

Claims (37)

In a circuit for detecting a signal, A first circuit arranged to generate a first sequence of M groups, each group having N logic signals, each of the first plurality of M groups having a predetermined sequence, and a second plurality of M groups Each is one of the complement of the selected sequence; Second circuitry arranged to generate a second sequence of logic signals, the number of second sequences of logic signals being equal to the product of M and N; And Third circuitry coupled to receive first and second sequences, the third circuitry generating a match signal in response to the first and second sequences Circuit comprising a. 2. The circuit of claim 1 wherein the predetermined sequence of the first plurality of M groups is a gold sequence. 2. The circuit of claim 1 wherein the second sequence is a Hadamard sequence. 2. The circuit of claim 1 wherein M is 8 and N is 32. 2. The circuit of claim 1 wherein M is 16 and N is 16. 2. The circuit of claim 1, wherein the third circuit for generating a coincidence signal generates a logic XOR of each signal from the first sequence and each signal from the second sequence. The circuit of claim 1, wherein the coincidence signal is a first search code signal. 2. The circuit of claim 1 wherein each of the first and second circuits comprise a shift register. In a circuit for detecting a signal, A first series circuit coupled to receive an input signal in response to a clock signal, the first series circuit having N taps arranged to generate a plurality of first tap signals, respectively, from the input signal; A first logic circuit coupled to receive a plurality of first tap signals and one of the N predetermined signals and a complement of the N predetermined signals, wherein the first logic circuit is the clock signal, the plurality of first tap signals And generating a first output signal in response to one of the N predetermined signals and a complement of the N predetermined signals. A second series circuit coupled to receive the first output signal, the second series circuit having M taps arranged to generate the plurality of second tap signals, respectively, from the first output signal, where N / The proportion of M is 4 or less; And A second logic circuit coupled to receive one of the true or complement of each of the plurality of second tap signals, wherein the second logic circuit is in the odd and complement of each of the plurality of second tap signals Generates a second output signal in response to one Circuit comprising a. 10. The circuit of claim 9, wherein the input signal is a Hadamard sequence. 11. The circuit of claim 10 wherein the N predetermined signals are gold sequences. 10. The circuit of claim 9, wherein the N predetermined signals are one of a Lindner sequence, a W sequence, an X sequence, and a Y sequence. 10. The circuit of claim 9 wherein M is 8 and N is 32. 10. The circuit of claim 9 wherein M is 16 and N is 16. 10. The method of claim 9, wherein the second output signal is a match signal, the match signal having at least twice the value of the second output signal in response to a substantial match between the input signal and the N predetermined signals. Circuit. 16. The circuit of claim 15, wherein the coincidence signal corresponds to a first search channel signal. 17. The circuit of claim 16 wherein each of said first and second series circuits is a shift register. 18. The circuit of claim 17, wherein each of the first and second series circuits includes an integer multiple of n between each tap. 10. The circuit of claim 9, wherein the first logic circuit is A plurality of N logic gates coupled to receive N predetermined signals and a plurality of first tap signals, the plurality of N logic gates generating a plurality of N logic signals, respectively; And A first summer circuit coupled to receive the N logic signals to generate a first output signal Circuit further comprising a. 20. The circuit of claim 19, wherein the second logic circuit further comprises a second summer circuit coupled to receive one of the odd or complement of each of the plurality of second tap signals. In a circuit for detecting a signal, A first series circuit coupled to receive an input signal in response to a clock signal, the first series circuit having N taps arranged to generate each of the plurality of first tap signals from the input signal; A first logic circuit coupled to receive a plurality of first tap signals and N predetermined signals, the first logic circuit generating a first output signal in response to the plurality of first tap signals and the N predetermined signals -; A second series circuit coupled to receive a first output signal, the second series circuit being arranged to generate a first plurality of samples of the output signal and a sample of a complement of the second plurality of first output signals With M tabs; And A second logic circuit coupled to receive the first plurality of samples and the sample of the second plurality of complements, the second logic circuit responsive to a logical combination of the first plurality of samples and the sample of the second plurality of complements Generates a second output signal Circuit comprising a. 22. The circuit of claim 21 wherein the input signal is a Hadamard sequence. 22. The circuit of claim 21 wherein the N predetermined signals are gold sequences. 22. The circuit of claim 21 wherein the N predetermined signals are one of a Lindner sequence, a W sequence, an X sequence, and a Y sequence. 22. The circuit of claim 21 wherein M is 8 and N is 32. 22. The circuit of claim 21 wherein M is 16 and N is 16. 22. The method of claim 21, wherein the second output signal is a match signal, wherein the match signal has a value of at least twice the value of the second output signal in response to a substantial match between the input signal and the N predetermined signals. Characterized by a circuit. 28. The circuit of claim 27 wherein the match signal is responsive to a first search channel signal. 29. The circuit of claim 28 wherein each of said first and second series circuits is a shift register. 30. The circuit of claim 29, wherein each of the first and second series circuits further comprises an integer multiple of n stages between each tap. 22. The circuit of claim 21 wherein the first logic circuit is A plurality of N logic gates coupled to receive N predetermined signals and a plurality of first tap signals to generate a plurality of N logic signals; A first summer circuit coupled to receive the N logic signals to generate a first output signal Circuit further comprising a. 32. The circuit of claim 31 wherein the second logic circuit further comprises a second summer circuit coupled to receive one of the odd or complement of each of the plurality of second tap signals. A method for detecting a signal in a mobile communication system, Receiving an input signal from a remote transmitter; Sampling M groups of each N signals from an input signal in response to a clock signal; Comparing the N signals of each group, and the complement of the predetermined sequence of signals with one of the predetermined sequence of signals; Generating a plurality of M signals in response to the comparing step of each group; And Generating a coincidence signal in response to the plurality of M signals Method comprising a. 34. The method of claim 33, wherein said receiving comprises receiving an input signal having a Hadamard sequence. 34. The method of claim 33, wherein said sampling step Determining a plurality of input signal values at each cycle time in response to the clock signal; And Storing each value in a shift register Method further comprising a. 34. The method of claim 33, wherein said comparing step Generating N logical signals in response to each logical combination of the N predetermined signals and the N signals; Summing the N logic signals; And Generating one of the M signals in response to the summing step Method comprising a. 34. The method of claim 33, wherein generating the coincidence signal is Summing one of the odd and complement of each of the plurality of M signals; And Generating the coincidence signal in response to the summing step Method comprising a.