KR20000032079A - Low loss switching drive circuit of boosting type converter for controlling power factor - Google Patents

Abstract

PURPOSE: A low loss switching drive circuit of a boosting type converter for controlling power factor is provided to minimize switching loss of a switch and a diode by adapting a soft switching manner. CONSTITUTION: A low loss switching drive circuit of a boosting type converter for controlling power factor includes a rectifier(21) for rectifying commercial power into pulse power. The pulse power is regulated by an inductor(L). A soft switching part(22) performs a switching operation using switching elements(S1,Sa), a resonance inductor(Lr), and capacitors(Cr1,Cr2) according to current output from the inductor(L). According to switching states of the switching elements(S1,Sa), current flowing in the inductor(L) is detected by a current detector(24). An output voltage of the rectifier(21) is detected by an input voltage detector(25), and a voltage of a filter capacitor(C) is detected by an output voltage detector(26). A power factor controller(27) controls an output voltage for controlling the soft switching part(22). A switch driver(28) outputs a switching control signal according to the output voltage.

Description

Low Loss Switching Drive Circuit of Step-up Converter for Soft Switching Power Factor Control

The present invention relates to a low loss switching drive circuit of a soft switching power factor control step-up converter for preventing efficiency from falling due to loss due to reverse recovery characteristics of a diode during switching in the power factor control type converter. The present invention relates to a low loss switching driving circuit of a boost converter for soft switching power factor control to minimize switching losses of switches and diodes.

As shown in FIG. 1, the DC power supply circuit without the conventional power factor control function includes a rectifying unit 10 for rectifying an input commercial power and outputting the rectified DC voltage, and a DC output from the rectifying unit 10. It is composed of a filter capacitor (C) for filtering the voltage supplied to the load (12).

As shown in FIG. 3, the circuit configuration of the conventional power factor control boost converter includes a rectifying unit 10 for rectifying an input commercial power and outputting the rectified DC voltage, and outputting from the rectifying unit 10. Step-up converter section 11 for performing an operation for improving the power factor with respect to the voltage, and a filter capacitor (C) for filtering the voltage output from the step-up converter section 11 to supply to the load 12 ), A current detector 13 for detecting a current input to the load 12, an input voltage detector 14 for detecting a voltage input to the load, and an output voltage generated when the load 12 is operated. A power factor controller for outputting a switching signal for power factor control to the boost type converter unit 11 using an output voltage detector 15 for detecting a voltage and a current and voltage value detected through the detectors 13 to 15; 16).

Looking at the prior art configured in this way in detail as follows.

First, referring to the DC power supply circuit without the power factor control function based on FIG. 1 and FIG. 2, the commercial power and the commercial current as shown in (C) of FIG. I _AC ) Is supplied to the rectifier 10.

The rectifier 10 rectifies the input commercial power using a diode to make a DC voltage, and outputs the rectified DC voltage to the filter capacitor C.

At this time, the input current I _IN supplied to the filter capacitor C is as shown in FIG.

The filter capacitor C receiving the input current I _IN and the DC voltage as described above is filtered, and the filtered voltage, that is, the output voltage Vo as shown in FIG. ) To operate.

The power factor of a circuit operating as described above usually has a value between 0.4 and 0.7.

In addition, the harmonics component is so large that it cannot meet the international standard IEC 61000-3-2.

When the power factor is low, the effective power is also reduced, which reduces the power available in the home.

Therefore, a power factor control circuit is inserted to reduce power factor and harmonics.

Such a circuit is illustrated in FIG. 3, which is described below with reference to FIGS. 3 and 4.

When supplying commercial power to the rectifier 10, the rectifier 10 rectifies the input voltage and outputs the rectified voltage (V _IN ) to the boost converter 11, the rectified voltage (V _IN ) is A voltage with twice the frequency of the input supply frequency (50/60 Hz) comes out.

When this voltage (V _IN ) is input and output to the boost converter 11, a current in phase with the input voltage (V _IN ) flows through the inductor (L). The in-phase sine wave current flows and the power factor is nearly 1.0.

At this time, the output voltage Vo that is filtered through the diode D and the filter capacitor C and supplied to the load 12 becomes a voltage larger than the peak value of the input voltage V _IN .

When the output voltage Vo is detected by the output voltage detector 15 and output to the power factor controller 16, the power factor controller 16 controls the output voltage to operate stably.

The power factor controller 16 controls the current of the inductor L to follow the input voltage V _IN , which is an input voltage detected by the input voltage detector 14 and an input current detected by the current detector 13. Control by using.

Since the switch S1 operates at a high frequency of 20 KHz or more, the current of the inductor L serves as a current source during each switching.

When the switch S1 of the boost converter 11 is turned on by the power factor controller 16 by the operation as described above, the inductor L receives the voltage V _IN rectified through the rectifier 10, The current I _L rises linearly.

At this time, the current flowing through the switch S1 ( I _S ) Is bypassed to the (-) side through the conducting switch (S1), and gradually increases as shown in (a) of FIG. 4, and decreases inversely when the value is higher than the predetermined value. Current flowing into D) I _D ) Gradually decreases as shown in FIG. 4 (b) and increases inversely, and decreases when the value exceeds a predetermined value to maintain a zero value.

This phenomenon is called reverse recovery of diodes.

At this time, the filter capacitor C supplies the output voltage Vo to the load 12 to operate.

When the switch S1 of the boost converter 11 is turned off by the power factor controller 16, the diode D is turned on so that the inductor L receives the (Vo-V _IN ) voltage and the inductor current I _L. ) Decreases linearly.

In this case, power is supplied from the input to the output to charge the filter capacitor (C).

The switch ( S ₁ Current flowing through I _S ) Decreases as shown in (a) of FIG. 4 and the current flowing through the diode D ( I _D ) Gradually increases as shown in (b) of FIG. 4.

By repeating the same operation as above, the inductor current ( I _L Improve the power factor so as to follow the shape of the input voltage.

However, in the prior art as described above, there are many switching losses occurring in each element, and particularly in the diode D, the current in the opposite direction as shown in FIG. (I _D ) This reverse recovery current flows in the path of D → S1 → C, which greatly increases the loss of the switch S1 and the diode D. Therefore, this switching circuit has a very low efficiency, and in addition, there is a problem of using a large heat sink and a large airflow fan to dissipate these losses.

Accordingly, an object of the present invention for solving the conventional problems as described above is a low-loss switching of the boost converter for soft switching power factor control to minimize the switching losses of the switch and the diode in the boost converter for power factor control using a soft switching method. In providing a driving circuit.

1 is a DC power supply circuit diagram without a conventional power factor control.

FIG. 2 is a signal waveform diagram of an output voltage and an input current of FIG. 1. FIG.

3 is a circuit diagram of a conventional power factor-type boost converter.

4 is a voltage and current waveform diagram at the time of switching in FIG.

5 is a low loss switching driving circuit diagram of the boost converter for soft switching power factor control of the present invention.

FIG. 6 is a low loss switching scheme and switching state and current / voltage waveform diagram during one cycle in FIG. 5; FIG.

FIG. 7 is a first embodiment of the switch driver in FIG. 5; FIG.

FIG. 8 is a second embodiment of the switch driver in FIG. 5; FIG.

Fig. 9 is a signal waveform diagram of each part in Figs. 7 and 8;

*** Explanation of symbols for main parts of drawing ***

21: rectifier 22: soft switching unit

23: load 24: current detector

25: input voltage detector 26: output voltage detector

27: power factor control unit 28: switch drive unit

According to an aspect of the present invention, there is provided a power factor converter for a power factor control including an inductor, a soft switching unit, a current and voltage detector, a power factor control unit, and a switch driver, wherein the soft switching unit includes an antiparallel diode in a resonant inductor. In this case, the main switch having the main switch is connected in series, and the two diodes connected in series are connected in parallel, and the auxiliary resonance capacitor and the auxiliary switch are connected in parallel, respectively, and the connection point of the two diodes connected in series, the resonance inductor, and the main Auxiliary resonant capacitor is connected between the connection point of the switch is characterized in that configured.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 is a low-loss switching driving circuit diagram of the boost converter for soft switching power factor control according to the present invention. As shown in FIG. 5, the rectifier 21 rectifies the commercial power input to make a pulse current power having a double frequency of 50/60 Hz, and An inductor L for regulating the current input from the rectifier 21, two switching elements S1, Sa, a resonant inductor Lr, and a capacitor Cr1 for the current output through the inductor L; The soft switching unit 22 performs a soft switching operation using Cr2 and detects a current flowing through the inductor L according to the switching states of the two switching elements S1 and Sa. The current detector 24, the input voltage detector 25 for detecting the output voltage of the rectifier 21, the output voltage detector 26 for detecting the voltage of the filter capacitor C, and the soft switching unit ( To control 22) And a power factor controller 27 for outputting one output voltage, and a switch driver 28 for outputting a switching control signal in accordance with the output voltage.

In the soft switching unit 22, the main switch S1 having the antiparallel diode D1 is connected in series to the resonant inductor Lr, and the two diodes Da1 and Da2 connected in series are connected in parallel. In addition, the auxiliary resonance capacitor Cr1 and the auxiliary switch Sa are connected in parallel, respectively, and the connection points of the two diodes Da1 and Da2 connected in series, and the resonance inductor Lr and the main switch S1, respectively. Auxiliary resonant capacitor Cr2 is connected between the connection points.

As illustrated in FIG. 7, the switch driver 28 includes a pulse generator 281 that receives two signals a output from the power factor controller 27 and generates two pulses using a NAND gate. And an output buffer unit 282 capable of inverting the signal output from the pulse generator 281 and supplying sufficient current for driving the transistor, and a signal output from the output buffer unit 282. Accordingly, the gate pulse generator 283 generates gate pulses capable of driving two switches.

In addition, as shown in FIG. 8, the switch driver 28 receives the signal a output from the power factor control unit 27 and inverts the signal by using a sickle gate NOT7 and monostable multivibrator. (MM) inverts the pulse generator 281 'to adjust the pulse width, and outputs the NOT gate output and the monostable multivibrator (MM) output of the pulse generator 281'. An output buffer unit 282 'capable of supplying sufficient current for driving a transistor, and a gate generating gate pulses capable of driving two switches according to a signal output from the output buffer unit 282' And a pulse generator 283 '.

Referring to the operation and effect of the present invention configured as described in detail as follows.

First, assuming that each device is ideal, the initial state is the main switch (S1) and the auxiliary switch (Sa) of the soft switching unit 22 is turned off so that the current of the inductor (L) through the diode (D) filter capacitor It is the situation supplying to (C).

When the power factor controller 27 outputs a signal a for turning on the main switch S1 of the soft switching unit 22, the switch driver 28 outputs a switch control signal of a high state to the terminal Vg1. The low voltage switch control signal is output to the Vg2 terminal.

The operation of the switch driver 28 will be described later with reference to FIGS. 7 and 8.

Accordingly, as shown in FIG. 6A, the main switch S1 of the soft switching unit 22 is turned on and the auxiliary switch Sa is turned off.

As the main switch S1 is turned on, the resonant inductor Lr receives the output voltage Vo, and the resonant inductor current (i _Lr ) Increases linearly, as shown in FIG. 6 (b). (T0-t1 interval)

2 resonant inductor current (i _Lr ) Is the current in the inductor (L) (I _L ) If is equal to, the current flowing to the diode (D) (I _D ) 6 is zero, as shown in FIG. 6 (i), and the resonance of the auxiliary resonance capacitor Cr1 and Cr1? Lr? Falls to zero as in (t1-t2 section)

The voltage of the diode D rises from zero to the output voltage Vo as shown in FIG.

Resonant inductor current from t2 V _IN → Freewheeling to the path of L → Lr → S1 → Rs and the path of Da2 → Da1 → Lr → S1.

When the turn-on time of the main switch S1 of the soft switching unit 22 ends, the main switch S1 is turned off by the power factor controller 27 and the switch driver 28, and the auxiliary switch Sa is turned on. Let's do it.

When the auxiliary switch Sa is turned on, the resonant inductor current flowing through the resonant inductor Lr (i _Lr ) Is resonated through the pass of the resonant inductor (Lr) → auxiliary resonance capacitor (Cr2) → diode (Da1) and drops to zero as shown in FIG. 6 (b). (T3-t4 section)

2 resonant inductor current (i _Lr ) After is zero, this time, the resonant inductor (Lr) → auxiliary switch (Sa) → diode (Da2) → auxiliary resonant capacitor (Cr2) continues to resonate to pass the resonant inductor current (i _Lr ) Is increased by resonating in the opposite direction as shown in FIG. 6 (b) (t4-t5 section).

When the voltage of the auxiliary resonance capacitor Cr2 becomes zero in the section t5 as shown in FIG. 6 (c), the resonance inductor current (i _Lr ) Is continuously refluxed while the auxiliary switch Sa is turned on in the path of the resonant inductor Lr? Auxiliary switch Sa? Diode D1.

To minimize losses, this reflux period should be as short as possible.

In the t6 section, when the auxiliary switch Sa is turned off, the resonant inductor Lr → resonant capacitor Cr1 → diode D is resonated in the path of the auxiliary switch Sa, which is the voltage of the resonant capacitor Cr1. The voltage rises to the output voltage Vo as shown in FIG. 6 (d), and the voltage of the diode D drops to zero as shown in FIG. 6 (h).

When the voltage of the auxiliary switch Sa is equal to the output voltage Vo, the diode D conducts and the current of the inductor L (I _L ) To the load 23.

At this time, the output voltage Vo is applied to the resonant inductor Lr so that the resonant inductor current (i _Lr ) 6 decreases linearly to zero as shown in FIG.

Thereafter, this state is maintained until the signal for turning on the main switch S1 by the power factor controller 27 and the switch driver 28 again ends.

Loss can be minimized because soft switching is always performed at the time of switching of each switch, and the current flowing through the main switch S1 is almost the current of the inductor L compared to the conventional one. (I _L ) Since the on-loss can be minimized.

Then, the operation of the switch driver 28 will now be described based on FIG. 7. For example, if the power factor controller 27 outputs a high signal a as shown in FIG. A NAND ring is performed through the first NAND gate ND1 of the pulse generator 281 to output a low signal b as shown in FIG. 9B.

The low state signal b is a high state in which a low state signal obtained by NANDing through the second and third NAND gates ND2 and ND3 is sequentially inverted through the inverter of the output buffer unit 282, respectively. Signal e is generated to the gate pulse generator 283 through the resistor R1.

Accordingly, the transistor Q1 of the gate pulse generator 283 is turned on and the transistor Q2 is turned off.

Accordingly, the high state signal of the power supply voltage terminal Vcc generates a high state pulse to the Vg1 terminal through the transistor Q1 and the gate resistor 283A.

Similarly, the signal b in the low state output through the first NAND gate ND1 of the pulse generator 281 is input to the fourth NAND gate ND4 through the capacitor c and the variable resistor VR. do.

Then, the fourth NAND gate ND4 provides the signal c of the high state as shown in FIG. 9C to the output buffer unit 282.

Accordingly, the output buffer unit 282 outputs the low-state signal d as shown in FIG. 9 (d) through the inverter to the gate pulse generator 283 through the resistor R2.

The signal d in the low state through the resistor R2 turns off the transistor Q3 and turns on the transistor Q4.

As the transistor Q4 is turned on, a low pulse is output to the Vg2 terminal through the gate resistor 283B.

In the power factor controller 27, as shown in FIG. 9A, when the low state signal a is input, the pulse generator 281 passes through the second and third NAND gates ND2 and N3. The NAND signal of the high state is output, and the signal c of the low state is output as shown in FIG. 9C through the fourth NAND gate ND4.

In this way, the output signal outputs the inverted low (e) and high state signals (d), respectively, as shown in FIG. 9 (d) through the output buffer unit 282.

The signal thus output generates gate pulses of low and high states through Vg1 and Vg2 terminals of the gate pulse generator 283.

In this manner, when the capacitor C of the pulse generator 281 is fully charged, the low signal is input to one input terminal of the fourth NAND gate ND4. At this time, the signal of the high state is continuously input to the other input terminal.

Accordingly, as shown in FIG. 9 (c), which is NAND ringed through the fourth NAND gate ND4, the signal c becomes a high state, which is inverted through the inverter of the output buffer unit 282, and thus, FIG. It goes low as in.

At this time, the output signal of the point e through the output buffer unit 282 continues to be low as shown in FIG.

As a result, the signals e and d output through the output buffer unit 282 are respectively low.

The waveform at point d is a waveform for driving the auxiliary switch Sa, and the waveform at point e is a waveform for driving the main switch S1.

Another embodiment of the switch driver 28 will be described with reference to FIGS. 8 and 9. First, when the signal a having a high state as shown in FIG. 9 (a) is input to the pulse generator 281 ′. Inverted from the gate (NOT7), as shown in FIG. 9 (b), is provided to the input terminal (+ T) of the monostable multivibrator (MM).

Then, the monostable multivibrator MM changes the pulse width by the time constant of the resistor VR and the capacitor C and outputs the pulse width to the output buffer unit 282 '.

As a result, the monostable multivibrator MM adjusts the pulse width as shown in FIG. One pulse is outputted, and the other outputs the output of the natgate NOT7 as a pulse.

Accordingly, the two knock gates NOT8 and NOT9 (NOT10 and NOT11) of the output buffer unit 282 'invert two pulses output from the pulse generator 282', respectively, to prevent the pulses from being generated. Output the same pulse as in

The signal thus output is finally output through the Vg1 and Vg2 terminals of the gate pulse generator 283.

By the above operation, the switch control signal for controlling the soft switching unit 22 is generated and output by the switch driver 28 by the signal provided by the power factor controller 27.

Therefore, the present invention has the effect of softly switching the switches of the soft switching unit to reduce the switch loss, reduce the EMI problem, and to reduce the price by compactly configuring the entire system.

Claims (5)

Inductor (L) for adjusting the input current by receiving the output of the rectifier 21 for rectifying the commercial power, and the soft switching operation to receive the output through the inductor (L) to minimize the loss of the switch and diode A switching unit 22, a current detector 24 for detecting a current flowing through the inductor L according to the switching state of the two switching elements, and an input voltage detector 25 for detecting an output voltage of the rectifier 21. ), An output voltage detector 26 for detecting a voltage output to the load, and a power factor controller 27 for providing an output voltage for soft switching using the voltage and current provided from each of the detectors 24-26. And a switch driver configured to output a switching control signal for controlling the switch and the diode of the soft switching unit 22 according to the output voltage of the power factor control unit 27. In the type converter, the switch driver 28 receives a signal A output from the power factor controller 27 to generate two pulses, and a pulse generator 281 and an output from the pulse generator 281. An output buffer unit 282 capable of inverting a signal and supplying sufficient current to drive a transistor; and a gate pulse capable of driving two switches according to a signal output from the output buffer unit 282. Low-loss switching driving circuit of the step-up converter for soft switching power factor control, characterized in that consisting of a gate pulse generator (283) for generating a. 2. The pulse generator 281 according to claim 1, wherein the pulse generator 281 sequentially receives the first NAND gate ND1, which receives and outputs a signal provided from the power factor controller to two input terminals, and sequentially outputs an output signal of the first NAND gate ND1. Receive the output signals of the second and third NAND gates ND2 and ND3 and the first NAND gate ND1 to one side of the input terminal, and output the output signals to the capacitor C. A low-loss switching driving circuit of a boost converter for soft switching power factor control, characterized in that it comprises a fourth NAND gate (ND4) for accepting the other input terminal through a variable resistor (VR) to NAND to make another pulse. 2. The pulse generating unit 281 'according to claim 1, wherein the pulse generator 281' receives a sickle gate for inverting a signal provided by the power factor controller and an output of the sick gate, and adjusts a pulse width by a time constant of a resistor and a capacitor. A low loss switching drive circuit of a boost converter for soft switching power factor control, comprising a monostable multivibrator. The low loss of the step-up converter for soft switching power factor control according to claim 1, wherein the output buffer unit 282 'is configured to invert two pulses provided by the pulse generator into three natgates connected in parallel. Switching drive circuit. The low-loss switching of the boost converter for soft switching power factor control according to claim 1, wherein the output buffer unit 282 inverts the two pulses provided by the pulse generator into two knock gates connected in parallel. Driving circuit.