KR20000027908A - Method for manufacturing an embedded dram - Google Patents

Abstract

PURPOSE: A method is provided to connect memory circuits and logic circuits and to maintain a good surface flatness by changing a portion of a non-conductive metal oxide into a conductive material. CONSTITUTION: A semiconductor substrate(100) is provided with a memory circuit region(101) and a logic circuit region(102). A hydrogen treatment is carried out to change an exposed heat-resisting metal oxide(106) into an electrically conductive layer. A mask(117) is removed and a second conduction layer is formed on the heat-resisting metal oxide(106). The second conductive layer, the heat-resisting metal oxide(106), and a first conductive layer(115) are patterned to form lower and upper electrodes of a capacitor and a dielectric layer, and first and second contact mutual connection is formed to second and third openings(113, 114).

Description

METHOD OF MANUFACTURING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY

The present invention relates to a method of manufacturing a dynamic random access memory (DRAM), and more particularly, to a method of manufacturing an embedded DRAM.

Embedded DRAM is an integrated circuit (IC) in which DRAM circuits and logic circuits are coupled together in a semiconductor substrate. At present, the manufacturing trend of semiconductor integrated circuits is to integrate memory cell arrays and high speed logic circuit elements. For example, microprocessors or digital signal processors all have integrated circuits combined with embedded memory.

Nowadays, semiconductor manufacturers are trying to improve the device's functionality while maintaining or lowering production costs. By miniaturization and manufacturing of sub-micron semiconductor devices, the purpose of improving performance and reducing production costs has been partially met. Sub-micron technology can improve device performance because it can reduce device degradation and parasitic capacitance. Moreover, submicron technology produces smaller semiconductor chips. Since small chip functionality is similar to large chips, more silicon chips are fabricated on silicon wafers of a given size. Therefore, the average production cost of each chip is lower.

Other semiconductor manufacturers are integrating logic circuit elements and memory devices in semiconductor chips. This not only improves the performance of the device, but also has the advantage of reducing production costs. Integration improves performance by reducing the time delay of a signal transmitted from a memory element of one portion of a semiconductor chip to a logic element of another semiconductor chip to a logic element. In addition, by combining memory and logic elements on a single semiconductor chip, production costs can be lowered because most common process steps can be shared.

Attempts have been made by various semiconductor manufacturers to provide a method of integrating logic circuits and memories in one single chip. For example, in US Patent No. 5,292,677, Dennison et al. Proposed a method for manufacturing a complementary metal oxide semiconductor (CMOS) device and a DRAM device on a single semiconductor chip. However, in producing these two elements, the method does not share many manufacturing steps and thus does not significantly affect the production cost. In addition, the method does not include fabrication of high-efficiency logic devices.

In order to fabricate high-efficiency high-speed logic circuits and memory devices on a single semiconductor chip, many manufacturing aspects must be considered. Most often, considerations relate to logic circuit processes or memory circuits, and both views are rarely considered together.

As discussed above, there is a need for an improved method of integrating logic and memory circuitry on a single silicon chip.

The present invention has been proposed to solve the above-mentioned problems, and provides an embedded memory manufacturing method capable of increasing the number of process steps shared with the manufacture of high-efficiency, high-performance logic devices, and thus reducing the production cost. There is a purpose.

Another object of the present invention is to provide a method of manufacturing an embedded DRAM in which the upper surface of the memory device region and the upper surface of the logic circuit region have the same height, and thus can increase the degree of planarity of the integrated circuit. .

Another object of the present invention is to provide an improved method for manufacturing an embedded DRAM. In this method, a heat-resistant metal oxide film is deposited on the entire contact hole having a high aspect ratio. Next, the deposited heat-resistant metal oxide film is treated by hydrogen plasma or hot hydrogen in order to change the heat-resistant metal oxide film from electrical non-conductive to conductive.

It is another object of the present invention to provide a method of manufacturing an embedded DRAM. In this method, a heat-resistant metal oxide film is deposited on the entire contact hole having a high aspect ratio. Next, hydrogen plasma or hot hydrogen is used to treat a portion of the heat resistant metal oxide film deposited on the contact hole. Part of the heat resistant metal oxide film treated by hydrogen plasma or hot hydrogen is changed from electrical non-conductive to conductive. On the other hand, a part of the heat resistant metal oxide film not exposed to hydrogen plasma or hot hydrogen treatment remains non-conductive and can be used as a dielectric film of the DRAM capacitor.

1A through 1F are cross-sectional views sequentially showing steps of a method of manufacturing an embedded DRAM according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 101 memory circuit area

102: logic circuit area 103: transfer FET

104: first source / drain region 105: second source / drain region

106: first gate electrode 107: logic FET

108: third source / drain region 109: fourth source / drain region

110: second gate electrode 111: first insulating film

112: first opening 113: second opening

114: third opening 115: first conductive film

116: heat resistant metal oxide film 117, 119: mask film

118: second conductive film 120: capacitor

121: first contact interconnect 122: second contact interconnect

123: second insulating film 124: fourth opening

125: fifth opening 126: third conductive film

126a: first conductive line 126b, 126c: second conductive line

(Configuration)

According to the present invention for achieving the above object, in the method of manufacturing an embedded DRAM, a semiconductor substrate having a predefined memory circuit region and a logic circuit region is first prepared. Next, a plurality of transfer field effect transistors are formed in the memory circuit region, where each transfer field effect transistor has first and second source / drain regions and a first gate electrode. A plurality of logic field effect transistors are formed in the logic circuit region, each logic field effect transistor having a third and fourth source / drain regions and a second gate electrode.

After the first insulating film is formed over the semiconductor substrate, the first insulating film is exposed so that the first and second source / drain regions of each transfer field effect transistor are exposed to form a plurality of first and second openings in the memory circuit region. This is patterned. Similarly, a plurality of third openings are formed in the logic circuit region, and each third opening is formed such that at least one conductive film region in the logic circuit region is exposed.

Next, a first conductive film is formed over the entire first insulating film. The first conductive layer covers the first, second, and third openings, but does not completely fill the openings. Next, a heat resistant metal oxide film is formed over the entire first conductive film. A mask layer is formed over the heat resistant metal oxide layer, the mask layer is formed to cover at least the first opening and to expose at least the second opening and the third opening. Hydrogen treatment is performed to change the exposed heat-resistant metal oxide film into a conductive film. The mask layer is removed. Thereafter, a second conductive film is formed over the heat resistant metal oxide film. The second conductive film, the heat resistant metal oxide film, and the first conductive film are patterned. As a result, an upper electrode, a dielectric film, and a lower electrode of the capacitor are formed over each first opening, and first and second contact interconnects are formed over each of the second and third openings, respectively.

In a preferred embodiment of this method, the first conductive film can be patterned before formation of the heat resistant metal oxide film. In addition, the heat resistant metal oxide film may be patterned before the hydrogenation.

According to another invention for achieving the above object, in the method for manufacturing an embedded DRAM, first, a second insulating film is formed on the second conductive film. A plurality of fourth openings are formed in the second insulating film to expose the upper electrode of each capacitor, and a plurality of fifth openings in the second insulating film to expose a portion of the second conductive film electrically connected to the at least one other conductive film. An opening is formed. A third conductive film is formed to fill the fourth and fifth openings and cover the second insulating film. The third conductive film is patterned to connect to at least one conductive region, respectively, through the fifth opening, as well as a plurality of second conductive lines, respectively, as well as a reference voltage through the fourth opening and the upper electrode of the capacitor. A plurality of first conductive lines connected to the reference voltage are formed.

According to still another invention for achieving the above object, in the method of manufacturing an embedded DRAM, a semiconductor substrate in which a memory circuit region and a logic circuit region are already defined is prepared. At least one transfer field effect transistor is formed in a memory circuit region having a field effect transistor having first and second source / drain regions and a first gate electrode. At least one field effect transistor is formed in a logic circuit region having a logic field effect transistor having third and fourth source / drain regions and a second gate electrode.

After the first insulating film is formed over the semiconductor substrate, the first insulating film is patterned to form first openings and second openings in the memory circuit region where the first and second source / drain regions of the transfer field effect transistor are exposed. . Similarly, a third opening is formed in the logic circuit region that exposes at least one conductive region. A first conductive film is formed over the entire first insulating film. The first conductive film fills the first and second and third openings. A heat resistant metal oxide film is deposited on the entire first conductive film. A mask layer is formed over the heat-resistant metal oxide film to cover at least the first opening and to expose at least the second and third opening upper regions.

Hydrogen treatment is performed to change the heat resistant metal oxide film in the exposed conductive film. The mask layer is removed. Thereafter, a second conductive film is formed over the heat resistant metal oxide film. The second conductive film, the heat resistant metal oxide film, and the first conductive film are patterned. Finally, an upper electrode, a dielectric film, and a lower electrode of the capacitor are formed on top of the first opening, and first and second contact interconnects are formed on the second opening and the third opening, respectively.

In a preferred embodiment of this method, the method of manufacturing an embedded DRAM further includes the following steps. That is, a second insulating film is formed on the second conductive film. A fourth opening is formed in the second insulating film. A fourth opening is formed in the second insulating film to expose the upper electrode of the capacitor, and a fourth opening is formed in the second insulating film so that a portion of the second conductive film electrically connected to the at least one first conductive film is exposed. Next, a third conductive film is formed to fill the fourth and fifth openings and cover the second insulating film. The third conductive layer is patterned to form a first conductive line connected to the reference voltage through the fourth opening and the upper electrode of the capacitor as well as a second conductive line connected to the at least one conductive region through the fifth opening.

Both the foregoing general description and the following detailed description are examples and are intended to explain the claimed invention in more detail.

(Action)

Referring to FIG. 1B, in the novel embedded DRAM manufacturing method according to the embodiment of the present invention, a part of the heat-resistant metal oxide layer deposited on the contact hole through hydrogen plasma or hot hydrogen treatment is changed from non-conductive to conductive material. do. On the other hand, the portion of the heat resistant metal oxide film that has not been treated remains non-conductive. In this case, the unprocessed heat-resistant metal oxide film may be used as a dielectric film of the DRAM capacitor. This allows combining memory circuits and logic circuits together and reducing production costs while maintaining good surface flatness for silicon wafers.

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 1.

In the drawings and the description, the same reference numerals are used where possible for the same or similar parts.

Heat-resistant metal oxide films such as titanium oxide (TiO2), tantalum pentoxide (Ta2O5), ferrous oxide (Fe2O3), and barium titanium oxide (BaTiO3) Wide band-gap insulating material. If a hydrogen plasma treatment or hot hydrogen treatment is performed to inject hydrogen between the metal ions or hydrogen vacancy of the heat resistant metal oxide film, the oxygen content in the heat resistant metal oxide film is reduced. Therefore, the heat resistant metal oxide film will be replaced with an n-type conductive oxide film. In other words, the original heat-resistant metal oxide film will be converted from a material having insulating properties to a material having semiconductive or conductive properties. The reaction mechanism is summarized by the following equation.

[Scheme]

Since the electrical conductivity of the heat resistant metal oxide film after hydrogen plasma treatment or hot hydrogen treatment depends on its oxygen content, the heat resistant metal oxide film can be made of a semiconductor material or a conductive material. In addition, the resistance value when the heat-resistant metal oxide film is changed to the conductive material can be appropriately adjusted.

Methods related to the conversion of heat-resistant metal oxides into conductive materials can be found in many articles. These publications were written by Fu-Tai Liou (one of the inventors of the present invention) and include the publication "Semiconductor electrodes for photoelectrolysis" (New York State University, 1982). The second publication, written by C. Y. Yang et al., Was published under the heading "Solid electrochemical modification of semiconductors" (Solid State Communication, Vol. 43, No. 8, pp. 633-636). The third publication was also published by Fu-Tai Liou et al. Under the title "Photoelectrolysis at Fe2O3 / TiO2 Heterojunction Electrode" (Journal of the Electrochemical Society, Vol. 129, No. 2, pp. 342-245).

The present invention uses the techniques proposed in the above publications to improve the method of forming an embedded DRAM. The main feature of the present invention is that a heat-resistant metal oxide film is deposited on the entire contact hole having a high aspect ratio. The electrical conductivity of the heat resistant metal oxide film on the contact hole is changed from non-conductive to conductive using hydrogen plasma treatment or hot hydrogen treatment.

1A through 1F are cross-sectional views sequentially illustrating steps of a method of manufacturing an embedded DRAM according to an exemplary embodiment of the present invention.

First, as shown in FIG. 1A, a semiconductor substrate 100 is prepared. The semiconductor substrate 100 may be divided into a memory circuit region 101 and a logic circuit region 102. The memory circuit area 101 has at least one transfer field effect transistor (hereinafter referred to as a transfer FET) 103. The transfer FET 103 has first and second source / drain regions 104 and 105, and a first gate electrode 106. The logic circuit region 102 includes at least one logic field effect transistor (hereinafter referred to as a 'logic FET') 107. The logic FET 107 has third and fourth source / drain regions 108 and 109 and a second gate electrode 110. The first insulating layer 111 is formed on the entire surface of the semiconductor substrate 100. Next, to form the first opening 112 and the second opening 113 on the memory circuit region 101 and to form the third opening 114 on the logic circuit region 102. The insulating film 111 is patterned. First opening 112 and second opening 113 expose first and second source / drain regions 104 and 105 of the transfer FET, respectively. The third opening 114 exposes at least one conductive region in the logic circuit region 102.

The exposed conductive region may be one of a gate electrode or a source / drain region of the logic FET. For example, the third opening exposes the source / drain regions 108 shown in FIG. 1A. The first conductive layer 115 is formed on the entire surface of the first insulating layer 111. The first conductive layer 115 may be, for example, a metallic titanium layer, a metallic tungsten layer, a titanium nitride layer, or a titanium / titanium nitride layer. May be). The first conductive layer 115 covers each of the first, second, and third openings 112, 113, and 114. Next, a heat resistant metal oxide film 116 is formed on the entire surface of the first conductive film 115. Titanium oxide (TiO 2), tantalum pentoxide (Ta 2 O 5), peroxide oxide (Fe 2 O 3), and barium titanium oxide (BaTiO 3) may be used to form the heat resistant metal oxide layer 116. Here, the heat resistant metal oxide film 116 is still an insulating film.

The first conductive layer 115 may be patterned before the heat-resistant metal oxide layer 116 is formed on the entire surface of the first conductive layer 115. If the first conductive film 115 is patterned before deposition of the heat resistant metal oxide film, subsequent heat resistant metal oxide film deposition covers the edge of the first conductive film 115.

Next, referring to FIG. 1B, a mask layer 117 is formed over the heat resistant metal oxide layer 116. The mask layer 117 covers at least the first opening 112 and exposes the second opening 113 and the third opening 114, for example. It may be a (diffusion barrier layer). For example, after hydrogen treatment such as hydrogen plasma treatment or hot hydrogen treatment, the exposed heat-resistant metal oxide film 116 is changed into a conductive film. After the hydrogen treatment, the exposed portion of the heat resistant metal oxide film 116 is changed into the conductive heat resistant metal oxide film 116b, while the unexposed heat resistant metal oxide film 116a remains non-conductive. In addition, the heat resistant metal oxide layer 116 may be patterned before the hydrogen treatment is performed.

1C and 1D, the mask film 117 is removed. For example, a metal tungsten is formed on the entire surface of the heat-resistant metal oxide films 116 (116a and 116b). Another mask layer 119 is formed on the entire surface of the second conductive layer 118. The second conductive film 118, the heat resistant metal oxide film 116, and the first conductive film 115 are patterned using the mask film 119. As a result, the conductive film 118a, the non-conductive film 116a1, and the conductive film 115a are formed on the first opening 112. The conductive layer 118a, the non-conductive layer 116a1, and the conductive layer 115a become upper electrodes, dielectric layers, and lower electrodes of the capacitor 120, respectively. At the same time, a first contact interconnect 121 and a second contact interconnect 122 are formed on top of the second opening 113 and on top of the third opening 114, respectively. Is formed.

The first contact interconnect 121 includes a second conductive film 118b, a heat resistant metal oxide film 116b1, and a first conductive film 115b. The second contact interconnect 122 includes a second conductive film 118c, a heat resistant metal oxide film 116b2, and a first conductive film 115c. Finally, the mask layer 119 is removed.

In FIG. 1E, a second insulating film 123 is formed on the entire surface of the second conductive films 118 (118a, 118b, and 118c). Next, a fourth opening 124 is formed in the second insulating layer 123 to expose the upper electrode 118a of the capacitor. In the meantime, a fifth opening 125 is formed in the second insulating film 123 so that a part of the second conductive film 118, for example, the conductive film 118b or 118c is exposed.

Next, referring to FIG. 1F, a third conductive layer 126 is formed over the fourth and fifth openings 124 and 125 and the second insulating layer 123. The third conductive layer 126 may be, for example, an aluminum layer, a copper layer, or an aluminum-copper alloy. The first conductive line 126 may be patterned so that a reference voltage, for example, 1 / 2Vcc is supplied to the upper electrode 118a of the capacitor through the fourth opening 124. 126a) is formed. Similarly, second conductive lines 126b or 126c are formed through the fifth opening 125 to be connected to at least one conductive region, respectively.

The top surfaces of the top electrode and contact interconnects produced by the method described above have the same relative height. Thus, the memory circuit area and the logic circuit area also have the same relative height. As a result, the degree of planarity for integrated circuits is greatly increased.

Moreover, the present invention also provides a method of manufacturing an embedded DRAM by depositing a heat-resistant metal oxide film over a large aspect ratio contact hole. A portion of the heat resistant metal oxide film deposited on the contact hole through the hydrogen plasma or hot hydrogen treatment is changed from non-conductive to conductive material. On the other hand, the portion of the heat resistant metal oxide film that has not been treated remains non-conductive. Thus, the untreated heat resistant metal oxide film can be used as the dielectric film of the DRAM capacitor.

The present invention has the effect that the present invention can combine memory circuits and logic circuits together, thus reducing production costs while maintaining good surface flatness for silicon wafers.

Claims (30)

Preparing a substrate having a memory circuit region and a logic circuit region; The memory circuit region having a plurality of transfer FETs, each transfer FET comprising a first and a second source / drain region and a first gate electrode, the logic circuit region having a plurality of logic FETs, each The logic FET includes third and fourth source / drain regions and a second gate electrode, Forming a first insulating film on the entire surface of the semiconductor substrate; Patterning the first insulating film to form a plurality of first and second openings in the memory circuit region, and forming a plurality of third openings in the logic circuit region; Each of the first and second openings exposes respective first and second source / drain regions of the transfer FET, each third opening exposes at least one of the conductive regions in the logic circuit region, Forming a first conductive film on the first insulating film so as to cover the first, second, and third openings without filling the first opening; Forming a heat-resistant metal oxide film on the entire surface of the first conductive film; Forming a mask film on the heat resistant metal oxide film, covering at least the first opening and exposing at least the second opening and the third opening; Performing hydrogen treatment to change the exposed heat-resistant metal oxide film to be an electrically conductive film; Removing the mask layer; Forming a second conductive film on the heat resistant metal oxide film; And The second conductive film, the heat resistant metal oxide film, and the first conductive film are patterned to form a capacitor upper electrode, a dielectric film, and a lower electrode on the first opening, respectively, and a first on the second and third openings, respectively. And forming a second contact interconnect. The method of claim 1, The forming of the heat-resistant metal oxide film may include depositing one of oxide films selected from the group consisting of titanium oxide (TiO 2), tantalum pentoxide (Ta 2 O 5), ferros oxide (Fe 2 O 3), and barium titanium oxide (BaTiO 3). A method of manufacturing an embedded DRAM comprising the steps. The method of claim 1, The forming of the mask film may include depositing a diffusion barrier material to form a photoresist material or a diffusion barrier layer to form a photoresist film. DRAM manufacturing method. The method of claim 1, The hydrogen treatment step includes a hydrogen plasma treatment or hot hydrogen treatment. The method of claim 1, The forming of the first conductive layer may include depositing titanium or tungsten. The method of claim 1, The forming of the first conductive layer may include depositing titanium nitride. The method of claim 1, The forming of the first conductive layer may include depositing titanium and titanium nitride in order to insert a titanium film between the substrate and the titanium nitride film. The method of claim 1, The method of forming a second conductive film includes depositing tungsten. The method of claim 1, And sidewall edges of the capacitor upper electrode are aligned with the sidewall edge of the capacitor lower electrode. The method of claim 1, The method further comprises patterning a first conductive film before forming the heat resistant metal oxide film. The method of claim 1, The method further comprises patterning a heat resistant metal oxide film prior to performing the hydrogen treatment. The method of claim 1, After patterning the second conductive film, the heat resistant metal oxide film, and the first conductive film, forming a second insulating film on the second conductive film; Forming a plurality of fourth openings in the second insulating film to expose the upper electrodes of the capacitors, and forming a plurality of fifth openings in the second insulating film so that a portion of the second conductive film connected to the at least one conductive region is exposed. step; Forming a third conductive film on an entire surface of the fourth opening, the fifth opening, and the second insulating film; And A plurality of first conductive lines for supplying a reference voltage to the upper electrode of each capacitor through the fourth opening, and at least one conductive region through the fifth opening, respectively; And patterning the third conductive film to form a plurality of second conductive lines. The method of claim 12, And the reference voltage comprises a 1/2 Vcc voltage. The method of claim 12, The forming of the third conductive film may include depositing aluminum, copper, or an aluminum-copper alloy. The method of claim 1, And wherein the conductive region represents a third or fourth source / drain region of the logic FET, or a second gate electrode. Preparing a semiconductor substrate having a memory circuit region and a logic circuit region; The memory circuit region has at least one transfer FET, the transfer FET comprises first and second source / drain regions and a first gate electrode, the logic circuit region having at least one logic FET, and the logic FET A third and fourth source / drain regions and a second gate electrode, Forming a first insulating film on the entire surface of the semiconductor substrate; Patterning the first insulating film to form first and second openings in the memory circuit region, and forming a third opening in the logic circuit region; Each of the first and second openings exposes respective first and second source / drain regions of the transfer FET, each third opening exposes at least one of the conductive regions in the logic circuit region, Forming a first conductive film on the first insulating film so as to cover the first, second, and third openings without filling the first opening; Forming a heat-resistant metal oxide film on the entire surface of the first conductive film; Forming a mask film on the heat resistant metal oxide film, covering at least the first opening and exposing at least the second opening and the third opening; Performing a hydrogen treatment to change the exposed heat-resistant metal oxide film to be an electrically conductive film; Removing the mask layer; Forming a second conductive film on the heat resistant metal oxide film; And The second conductive film, the heat resistant metal oxide film, and the first conductive film are patterned to form a capacitor upper electrode, a dielectric film, and a lower electrode on each of the first openings, and a first on the second and third openings, respectively. And forming a second contact interconnect. The method of claim 16, The forming of the heat-resistant metal oxide film may include depositing one of oxide films selected from the group consisting of titanium oxide (TiO 2), tantalum pentoxide (Ta 2 O 5), ferros oxide (Fe 2 O 3), and barium titanium oxide (BaTiO 3). A method of manufacturing an embedded DRAM comprising the steps. The method of claim 16, Forming a mask film includes depositing a diffusion barrier material to form a photoresist material or a barrier film to form a photoresist film. The method of claim 16, The performing of the hydrogen treatment is a step performed using hydrogen plasma treatment or hot hydrogen treatment. The method of claim 16, The forming of the first conductive layer may include depositing titanium or tungsten. The method of claim 16, The forming of the first conductive film may include depositing a titanium nitride film. The method of claim 16, The forming of the first conductive film may further include depositing titanium and titanium nitride in order to insert a titanium film between the semiconductor substrate and the titanium nitride film. The method of claim 16, The forming of the second conductive layer may include depositing tungsten. The method of claim 16, And the sidewall edge of the capacitor upper electrode is aligned with the sidewall edge of the capacitor lower electrode. The method of claim 16, The method further comprises patterning the first conductive film prior to forming the heat resistant metal oxide film. The method of claim 16, The method further comprises patterning a heat resistant metal oxide film and a heat resistant metal oxide film before performing the hydrogen treatment. The method of claim 16, The patterning of the second conductive film, the heat resistant metal oxide film, and the first conductive film includes: forming a second insulating film on the second conductive film; Forming a fourth opening in the second insulating film to expose the upper electrode of the capacitor, and forming a fifth opening in the second insulating film to expose a portion of the second conductive film connected to the at least one conductive region; Forming a third conductive film on an entire surface of the fourth opening, the fifth opening, and the second insulating film; And A third conductive line for supplying a reference voltage to the upper electrode of each capacitor through the fourth opening, and a second conductive line respectively connected to at least one conductive region through the fifth opening; A method for manufacturing an embedded DRAM comprising patterning a conductive film. The method of claim 27, The reference voltage is a manufacturing method of the embedded DRAM including a 1/2 Vcc voltage. The method of claim 27, The forming of the third conductive layer may include depositing aluminum, copper, or an aluminum-copper alloy. The method of claim 16, And wherein the conductive region represents a third or fourth source / drain region of the logic FET, or a second gate electrode.