KR20000023048A - Semiconductor integrated circuit and Method of testing the same - Google Patents

Abstract

PURPOSE: A semiconductor integrated circuit and a test method thereof are provided to separately test an operation of a digital circuit by inputting a test signal through a first external input terminal. CONSTITUTION: A digital circuit(C1) receives digital signals inputted from digital circuit input terminals(I0,I1,...,In), performs a decoding and a storage of digital signals, and outputs parallel digital signals(G0,G1,..,G7) with 8 bits in the time determined by a clock signal(CLK). An analog circuit(C2) receives parallel digital signals(G0,G1,..,G7) with 8 bits outputted from the digital circuit(C1), converts the received parallel digital signals(G0,G1,..,G7) into analog signals, and outputs analog signals through an analog circuit output terminal(P0). The analog circuit(C2) has an analog signal processing unit(D0) for converting parallel digital signals(G0,G1,..,G7) into analog signals and outputs analog signals in the time determined by the clock signal(CLK) and a parallel/serial converting block(D1) for converting parallel digital signals(G0,G1,..,G7) into serial digital signals according to an enable signal(CVEN) and the clocks signal(CLK).

Description

Semiconductor integrated circuit and method of testing the same

The present invention generally relates to a semiconductor integrated circuit and a test method for inspecting the semiconductor integrated circuit. More specifically, it relates to a semiconductor integrated circuit in which analog circuits and digital circuits are integrated and analog circuits, digital circuits, and connections between them can be easily and accurately inspected.

Recently, with the improvement of semiconductor integrated circuit technology, semiconductor integrated circuits in which analog and digital circuits are integrated in one chip or device have been realized. For example, it is required to sample an analog signal such as a video signal or an audio signal on a time axis, convert the sampled value into a digital value, and convert it into a digital signal that can be processed by a digital signal processor such as a CPU. The above-described integrated circuit, in which the analog circuit and the digital circuit are integrated, can be preferably used to perform the above functions. In this case, the analog circuit performs the above-described sampling, and the digital circuit converts the sampled value into a digital value by performing encoding or the like. In other cases, the encoded digital signal is decoded by the digital circuit, and the signal decoded by the analog circuit is converted into an analog signal such as an original video signal or an audio signal. In this way, by integrating the analog circuit and the digital circuit, a semiconductor integrated circuit having multifunction, high micronization, and high integration is realized.

In the semiconductor integrated circuit described above, analog circuits and digital circuits are often electrically connected to each other to form one integrated circuit. Therefore, when testing a semiconductor integrated circuit to detect a defect likely to occur in such a semiconductor integrated circuit, a wiring path for clearly checking in which circuit part the defect is present or connecting an analog circuit and a digital circuit. It is difficult or impossible to clearly check whether a defect is present.

As a result, in the conventional semiconductor integrated circuit, it is necessary to cut the internal wiring or the wirings partially to inspect the analog circuit and the digital circuit separately. Therefore, the inspection work becomes very complicated and time consuming. In addition, in such an inspection method, it was impossible to inspect a defect in the wiring path connecting the analog circuit and the digital circuit. Therefore, in order to inspect the wiring route, it is necessary to observe the wiring route optically, for example, using a microscope or the like, and it is difficult to inspect the wiring route electrically.

Accordingly, an object of the present invention is to solve the above-mentioned problems of the conventional semiconductor integrated circuit in which an analog circuit and a digital circuit are integrated therein.

It is still another object of the present invention to provide a semiconductor integrated circuit having an analog circuit and a digital circuit integrated therein, the analog circuit and the digital circuit being inspectable respectively, and the wiring path connecting the analog circuit and the digital circuit also inspectable. Is in.

It is still another object of the present invention to provide a semiconductor integrated circuit having an analog circuit and a digital circuit integrated therein, each of which can be electrically inspected by an analog circuit, a digital circuit, and a wiring path connecting the analog circuit and the digital circuit. .

It is still another object of the present invention to provide a semiconductor integrated circuit having an analog circuit and a digital circuit integrated therein, wherein the analog circuit, the digital circuit, and the wiring path connecting the analog circuit and the digital circuit can be easily and clearly inspected, respectively. It is in doing it.

1 is a block circuit diagram showing a structure of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a table showing the relationship between the states of the mode switching signal and the operation modes in the semiconductor integrated circuit according to the first embodiment of the present invention.

3 is a waveform diagram illustrating signal waveforms of various circuit nodes in a normal operation mode in a semiconductor integrated circuit according to a first exemplary embodiment of the present invention.

4 is a waveform diagram illustrating signal waveforms of various circuit nodes in an analog circuit individual test mode in the semiconductor integrated circuit according to the first exemplary embodiment of the present invention.

5 is a waveform diagram illustrating signal waveforms of various circuit nodes in a simulation mode in a semiconductor integrated circuit according to a first exemplary embodiment of the present invention.

6 is a waveform diagram illustrating signal waveforms of various circuit nodes in a test terminal connection confirmation mode in the semiconductor integrated circuit according to the first embodiment of the present invention.

7 is a block circuit diagram illustrating a structure of a semiconductor integrated circuit according to a second embodiment of the present invention.

8 is a table showing a relationship between states of mode switching signals and operating modes in the semiconductor integrated circuit according to the second embodiment of the present invention.

9 is a waveform diagram illustrating signal waveforms of various circuit nodes in a normal operation mode and an analog circuit individual test mode in a semiconductor integrated circuit according to a second exemplary embodiment of the present invention.

FIG. 10 is a waveform diagram illustrating signal waveforms of various circuit nodes in a simulation mode in a semiconductor integrated circuit according to a second exemplary embodiment of the present invention.

FIG. 11 is a waveform diagram illustrating signal waveforms of various circuit nodes in a digital macro test mode in a semiconductor integrated circuit according to a second exemplary embodiment of the present invention.

※ Explanation of symbols for main parts of drawing

C0, H0: Semiconductor integrated circuit C1, H2: Digital circuit

C2, H1: Analog Circuit D0, LO: Analog Signal Processing Unit

D1: P / S conversion block I0, I1, In: Digital circuit input terminal

S0, S1, MS0, MS1: Mode switching signal CLK, MCLK: Clock signal

CVEN: Enable signal P0: Analog circuit output terminal

TI1 ~ TI7, DA0 ~ DA7: External input terminal F0 ~ F8, J0 ~ J15: Selector

TO1 ~ TO7, DB0 ~ DB7: External output terminal L1: S / P conversion block

NO: Analog input terminal CVDN: Conversion enable signal

RO0 ~ RO3, ROn: Digital circuit output terminal

According to one aspect of the invention, there is provided a semiconductor integrated circuit in which an analog circuit and a digital circuit are integrated therein, and a signal output from one of the analog circuit and the digital circuit is input to the other of the analog circuit and the digital circuit. The semiconductor integrated circuit selects one of a signal output from one of the analog circuit and the digital circuit or a signal input from the first external terminal in response to the mode switching signal, and converts the selected signal to the other of the analog circuit and the digital circuit. It has a 1st selector part which inputs.

In the above-described semiconductor integrated circuit, the output signal of the digital circuit is input to the analog circuit, the first selector unit is configured to select the signal output from the digital circuit or the signal input from the external terminal, so that the selected signal is input to the analog circuit. Can be. Here, the semiconductor integrated circuit may further include a second external terminal for outputting a signal selected by the first selector to the outside. In addition, the analog circuit includes an analog signal processing unit for processing a signal output from the digital circuit, and the semiconductor integrated circuit includes a parallel / serial (P / S) conversion block for P / S conversion of the signal output from the first selector unit. And a second selector for selecting and outputting an output signal of the analog signal processor or an output signal of the P / S conversion block.

In addition, in the above-described semiconductor integrated circuit, the output signal of the analog circuit is input to the digital circuit, the analog circuit is an analog signal processor for processing a signal input from the outside, the signal input from the outside is S / P conversion And a serial / parallel (S / P) conversion block and an output signal of the S / P conversion block or a signal input from the first external terminal, and output the selected signal to the first selector. Here, in the semiconductor integrated circuit, the first selector unit may select a signal output from the analog circuit or a signal output from the second selector, and input the selected signal into the digital circuit. The semiconductor integrated circuit may further include a second external terminal for outputting a signal selected by the first selector to the outside.

According to another aspect of the present invention, a semiconductor integrated circuit wherein an analog circuit and a digital circuit are integrated therein, and a signal output from one of the analog circuit and the digital circuit is input to the other of the analog circuit and the digital circuit. Circuit test methods are provided. The method includes the steps of: providing a first selector unit integrated in the semiconductor integrated circuit, the first selector section for selecting a signal output from one of an analog circuit and a digital circuit or a signal input from a first external terminal in response to a mode switching signal; Selecting a signal input from the first external terminal by the first selector and inputting the selected signal to another one of an analog circuit and a digital circuit; And examining the output signal of the other of the analog circuit and the digital circuit in consideration of the signal input from the first external terminal.

In the above-described method, in the semiconductor integrated circuit, the output signal of the digital circuit is input to the analog circuit, and the first selector section selects the signal output from the digital circuit or the signal input from the first external terminal, and selects the selected signal from the analog circuit. Can be configured to enter. The semiconductor integrated circuit includes an analog signal processing unit for processing a signal output from the digital circuit, a parallel / serial (P / S) conversion block for P / S conversion of the signal output from the digital circuit, an output signal of the analog signal processing unit, or A second selector for selecting and outputting an output signal of the P / S conversion block may be further provided. In this structure, the first selector section can select and pass a signal output from the digital circuit and the second selector section can select and pass an output signal of the P / S conversion block, thereby providing a serial of the signal output from the digital circuit. Enable output.

In addition, the first selector may select and pass a signal input from the first external terminal, and the second selector may select and pass an output signal of the P / S conversion block, thereby providing P / S from the first external terminal. Enables checking of the connection to the output of the transform block.

In the above-described method, in the semiconductor integrated circuit, the output signal of the analog circuit is input to the digital circuit. The semiconductor integrated circuit includes an analog signal processor for processing a signal input from the outside, a serial / parallel (S / P) conversion block for S / P converting a signal input from the outside, an output signal of the S / P conversion block, or The second selector may further include a second selector for selecting a signal input from the first external terminal and outputting the selected signal to the first selector. The first selector may be a signal output from an analog circuit or a signal output from the second selector. Can be configured to input the selected signal into the digital circuit. In this configuration, the first selector unit can select and pass a signal output from the second selector unit, and the second selector unit can select and pass an output signal of the S / P conversion block, thereby passing an external signal to the digital circuit. Enable serial input.

In addition, the first selector unit may select and pass a signal output from the second selector unit, and the second selector unit may select and pass a signal input from the first external terminal, thereby allowing the digital circuit to be individually inspected. To be able.

In summary, in the above-described semiconductor integrated circuit and its test method, the first selector portion and the second selector portion are switched by a mode switching signal, whereby an internal wiring path for connecting the analog circuit and the digital circuit, the first external terminal, and the first 2 It is possible to selectively connect or disconnect between external terminals. Therefore, by inputting the signal to the first external terminal and outputting the signal from the second external terminal, it becomes possible to individually inspect the function of the operation of the analog circuit or the digital circuit, the wiring path, and the like. As a result, it is possible to easily and clearly inspect the semiconductor integrated circuit having the analog circuit and the digital circuit integrated therein.

The features and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. In the drawings, like reference numerals refer to the same or corresponding parts.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings and descriptions thereof, some reference numerals are used to indicate signal terminals and signals input or output through these signal terminals.

1 is a block circuit diagram showing a structure of a semiconductor integrated circuit according to a first embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 1 is generally denoted by reference numeral C0. The semiconductor integrated circuit C0 has a digital circuit C1 and an analog circuit C2 integrated therein. For example, the digital circuit C1 receives the digital signals input from the digital circuit input terminals I0, I1, ... In, performs digital processing on the digital signals, for example, decoding, storing data, and the like, and clock signals. The digitally processed signals are output as 8-bit parallel digital signals G0, G1, ..., G7 at the time determined by CLK. The analog circuit C2 receives, for example, 8-bit parallel digital signals G0, G1, ..., G7 output from the digital circuit C1 and outputs them from the analog circuit output terminal P0. Convert to That is, the analog circuit C2 converts the digital signals G0, G1, ..., G7 input thereto into an analog signal, and outputs the analog signal at the timing determined by the above-described clock signal CLK. A parallel / serial (P / S) conversion block (D1) for converting an analog signal processor (D0) and an input 8-bit parallel digital signal into a serial digital signal according to an enable signal (CVEN) and a clock signal (CLK). ).

The semiconductor integrated circuit C0 further includes a first selector portion formed of a set of selectors F0, F1, ..., F7, and a second selector portion composed of the selector F8. The selectors F0, F1, ..., F7 are the digital signals G0, G1, ..., G7 or the semiconductor integrated circuit C0 output from the digital circuit C1 in accordance with the mode switching signal S0. Selects the external input signals inputted from the external input terminals TI0, TI1, ..., TI7. The signals selected by the selectors F0, F1, ..., F7 are supplied to the analog signal processor D0, the P / S conversion block D1 and the external output terminals T0, T1, ..., T7. do. The external output terminals T1, T2, ..., T7 are the output terminals of the selectors F0, F1, ..., F7, the input terminals of the analog signal processing unit D0, and the P / S conversion block D1. Connected to the input terminal of, it is used to output 8-bit parallel signals selected by the selectors F0, F1, ..., F7 without changing their logic state.

The selector F8 selects the analog signal output from the analog signal processing unit D0 or the digital signal output from the P / S conversion block D1 in accordance with the mode switching signal S1, and selects the selected signal as the analog circuit output terminal. Output to (P0).

Hereinafter, operation in various modes of the semiconductor integrated circuit shown in FIG. 1 will be described. In the semiconductor integrated circuit according to this embodiment, the operation, characteristics, connection, etc. of the semiconductor integrated circuit can be inspected in four modes determined by the combination of the state of the mode switching signals S0 and S1. In other words, as shown in Fig. 2, four different modes, i.e., "normal operation mode" (S0 = " 0 ") depending on the state " 1 " or " 0 " of each mode switching signal S0, S1. , S1 = "0"), "Analog Circuit Individual Test Mode" (S0 = "1", S1 = "0"), "Simulation Mode" (S0 = "0", S1 = "1"), and "Test Terminal connection confirmation mode "(S0 =" 1 ", S1 =" 1 "). Hereinafter, each mode is demonstrated.

The normal operation mode is used when the semiconductor integrated circuit actually performs a normal operation, that is, when the input digital signal is digitally processed and converted into an analog signal in the semiconductor integrated circuit. In this mode, as shown in Fig. 2, the mode switching signal S0 is set to "0", for example, logically low level, and the mode switching signal S1 is also set to "0", for example, logically low level. do. As a result, the selectors F0, F1, ..., F7 are switched to the state in which the digital signals G0, G1, ..., G7 output from the digital circuit C1 are selected and output. The selector F8 switches to a state in which the output signal from the analog signal processing unit D0 is selected and output.

Accordingly, the digital signals G0, G1, ..., G7 output from the digital circuit C1 pass through the selectors F0, F1, ..., F7 and the analog signal processing unit (1) of the analog circuit C2 ( D0). In the analog signal processing unit D0, the digital signals G0, G1, ..., G7 input thereto are sampled and converted into analog signals in response to the arrival edge or the arrival edge of the clock signal CLK. That is, D / A (digital / analog) conversion is performed. The D / A converted analog signal passes through the selector F8 and is output from the analog circuit output terminal P0.

3 shows signal waveforms in the normal operation mode described above. In Fig. 3, the waveform G (7: 0) in each clock cycle represents 8-bit parallel digital signals G0, G1, ..., G7, and each display " E0H " &Quot; EFH " and the like represent a hexadecimal representation of 8-bit parallel digital signals G0, G1, ..., G7. In the normal operation mode, it is possible to check the overall operation of the semiconductor integrated circuit including the operation of the digital circuit C1, the operation of the analog circuit C2, the connection of the two circuits C1, C2, and the like.

The analog circuit individual test mode is a mode in which the analog circuit C2 is electrically separated from other circuit blocks of the semiconductor integrated circuit C0 so that the analog circuit C2 can operate individually. Behavior, characteristics, etc. can be examined.

In this mode, as shown in Fig. 2, the mode switching signal S0 is set to "1", for example, logically high level, and the mode switching signal S1 is set to "0", for example, logically low level. do. As a result, the selector F0, F1, ..., F7 selects the signals input from the external input terminals TI0, TI1, ..., TI7, and selects them from the selector F0, F1, ..., F7. It is switched to the output state. In addition, the selector F8 is switched to a state in which an output signal from the analog signal processing unit D0 is selected and output from the selector F8.

Accordingly, signals such as test signals input from the external input terminals TI0, TI1, ..., TI7 pass through the selectors F0, F1, ..., F7, and the analog signal processor D0 of the analog circuit C2. ) Is entered. In the analog signal processing unit D0, in response to the arrival edge or the arrival edge of the clock signal CLK, the signals input thereto are sampled and converted into analog signals. That is, D / A conversion. The D / A converted analog signal passes through the selector F8 and is output from the analog circuit output terminal P0.

4 shows signal waveforms in the above-described analog circuit individual test mode. In Fig. 4, the waveforms TI (7: 0) in each clock cycle represent 8-bit parallel digital signals input from the external input terminals TI0, TI1, ..., TI7, each of which is illustrated in the waveform. The display " E0H ", " EFH " and the like represent hexadecimal display of 8-bit parallel digital signals input from the external input terminals TI0, TI1, ..., TI7. In the analog circuit individual test mode, the operation of the analog circuit C2 is performed by checking the signal output from the analog circuit output terminal P0 in consideration of the signals input from the external input terminals TI0, TI1, ..., TI7. It is possible to check the characteristics, etc.

The simulation mode is a mode in which the digital circuit C1 or the like can be digitally tested using, for example, an LSI tester. In the above-described normal mode, since the analog signal is output from the analog circuit output terminal P0, it is difficult to effectively test the digital circuit C1 or the like using the LSI tester. Thus, in this mode, for example, the operation of the digital circuit C1 or the like is simulated and tested using the digital test data.

In this mode, as shown in Fig. 2, the mode switching signal S0 is set to "0", for example, logically low level, and the mode switching signal S1 is set to "1", for example, logically high level. do. As a result, the selectors F0, F1, ..., F7 select the digital signals G0, G1, ..., G7 outputted from the digital circuit C1 to selector F0, F1, ... It is switched to the state output from .F7). In addition, the selector F8 is switched to a state in which an output signal from the P / S conversion block D1 is selected and output from the selector F8.

Accordingly, the digital signals G0, G1, ..., G7 output from the digital circuit C1 pass through the selectors F0, F1, ..., F7 to convert P / S of the analog circuit C2. Input is made to block D1. In the P / S conversion block D1, the input digital signals G0, G1, ..., G7 are converted into serial digital signals. The serial digital signal passes through the selector F8 and is output from the analog circuit output terminal P0. The P / S conversion block D1 is enabled to perform parallel / serial conversion when the enable signal CVEN is "1", for example, a high logic level.

5 shows signal waveforms in the simulation mode described above. In Fig. 5, the waveform G (7: 0) in each clock cycle represents 8-bit parallel digital signals G0, G1, ..., G7, and each display " E0H " &Quot; EFH " and the like represent a hexadecimal representation of 8-bit parallel digital signals G0, G1, ..., G7. In FIG. 5, the P / S conversion block D1 includes the digital signals G0, G1, ..., G7 output from the digital circuit C1 at the timing when the enable signal CVEN becomes "1". The parallel / serial conversion is started and the converted serial signal is output from the analog circuit output terminal P0. For example, in a clock cycle in which the enable signal CVEN becomes "1", the 8-bit parallel signals G0, G1, ..., G7 are "EFH" in hexadecimal and "1110111" in binary. Therefore, from the next clock cycle, data "1", "1 '." 1 "," 0 "," 1 ", ... are sequentially output from the analog circuit output terminal P0. It is possible to effectively and quickly check the operation, characteristics, and the like of the digital circuit C1 and the connection from the digital circuit C1 to the P / S conversion block D1.

In the test terminal connection confirmation mode, in order to confirm whether the analog circuit C2 can be accessed from the outside of the semiconductor integrated circuit in the analog circuit individual test mode described above, the analog circuit C2 is properly connected from the external input terminal. This mode is used to check whether or not there is. Thus, in this mode, the connection related to the analog circuit C2 or the like is simulated and tested using the digital test data.

In this mode, as shown in Fig. 2, the mode switching signal S0 is set to "1", for example, logically high level, and the mode switching signal S1 is also set to "1", for example, logically high level. do. As a result, the selectors F0, F1, ..., F7 select signals inputted from the external input terminals TI0, TI1, ..., TI7, and selectors F0, F1, ..., F7. It is switched to the output state from. In addition, the selector F8 is switched to a state in which an output signal from the P / S conversion block D1 is selected and output from the selector F8.

Therefore, the signals input from the external input terminals TI0, TI1, ..., TI7 pass through the selectors F0, F1, ..., F7 to pass through the P / S conversion block D1 of the analog circuit C2. Is entered. In the P / S conversion block D1, the input signals are converted into serial digital signals. The serial digital signal passes through the selector F8 and is output from the analog circuit output terminal P0.

6 shows signal waveforms in the test terminal connection confirmation mode described above. In Fig. 6, the waveforms TI (7: 0) in each clock cycle represent 8-bit parallel digital signals such as digital test signals input from the external input terminals TI0, TI1, ..., TI7. Each illustrated "E0H", "EFH", etc., represents a hexadecimal representation of 8-bit parallel digital signals. As shown in FIG. 6, the P / S conversion block D1 is inputted from the external input terminals TI0, TI1, ..., TI7 at a timing when the enable signal CVEN becomes "1". The parallel / serial conversion of the digital signals is started and the converted serial signal is output from the analog circuit output terminal P0. Therefore, in this mode, check whether the external input terminals TI0, TI1, ..., TI7 are correctly connected to the analog circuit C2, etc., and check P at the external input terminals TI0, TI1, ..., TI7. The connection to the / S conversion block D1 and the like can be confirmed effectively and quickly.

In all the above-described modes, it is possible to observe and inspect the signals input from the external output terminals T0, T1, ..., T7 to the analog circuit C2. Further, in the simulation mode, signals output from the digital circuit C1 and input to the analog circuit C2 can be directly observed and inspected at the external output terminals T0, T1, ..., T7.

As described above, in the first embodiment, by providing selectors F0, F1, ..., F7, selector F8, and P / S conversion block D1 to the analog circuit C2, and By appropriately switching (F0, F1, ..., F7) and selector F8, the connection between the digital circuit C1 and the analog circuit C2 can be inspected or the output signal from the digital circuit C1 can be directly Can be checked In addition, by inputting or outputting signals in a state in which the digital circuit and the analog circuit are disconnected, the operation and characteristics of the digital circuit and the analog circuit can be individually inspected. In particular, by using the simulation mode, it is possible to directly derive the signal output from the digital circuit C1 through the output terminal P0. Therefore, the semiconductor integrated circuit is inspected using a simulator or an LSI that handles only the digital signal. Can be carried out effectively and quickly.

7 is a block circuit diagram showing a schematic structure of a semiconductor integrated circuit according to the second embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 7 is generally denoted by reference numeral H0. The semiconductor integrated circuit H0 includes an analog circuit H1 and a digital circuit H2 integrated therein.

The analog circuit H1 receives the analog signal input from the analog input terminal N0 and converts the analog signal into a digital signal supplied to the digital circuit H2. That is, the analog circuit H1 converts the input analog signal into an eight-line digital signal and outputs the analog signal processing unit L0 and the one-line digital signal input to the analog input terminal N0 as an eight-line digital signal. And a serial / parallel (S / P) conversion block L1 for converting. In addition, the analog circuit H1 may include signals inputted to the semiconductor integrated circuit from the outside through the external input terminals DA0, DA1, ..., DA7 or the S / P conversion block according to the mode switching signal MS0. The selector J8, J9, ..., J15 for selecting one of the output signals from L1, and the eight-line signals outputted from the analog signal processor L0 and the selector J8, in accordance with the mode switching signal MS1. And selectors J0, J1, ..., J7 for selecting one of the signals output from J9, ..., J15.

The digital circuit H2 receives 8 line input signals K0.K1, ..., K7 from the selectors J0, J1, ..., J7, respectively, and performs predetermined processing such as encoding and data storage. Output to digital circuit output terminals (R0, R1, ..., Rn). In addition, the input terminals of the digital circuit H2 to which the input signals K0.K1, ..., K7 are input are connected to the external output terminals DB0, DB1, ..., DB7 of the semiconductor integrated circuit H0. do.

The clock signal MCLK is input to the analog signal processor L0 and the digital circuit H2, and both the analog signal processor L0 and the digital circuit H2 operate in accordance with the timing of the clock signal MCLK. In addition, the S / P conversion block L1 operates only when it is enabled by the conversion enable signal CVDN.

The semiconductor integrated circuit shown in FIG. 7 has four modes determined by the combination of the states of the mode switching signals MS0 and MS1. In other words, as shown in Fig. 8, four different modes, that is, the "normal operation mode" (MS0 = "0"), depending on the state "1" or "0" of each mode switching signal MS0, MS1. , "MS1 =" 0 ")," Analog Circuit Individual Test Mode "(MS0 =" 0 ", MS1 =" 0 ")," Simulation Mode "(MS0 =" 0 ", MS1 =" 1 "), and" Digital " Macro test mode "(MS0 =" 1 ", MS1 =" 1 "). Here, it can be seen that the states of the mode switching signals MS0 and MS1 are the same in the "normal operation mode" and the "analog circuit individual test mode".

In the normal operation mode, the mode switching signals MS0 and MS1 are all "0". In this mode, the selectors J8, J9, ..., J15 select the output signal passing through the S / P conversion block L1, while the selectors J0, J1, ..., J7 select the analog signal processing section. Select the signal that passed (L0). Therefore, the analog signal supplied from the outside through the analog signal input terminal N0 is input to the analog signal processing unit L0 of the analog circuit H1, and is sampled by the clock signal MCLK and converted into a digital signal. The converted digital signals are input to the digital circuit H2 through the selectors J0, J1, ..., J7 as the input signals K0.K1, ..., K7. The input signals K0.K1, ..., K7 are digitally processed as described above in the digital circuit H2 and output from the digital circuit output terminals R0, R1, ..., Rn.

9 shows signal waveforms in the normal operation mode described above. In FIG. 9, the waveform K (7: 0) in each clock cycle represents an 8-bit parallel digital signal K0.K1, ..., K7 input to the digital circuit H2, and in each clock cycle. Waveforms DB (7: 0) represent the same 8-bit parallel digital signals output from external output terminals DB0, DB1, ..., DB7. In the normal operation mode, it is possible to check the overall operation of the semiconductor integrated circuit H0 including the operation of the analog circuit H1, the operation of the digital circuit H2, the connection of the two circuits H1, H2, and the like.

The analog signal individual test mode is realized under the same mode switching signals MS0 and MS1 as in the normal operation mode. The signals K0.K1, ..., K7 output from the analog signal processor L0 may be obtained from the external output terminals DB0, DB1, ..., DB7. By observing and inspecting the input signals K0, K1, ..., K7, it is possible to individually inspect the operation, characteristics, and the like of the analog circuit H1. The waveform of the signal in this mode is the same as the waveform shown in FIG.

In the simulation mode, as shown in Fig. 8, the mode switching signal MS0 is "0" and the mode switching signal MS1 is "1". Thus, selectors J8, J9, ..., J15 select the output signal which has passed through S / P conversion block L1, while selectors J0, J1, ..., J7 selector J8, J9. , ..., J15) to select the signal that passed. As a result, it is possible to input the serial digital signal from the analog signal input terminal N0 to the S / P conversion block L1 and convert it into an eight-line digital signal. The converted eight-line digital signals are input signals K0.K1, ..., K7 through selectors J8, J9, ..., J15 and selectors J0, J1, ..., J7. It is supplied to the digital circuit H2.

Fig. 10 shows signal waveforms in the simulation mode described above. As shown in Fig. 10, for example, at the arrival of the conversion enable signal CVDN, the S / P conversion block L1 is 8-bit digital from the analog signal input terminal N0 at the timing of the clock signal MCLK. Start receiving signals sequentially. After eight clock cycles, at a timing when the conversion enable signal CVDN becomes " 1 ", the S / P conversion block L1 is an eight-line parallel digital signal converted from a serial signal input from the analog signal input terminal N0. Will start printing. The converted eight-line digital signal is supplied to the digital circuit H2 as the input signals K0.K1, ..., K7. For example, in Fig. 10, an 8-bit serial signal "11000101" (in this case, "1" is low level and "0" is high level) is received from the input terminal N0, and then the input signal K0. The hexadecimal signal " C5H " is obtained as .K1, ..., K7). Therefore, in the simulation mode, the operation, characteristics, etc. of the digital circuit H2 including circuits from the S / P conversion block L1 to the digital circuit H2 and the like can be obtained by using a simulator or an LSI tester that handles the digital signals. It can be tested effectively and quickly.

In the digital circuit test mode, the mode switching signals MS0 and MS1 are both "1". In this mode, the selectors J8, J9, ..., J15 select the signals passing through the external input terminals DA0, DA1, ..., DA7, and selectors J0, J1, ..., J7 Selects the signal that has passed through selectors J8, J9, ..., J15. Therefore, without using the analog signal processing unit L0 and the S / P conversion block L1, through the selectors J8, J9, ..., J15 and the selectors J0, J1, ..., J7, As the input signals K0.K1, ..., K7, a digital signal may be input from the external input terminals DA0, DA1, ..., DA7 to the digital circuit H2. The input signals K0.K1, ..., K7 are digitally processed as described above in the digital circuit H2 and output from the digital circuit output terminals R0, R1, ..., Rn.

Fig. 11 shows signal waveforms in the above-described digital circuit test mode. In Fig. 11, the waveforms DA (7: 0) and waveforms K (7: 0) in each clock cycle are respectively input to the external input terminals DA0, DA1, ..., inputted to the digital circuit H2. DA7) and the parallel digital signals supplied from the digital signals K0.K1, ..., K7. In the digital circuit test mode, for example, it is possible to check the digital circuit H2 by using a digital test signal or the like input from the external input terminals DA0, DA1, ..., DA7.

As described above, in the second embodiment, the selector J0, J1, ..., J7, the selector J8, J9, ..., J15, and the S / P conversion block in the analog circuit H1. L1) and by appropriately switching the selectors J0, J1, ..., J7 and the selectors J8, J9, ..., J15, between the analog circuit H1 and the digital circuit H2. It is possible to check the connection or output the signal directly from the analog circuit H1. In addition, by inputting or outputting a signal under the condition that the analog circuit H1 and the digital circuit H2 are disconnected, it is possible to individually inspect the operation and characteristics of the analog circuit H1 and the digital circuit H2. In particular, by using the simulation mode, it is possible to directly input the serial digital signal from the terminal NO to the digital circuit H2 via the S / P conversion block L1. Therefore, the inspection of the digital circuit H2 using the simulator which handles only the digital signal or the LSI tester can be carried out effectively and quickly.

In the above embodiments, a plurality of selectors are provided in the analog circuit. However, since these selectors operate only when the mode is switched, and these selectors operate independently of the operation of analog circuits and digital circuits, these selectors are placed in portions other than analog circuits in semiconductor integrated circuits, or analog circuits and digital circuits. It can be arranged independently from the circuit.

As described above, according to the present invention, in a semiconductor integrated circuit having an analog circuit and a digital circuit integrated therein, and a signal from one of the analog circuit and the digital circuit is input to the other of the analog circuit and the digital circuit, A first selector section is provided for selecting between a signal input from one of an analog circuit and a digital circuit and a signal input from a first external input terminal. Therefore, by appropriately switching the first selector, it is possible to selectively connect or disconnect the wiring path between the analog circuit and the digital circuit, and to disconnect or connect between the first external input terminal and the analog or digital circuit. As a result, by inputting a test signal or the like through the first external input terminal, it becomes possible to individually inspect the operation of the analog circuit or the digital circuit.

In addition, an analog signal processing unit and P / S conversion means or S / P conversion means are constituted in an analog circuit, and a signal input from an external input terminal is selected between the output from the analog signal processing unit and the output of the P / S conversion means. And a second selector for selecting between the output of the S / P conversion means. By this structure, it is possible to effectively and accurately check the analog and digital circuits and the wiring paths integrated in the semiconductor integrated circuit.

Although the foregoing description has been made with reference to specific embodiments, those skilled in the art can make various modifications and changes without departing from the spirit of the invention described in the claims. Accordingly, the present invention is to be described in an illustrative sense, and not by way of limitation, and all analogous art shall be included within the spirit of the invention. Accordingly, the invention is intended to embrace all such changes and modifications as fall within the scope of the appended claims.

Claims (16)

In a semiconductor integrated circuit in which an analog circuit and a digital circuit are integrated therein, and a signal output from one of the analog circuit and the digital circuit is input to the other of the analog circuit and the digital circuit. In response to a mode switching signal, one of a signal output from the one of the analog circuit and the digital circuit or a signal input from a first external terminal is selected, and the selected signal is selected from the other of the analog circuit and the digital circuit. A semiconductor integrated circuit having a first selector unit for inputting one. The digital signal of claim 1, wherein an output signal of the digital circuit is input to the analog circuit, and the first selector selects a signal output from the digital circuit or a signal input from the external terminal, and selects the selected signal as the analog circuit. The semiconductor integrated circuit, characterized in that the input. The semiconductor integrated circuit according to claim 2, further comprising a second external terminal for outputting a signal selected by the first selector to the outside. 3. The analog circuit according to claim 2, wherein the analog circuit includes an analog signal processing unit for processing a signal output from the digital circuit, and the semiconductor integrated circuit includes parallel / P / S conversion of a signal output from the first selector unit. And a second selector for selecting and outputting a serial (P / S) conversion block and an output signal of the analog signal processor or an output signal of the P / S conversion block. 4. The analog circuit according to claim 3, wherein the analog circuit includes an analog signal processing unit for processing a signal output from the digital circuit, and the semiconductor integrated circuit includes parallel / P / S conversion of a signal output from the first selector unit. And a second selector for selecting and outputting a serial (P / S) conversion block and an output signal of the analog signal processor or an output signal of the P / S conversion block. The signal of claim 1, wherein an output signal of the analog circuit is input to the digital circuit, and the analog circuit includes an analog signal processor for processing a signal input from an external device, and a serial / sigma signal for S / P conversion. And a parallel (S / P) conversion block and an output signal of the S / P conversion block or a signal input from the first external terminal, and output the selected signal to the first selection unit. The semiconductor integrated circuit according to claim 6, wherein the first selector unit selects a signal output from the analog circuit or a signal output from the second selector and inputs the selected signal to the digital circuit. 7. The semiconductor integrated circuit according to claim 6, further comprising a second external terminal for outputting a signal selected by the first selector to the outside. 8. The semiconductor integrated circuit according to claim 7, further comprising a second external terminal for outputting a signal selected by the first selector to the outside. In the semiconductor integrated circuit test method wherein an analog circuit and a digital circuit are integrated therein, and a signal output from one of the analog circuit and the digital circuit is input to the other of the analog circuit and the digital circuit. Providing a first selector unit integrated in the semiconductor integrated circuit and configured to select a signal output from one of the analog circuit and the digital circuit or a signal input from a first external terminal in response to a mode switching signal; Selecting a signal input from the first external terminal by the first selector and inputting the selected signal to the other one of the analog circuit and the digital circuit; And And examining the output signal of the other of the analog circuit and the digital circuit in consideration of the signal input from the first external terminal. 11. The semiconductor integrated circuit of claim 10, wherein in the semiconductor integrated circuit, an output signal of the digital circuit is input to the analog circuit, and the first selector unit selects a signal output from the digital circuit or a signal input from the first external terminal. And by inputting the selected signal to the analog circuit, the analog circuit can be individually inspected from the digital circuit. 11. The semiconductor integrated circuit of claim 10, wherein in the semiconductor integrated circuit, an output signal of the digital circuit is input to the analog circuit, and the first selector unit selects a signal output from the digital circuit or a signal input from the first external terminal. Input the selected signal to the analog circuit, the semiconductor integrated circuit includes an analog signal processor for processing a signal output from the digital circuit and a parallel / serial P / S conversion for a signal output from the digital circuit. / S) conversion block and a second selector for selecting and outputting the output signal of the analog signal processing unit or the output signal of the P / S conversion block, wherein the first selector unit is a signal output from the digital circuit Select and pass the signal, and the second selector unit selects and passes the output signal of the P / S conversion block, thereby And a serial output of the signal output from the de-circuit circuit. 11. The semiconductor integrated circuit of claim 10, wherein in the semiconductor integrated circuit, an output signal of the digital circuit is input to the analog circuit, and the first selector unit selects a signal output from the digital circuit or a signal input from the first external terminal. Input the selected signal to the analog circuit, the semiconductor integrated circuit includes an analog signal processor for processing a signal output from the digital circuit and a parallel / serial P / S conversion for a signal output from the digital circuit. / S) conversion block and a second selector for selecting and outputting the output signal of the analog signal processing unit or the P / S conversion block, the first selector unit is input from the first external terminal Selects and passes the selected signal, and the second selector unit selects and passes the output signal of the P / S conversion block. 1) A method for testing a semiconductor integrated circuit, characterized in that it is possible to inspect a connection from an external terminal to said output of said P / S conversion block. 11. The semiconductor integrated circuit of claim 10, wherein in the semiconductor integrated circuit, an output signal of the analog circuit is input to the digital circuit, and the semiconductor integrated circuit outputs a second external terminal for outputting a signal selected by the first selector to the outside. And further comprising the analog circuit can be individually inspected from the digital circuit. The semiconductor integrated circuit of claim 10, wherein the output signal of the analog circuit is input to the digital circuit, and the semiconductor integrated circuit includes an analog signal processor for processing a signal input from the outside, and a signal input from the outside. A serial / parallel (S / P) conversion block for S / P conversion, an output signal of the S / P conversion block or a signal input from the first external terminal, and outputting the selected signal to the first selector; And a second selector unit, wherein the first selector unit selects a signal output from the analog circuit or a signal output from the second selector unit to input a selected signal to the digital circuit, and the first selector unit When the signal output from the second selector unit is selected and passed through, and the second selector unit selects and passes the output signal of the S / P conversion block. And thereby enabling serial input of an external signal to the digital circuit. The semiconductor integrated circuit of claim 10, wherein the output signal of the analog circuit is input to the digital circuit, and the semiconductor integrated circuit includes an analog signal processor for processing a signal input from the outside, and a signal input from the outside. A serial / parallel (S / P) conversion block for S / P conversion, an output signal of the S / P conversion block or a signal input from the first external terminal, and outputting the selected signal to the first selector; A second selector unit is further provided, wherein the first selector unit selects a signal output from the analog circuit or a signal output from the second selector unit to input the selected signal to the digital circuit, and the first selector unit comprises the first selector. 2 selects and passes a signal output from the selector unit, and the second selector unit selects a signal input from the first external terminal And the digital circuit can be inspected individually by passing it through.