KR20000021053A - Method of forming metal wiring of semiconductor device - Google Patents
Method of forming metal wiring of semiconductor device Download PDFInfo
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- KR20000021053A KR20000021053A KR1019980039974A KR19980039974A KR20000021053A KR 20000021053 A KR20000021053 A KR 20000021053A KR 1019980039974 A KR1019980039974 A KR 1019980039974A KR 19980039974 A KR19980039974 A KR 19980039974A KR 20000021053 A KR20000021053 A KR 20000021053A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 90
- 239000002184 metal Substances 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 92
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 36
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 36
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 31
- 239000010937 tungsten Substances 0.000 claims abstract description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 47
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 20
- 239000006227 byproduct Substances 0.000 abstract description 10
- 238000005260 corrosion Methods 0.000 abstract description 2
- 230000007797 corrosion Effects 0.000 abstract description 2
- 235000012054 meals Nutrition 0.000 abstract 1
- 238000004380 ashing Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀 더 구체적으로는 반도체 장치의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring in a semiconductor device.
도 1a 내지 도 1c는 종래의 반도체 장치의 금속 배선 형성 방법의 공정들을 순차적으로 보여주는 단면도이다.1A to 1C are cross-sectional views sequentially showing processes of a metal wiring forming method of a conventional semiconductor device.
도 1a를 참조하면, 종래의 반도체 장치의 금속 배선 형성 방법은, 먼저 제 1 층간 절연막(10) 상에 배리어막(12), 알루미늄막(14), 그리고 캡핑층(16)이 차례로 형성된다. 상기 배리어막(12)은 Ti막과 Ti/TiN막 중 어느 하나로 형성되며, 상기 캡핑층(16)은 TiN막으로 형성된다. 이어, 상기 캡핑층(16) 상에 포토레지스트막 패턴(18)이 형성된다.Referring to FIG. 1A, in the conventional method of forming metal wirings of a semiconductor device, a barrier film 12, an aluminum film 14, and a capping layer 16 are sequentially formed on a first interlayer insulating film 10. The barrier layer 12 is formed of any one of a Ti layer and a Ti / TiN layer, and the capping layer 16 is formed of a TiN layer. Subsequently, a photoresist layer pattern 18 is formed on the capping layer 16.
상기 포토레지스트막 패턴(18)을 마스크로 사용하여 상기 캡핑층(16), 알루미늄막(14), 그리고 배리어막(12)을 차례로 식각함으로써 금속막 패턴이 형성된다. 상기 금속막 패턴은 알루미늄막(14)과 캡핑층(16)으로 이루어진다. 상기 금속막 패턴 형성을 위한 식각시 상기 금속막 패턴들 간의 브리지(bridge)를 방지하기 위해 상기 제 1 층간 절연막(10)의 일부 두께가 함께 식각된다.The metal layer pattern is formed by sequentially etching the capping layer 16, the aluminum layer 14, and the barrier layer 12 using the photoresist layer pattern 18 as a mask. The metal film pattern includes an aluminum film 14 and a capping layer 16. A portion of the thickness of the first interlayer insulating layer 10 is etched together to prevent a bridge between the metal layer patterns during the etching for forming the metal layer pattern.
이때, 상기 금속막 패턴 형성을 위한 금속막들(12, 14, 16)의 식각시 마스크로 사용되는 포토레지스트막 패턴(18)의 두께가 낮을 경우, 상기 포토레지스트막 패턴(18)은 상기 금속막들(12, 14, 16)의 식각 가스에 대한 식각 선택비가 낮기 때문에 상기 포토레지스트막 패턴(18)이 식각되면 금속막 패턴의 상부 에지 부분도 함께 식각되는 현상이 발생될 수 있다.In this case, when the thickness of the photoresist film pattern 18 used as a mask when etching the metal films 12, 14, and 16 for forming the metal film pattern is low, the photoresist film pattern 18 may be formed of the metal. Since the etching selectivity of the layers 12, 14, and 16 with respect to the etching gas is low, when the photoresist layer pattern 18 is etched, the upper edge portion of the metal layer pattern may also be etched.
다음에, 애싱(ashing) 공정으로 상기 포토레지스트막 패턴(18)이 제거된다. 상기 애싱 공정은 O2, CF4가스가 주 애싱 가스로 사용되어 수행되는데 상기 포토레지스트막 패턴(18) 형성을 위한 애싱 공정시 상기 캡핑층(16)인 TiN막도 부분적으로 식각되어 상기 캡핑층(16)의 표면이 거칠어지는 현상이 생길 수 있다.Next, the photoresist film pattern 18 is removed by an ashing process. The ashing process is performed using O 2 , CF 4 gas as the main ashing gas, and the TiN film, which is the capping layer 16, is partially etched during the ashing process for forming the photoresist layer pattern 18. The surface roughness of (16) may occur.
이어, 상기 금속막 패턴을 포함하여 상기 제 1 층간 절연막(10) 상에 제 2 층간 절연막(20)이 형성된다. 비아 콘택홀(via contact hole) 형성용 마스크를 사용하여 상기 금속막 패턴의 표면이 노출될 때까지 상기 제 2 층간 절연막(20)을 식각함으로써 비아 콘택홀(22)이 형성된다. 그러나, 상기 비아 콘택홀(22) 형성을 위한 식각시 과식각되어 상기 금속막 패턴의 캡핑층(16) 및 알루미늄막(14)이 식각될 수 있다.Subsequently, a second interlayer insulating film 20 is formed on the first interlayer insulating film 10 including the metal film pattern. The via contact hole 22 is formed by etching the second interlayer insulating layer 20 until the surface of the metal layer pattern is exposed using a mask for forming a via contact hole. However, during etching to form the via contact hole 22, the capping layer 16 and the aluminum layer 14 of the metal layer pattern may be etched.
그 결과로, 식각된 알루미늄막 부산물이 상기 비아 콘택홀(22)의 측벽에 붙는 현상이 발생되고, 식각 부산물에 의해 저항이 증가되는 문제가 생긴다. 그리고, 상기 금속막 패턴의 형성 후, 대기 중에 노출시 상기 비아 콘택홀(22) 형성시 노출된 알루미늄막(14)이 부식되는 현상이 발생될 수 있다.As a result, a phenomenon that the etched aluminum film by-products adhere to the sidewalls of the via contact hole 22 occurs, and a problem arises in that the resistance is increased by the etching by-products. After the formation of the metal layer pattern, the exposed aluminum layer 14 may be corroded when the via contact hole 22 is formed when exposed to the air.
본 발명은 상술한 제반 문제점을 해결하기 위해 제안된 것으로서, 금속막 패턴의 식각시 포토레지스트막 패턴의 식각으로 금속막 상부가 식각되고, 비아 콘택홀 형성시 부산물이 생기는 것을 방지할 수 있고, 콘택홀의 측벽에 알루미늄막이 붙고, 대기 중에 노출시 알루미늄막의 부식을 방지할 수 있는 반도체 장치의 금속 배선 형성 방법을 제공함에 그 목적이 있다.The present invention has been proposed to solve the above-mentioned problems, and the upper portion of the metal layer is etched by the etching of the photoresist layer pattern during the etching of the metal layer pattern, and by-products can be prevented from being formed when the via contact hole is formed. An object of the present invention is to provide a method for forming a metal wiring in a semiconductor device in which an aluminum film is attached to the sidewall of the hole and can prevent corrosion of the aluminum film when exposed to air.
도 1a 내지 도 1c는 종래의 반도체 장치의 금속 배선 형성 방법의 공정들을 순차적으로 보여주는 단면도; 그리고1A to 1C are cross-sectional views sequentially showing processes of a metal wiring forming method of a conventional semiconductor device; And
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 장치의 금속 배선 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.2A through 2D are flowcharts sequentially illustrating processes of a metal line forming method of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10, 100 : 제 1 층간 절연막 12, 102 : 배리어막10, 100: first interlayer insulating film 12, 102: barrier film
14, 104 : 알루미늄막 16, 106 : 캡핑층14, 104: aluminum film 16, 106: capping layer
108 : 텅스텐막 18, 110: 포토레지스트막 패턴108: tungsten film 18, 110: photoresist film pattern
20, 112 : 제 2 층간 절연막 22, 114 : 비아 콘택홀20, 112: second interlayer insulating film 22, 114: via contact hole
(구성)(Configuration)
상술한 목적을 달성하기 위한 본 발명에 의하면, 반도체 장치의 금속 배선 형성 방법은, 제 1 층간 절연막 상에 배리어막, 제 1 금속막, 그리고 제 2 금속막을 차례로 형성하는 단계와; 상기 제 2 금속막은 상기 제 1 금속막을 식각하는 식각 가스에 대해 식각 선택비를 갖는 막질이고, 배선 형성용 마스크를 사용하여 상기 제 2 금속막, 제 1 금속막, 그리고 배리어막을 차례로 식각하여 금속막 패턴을 형성하는 단계와; 상기 금속막 패턴 상의 상기 마스크를 제거하는 단계와; 상기 금속막 패턴을 포함하여 상기 제 1 절연막 상에 제 2 층간 절연막을 형성하는 단계 및; 콘택홀 형성용 마스크를 사용하여 상기 제 1 금속막의 표면이 노출될 때까지 상기 제 2 층간 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하되, 상기 제 2 금속막에 의해 상기 제 1 금속막이 노출되지 않는다.According to the present invention for achieving the above object, a method of forming a metal wiring of a semiconductor device comprises the steps of: sequentially forming a barrier film, a first metal film, and a second metal film on the first interlayer insulating film; The second metal layer is a film having an etching selectivity with respect to an etching gas for etching the first metal layer, and the second metal layer, the first metal layer, and the barrier layer are sequentially etched using a wiring forming mask to form a metal layer. Forming a pattern; Removing the mask on the metal film pattern; Forming a second interlayer insulating film on the first insulating film including the metal film pattern; Forming a contact hole by etching the second interlayer insulating film until the surface of the first metal film is exposed using a contact hole forming mask, wherein the first metal film is exposed by the second metal film. It doesn't work.
(작용)(Action)
도 2c를 참조하면, 본 발명의 실시예에 따른 신규한 반도체 장치의 금속 배선 형성 방법은, 제 1 층간 절연막 상에 형성된 배리어막, 제 1 금속막, 그리고 제 2 금속막을 배선 형성용 마스크를 사용하여 차례로 식각함으로써 금속막 패턴이 형성된다. 이때, 상기 제 2 금속막은 제 1 금속막을 식각하는 식각 가스에 대해 식각 선택비를 갖는 막질로 형성된다. 이와 같은 반도체 장치의 금속 배선 형성 방법에 의해서, 금속막 패턴 형성을 위한 금속으로 텅스텐막을 추가하여 형성함으로써 금속막 패턴 형성시 마스크로서 작용하여 금속막 패턴이 식각되는 것을 방지할 수 있고, 비아 콘택홀 형성을 위한 식각시 알루미늄막이 식각되면서 발생한 부산물이 콘택홀의 측벽에 붙는 현상 및 부산물이 생성되는 현상 등을 방지할 수 있으며, 그리고 대기 중에 노출시 알루미늄막이 부식되는 것을 방지할 수 있다.Referring to FIG. 2C, in the method of forming a metal wiring of a novel semiconductor device according to an embodiment of the present invention, a barrier film, a first metal film, and a second metal film formed on a first interlayer insulating film may be formed using a wiring forming mask. By etching sequentially, a metal film pattern is formed. In this case, the second metal layer is formed of a film having an etching selectivity with respect to the etching gas for etching the first metal layer. By the metal wiring forming method of the semiconductor device, by adding a tungsten film to the metal for forming the metal film pattern, the metal film pattern can be prevented from being etched by acting as a mask when forming the metal film pattern, and the via contact hole is formed. When the aluminum film is etched for forming, by-products generated by etching may be prevented from sticking to the sidewalls of the contact holes, and by-products may be generated, and the aluminum film may be prevented from being corroded when exposed to the air.
(실시예)(Example)
이하, 도 2a 내지 도 2d를 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2D.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 장치의 금속 배선 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.2A through 2D are flowcharts sequentially illustrating processes of a metal line forming method of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 본 발명의 반도체 장치의 금속 배선 형성 방법은, 먼저 제 1 층간 절연막(100) 상에 배리어막(barrier layer)(102), 알루미늄(Al)막(104), 캡핑층(capping layer)(106), 그리고 텅스텐(W)막(108)이 차례로 형성된다. 상기 배리어막(102)은 Ti막과 Ti/TiN막 중 어느 하나로 형성되고, 상기 캡핑층(106)은 TiN막으로 형성된다.Referring to FIG. 2A, a metal wiring forming method of a semiconductor device according to an embodiment of the present invention may first include a barrier layer 102, an aluminum (Al) film 104, and a capping layer (on a first interlayer insulating film 100). A capping layer 106 and a tungsten (W) film 108 are formed in this order. The barrier layer 102 is formed of one of a Ti layer and a Ti / TiN layer, and the capping layer 106 is formed of a TiN layer.
상술한 바와 같이, 본 발명에서는 상기 캡핑층(106) 상에 금속막으로 텅스텐막(108)이 추가로 형성된다. 상기 텅스텐막(108)은 금속막 패턴의 주 금속(main metal)인 알루미늄막(104)에 비해 상대적으로 얇은 두께로 형성되며, 상기 알루미늄막(104)을 식각하는 식각 가스에 대해 식각 선택비를 갖는 막질이다. 이어, 상기 텅스텐막(108) 상에 포토레지스트막 패턴(110)이 형성된다.As described above, in the present invention, a tungsten film 108 is further formed on the capping layer 106 as a metal film. The tungsten film 108 is formed to have a relatively thin thickness compared to the aluminum film 104 which is the main metal of the metal film pattern, and has an etch selectivity with respect to an etching gas for etching the aluminum film 104. It is a membrane quality. Subsequently, a photoresist film pattern 110 is formed on the tungsten film 108.
도 2b에 있어서, 상기 포토레지스트막 패턴(110)이 마스크로 사용되어 상기 텅스텐막(108)이 식각된다. 여기서, 상기 텅스텐막(108)은 상기 캡핑층(106)인 TiN막과의 선택비를 이용하여 식각된다. 상기 식각 공정은 SF6식각 가스가 주 가스(main gas)로 사용되어 수행된다.In FIG. 2B, the tungsten film 108 is etched by using the photoresist film pattern 110 as a mask. Here, the tungsten film 108 is etched using the selectivity with respect to the TiN film which is the capping layer 106. The etching process is performed using SF 6 etching gas as the main gas.
다음에, 상기 캡핑층(106), 알루미늄막(104), 그리고 배리어막(102)을 차례로 식각함으로써 도 2c에 도시된 바와 같이, 금속막 패턴이 형성된다. 상기 금속막 패턴은 알루미늄막(104), 캡핑층(106), 그리고 텅스텐막(108)으로 이루어진다. 상기 금속막 패턴 형성을 위한 상기 금속막들의 식각시 제 1 층간 절연막(100) 상에 떨어진 금속들에 의한 브리지를 방지하기 위해 상기 제 1 층간 절연막(100)의 일부 두께도 함께 식각된다.Next, the capping layer 106, the aluminum film 104, and the barrier film 102 are sequentially etched to form a metal film pattern as shown in FIG. 2C. The metal film pattern includes an aluminum film 104, a capping layer 106, and a tungsten film 108. Partial thicknesses of the first interlayer insulating layer 100 may also be etched to prevent bridges due to metals falling on the first interlayer insulating layer 100 when the metal layers are etched to form the metal layer pattern.
상기 금속막 패턴 형성을 위한 식각 방법으로는 도 2b에 도시되어 있는 상기 텅스텐막(108)을 패터닝한 포토레지스트막 패턴(110)을 마스크로 사용하여 상기 캡핑층(106), 알루미늄막(104), 그리고 배리어막(102)을 바로 식각하는 방법과 상기 포토레지스트막 패턴(110)을 제거한 후, 상기 텅스텐막(108)을 마스크로 사용하여 상기 캡핑층(106), 알루미늄막(104), 그리고 배리어막(102)을 차례로 식각하는 방법이 있다.As an etching method for forming the metal film pattern, the capping layer 106 and the aluminum film 104 using the photoresist film pattern 110 patterned from the tungsten film 108 shown in FIG. 2B as a mask. After the barrier layer 102 is directly etched and the photoresist layer pattern 110 is removed, the capping layer 106, the aluminum layer 104, and the tungsten layer 108 are used as a mask. There is a method of etching the barrier film 102 in sequence.
상기 포토레지스트막 패턴(110)을 마스크로 사용하여 상기 텅스텐막(108) 하부의 금속막들을 식각하는 방법에서 상기 포토레지스트막 패턴(110)은 상기 금속막들에 비해 상대적으로 식각 선택비가 낮기 때문에 상기 금속막들을 식각하기 위한 식각 가스인 Cl 가스로 수행시 상기 포토레지스트막 패턴(110)도 함께 식각되어 상기 텅스텐막(108)의 표면이 도 2c와 같이, 노출될 수 있다. 그러나, 상기 알루미늄막(104)의 주 식각 가스로 사용되는 상기 Cl2가스에 상기 알루미늄막(104)은 잘 식각되지만 텅스텐막(108)은 잘 식각되지 않는다.In the method of etching the metal layers below the tungsten layer 108 using the photoresist layer pattern 110 as a mask, the photoresist layer pattern 110 has a lower etching selectivity than the metal layers. When the photoresist layer pattern 110 is etched together with Cl gas, which is an etching gas for etching the metal layers, the surface of the tungsten layer 108 may be exposed as shown in FIG. 2C. However, the aluminum film 104 is well etched in the Cl 2 gas used as the main etching gas of the aluminum film 104, but the tungsten film 108 is not etched well.
결과적으로, 상기 텅스텐막(108)에 의해 하부의 캡핑층(106), 알루미늄막(104), 그리고 배리어막(102)은 종래의 금속막들에 비해 상대적으로 낮은 식각률을 갖는 포토레지스트막 패턴(110)이 식각되면서 발생되었던 금속막 패턴 상부 에지의 식각이 방지된다.As a result, the lower capping layer 106, the aluminum film 104, and the barrier film 102 are formed by the tungsten film 108 to have a photoresist pattern having a relatively lower etching rate than that of conventional metal films. Etching of the upper edge of the metal film pattern generated as the 110 is etched is prevented.
다음에, 상기 텅스텐막(108)을 마스크로 사용하여 상기 금속막들을 식각하는 방법은, 앞서 설명한 방법에 비해 다소 복잡하나 한 챔버(chamber)에서 텅스텐막(108)과 알루미늄막(104)을 한 번의 공정으로 식각할 수 없는 상황에서 수행된다. 상기 방법에 따른 상기 금속막 패턴 형성을 위한 공정은 먼저, 텅스텐막(108) 상의 포토레지스트막 패턴(110)을 제거하기 위한 애싱 공정과 스트립 공정이 수행된다(도면에 미도시).Next, the method of etching the metal films using the tungsten film 108 as a mask is somewhat more complicated than the method described above, but the tungsten film 108 and the aluminum film 104 are formed in one chamber. It is carried out in a situation where it cannot be etched by the burn process. In the process for forming the metal film pattern according to the method, first, an ashing process and a strip process for removing the photoresist film pattern 110 on the tungsten film 108 are performed (not shown).
이때, 상기 텅스텐막(108)에 의해 상기 포토레지스트막 패턴(110)의 제거 공정시 상기 캡핑층(106)의 표면이 거칠어지는 현상을 방지할 수 있고, 상기 알루미늄막(104) 상의 캡핑층(106)이 식각되지 않고 남게 됨으로써 대기 중에 노출시 상기 알루미늄막(104)이 부식되는 것을 방지할 수 있다. 그리고, 식각시 상기 알루미늄막(104)의 주 식각 가스인 Cl2가스에 상기 텅스텐막(108)은 상기 언급한 바와 같이, 식각이 잘 되지 않기 때문에 상기 텅스텐막(108)은 마스크로서의 역할을 잘 수행한다.In this case, the surface of the capping layer 106 may be roughened during the removal process of the photoresist layer pattern 110 by the tungsten layer 108, and the capping layer on the aluminum layer 104 may be prevented. 106 may be left without being etched to prevent the aluminum film 104 from being corroded when exposed to air. In addition, since the tungsten film 108 is not etched well in the Cl 2 gas, which is the main etching gas of the aluminum film 104 during etching, the tungsten film 108 serves as a mask well. Perform.
이어, 상기 금속막 패턴을 포함하여 상기 제 1 층간 절연막(100) 상에 제 2 층간 절연막(112)이 형성된다. 비아 콘택홀 형성용 마스크를 사용하여 상기 금속막 패턴의 표면이 노출될 때까지 상기 제 2 층간 절연막(112)을 식각함으로써 비아 콘택홀(114)이 형성된다. 텅스텐막(108)을 적용한 본 발명에서 상기 비아 콘택홀(114)의 형성시 상기 알루미늄막(104)을 식각하는 식각 가스에 대해 선택비를 갖는 막질인 텅스텐막(108)을 상기 캡핑층(106) 상에 형성함으로써 상기 알루미늄막 식각 부산물이 콘택홀 측벽에 붙는 현상, 부산물이 생성되는 현상 등을 방지할 수 있고 또한, 알루미늄막(104)이 부식되는 현상도 막을 수 있다.Subsequently, a second interlayer insulating layer 112 is formed on the first interlayer insulating layer 100 including the metal layer pattern. The via contact hole 114 is formed by etching the second interlayer insulating layer 112 until the surface of the metal layer pattern is exposed using a mask for forming a via contact hole. In the present invention to which the tungsten film 108 is applied, the capping layer 106 includes a tungsten film 108 having a selectivity with respect to an etching gas for etching the aluminum film 104 when the via contact hole 114 is formed. It is possible to prevent the aluminum film etching by-products from adhering to the contact hole sidewalls, to produce the by-products, etc., and to prevent the aluminum film 104 from corroding.
그리고, 상기 알루미늄막(104)에 비해 상대적으로 얇은 두께의 텅스텐막(108)을 추가로 형성함으로써 상기 텅스텐막(108)에 의한 금속막 패턴의 저항이 증가하거나 데이터(data) 전송 속도가 저하되는 등의 문제는 생기지 않는다.Further, by further forming a tungsten film 108 of a relatively thin thickness compared to the aluminum film 104, the resistance of the metal film pattern by the tungsten film 108 is increased or the data transmission speed is lowered. This does not occur.
본 발명은 금속막 패턴 형성을 위한 금속으로 텅스텐막을 추가하여 형성함으로써 금속막 패턴 형성시 마스크로서 작용하여 금속막 패턴이 식각되는 것을 방지할 수 있고, 비아 콘택홀 형성을 위한 식각시 알루미늄막이 식각되면서 발생한 부산물이 콘택홀의 측벽에 붙는 현상 및 부산물이 생성되는 현상 등을 방지할 수 있으며, 그리고 대기 중에 노출시 알루미늄막이 부식되는 것을 방지할 수 있는 효과가 있다.According to the present invention, by adding a tungsten film to the metal for forming the metal film pattern, the metal film pattern can be prevented from being etched by acting as a mask when the metal film pattern is formed, and the aluminum film is etched during the etching to form the via contact hole. The generated by-products may be prevented from adhering to the sidewalls of the contact holes and the by-products generated, and the aluminum film may be prevented from being corroded when exposed to the air.
Claims (6)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100740802B1 (en) * | 2003-07-21 | 2007-07-25 | (주)빅셀 | Removable carrier for protecting a hard disk drive form shock |
| US7486509B2 (en) | 2005-07-18 | 2009-02-03 | Samsung Electronics Co., Ltd. | Bracket for disk drive |
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1998
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100740802B1 (en) * | 2003-07-21 | 2007-07-25 | (주)빅셀 | Removable carrier for protecting a hard disk drive form shock |
| US7486509B2 (en) | 2005-07-18 | 2009-02-03 | Samsung Electronics Co., Ltd. | Bracket for disk drive |
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