KR19990080079A - Address Error Detection Device of Computer System - Google Patents

Abstract

The present invention relates to an address error detection apparatus of a computer system that allows monitoring of address access outside of the current actual memory capacity. In the prior art, when a program is developed in a state in which the memory corresponding to the desired memory capacity is not actually set in hardware, if an address outside the actual memory capacity is approached in hardware within the desired memory capacity, Later, when executing the program developed as described above, if the hardware does not meet the actual desired memory capacity, the program has an error that occurs. In the present invention for solving the drawbacks of the prior art, it is possible to improve the program development environment by monitoring the access of the address outside the current hardware real memory area in the development of the program. Therefore, the present invention has the effect of developing a more complete program.

Description

Address Error Detection Device of Computer System

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an apparatus for detecting address errors in a computer system, and more particularly to an apparatus for detecting address errors in a computer system for monitoring address access beyond a current actual memory capacity. .

In this regard, the software developer works with the hardware developer to create a table called an address map according to the desired memory capacity and develop a program using an address within this range. For example, if a DRAM (Dynamic Random Access Memory) has a total capacity of 64 Mbytes, the address map provides a hardware address area corresponding to 64 Mbytes.

DRAM, which is generally used, is formed in a module form for each memory capacity and used in a socket to increase the memory capacity in order of, for example, "16Mbyte-32Mbyte-48Mbyte-64Mbyte". . In other words, if the address map is set so that 64 Mbytes of capacity can be accessed, all 64 Mbytes of address area can be accessed in hardware even if the DRAM module is not inserted in each socket.

1 is a block diagram illustrating an example of memory use according to the prior art, in which a decoder 12 decodes an address signal output from a processor 2 so as to decode first and second signals. The DRAM select signal for selecting the third and fourth DRAM sockets 4, 6, 8, and 10 is output.

Next, the DRAM controller 14 controls read / write of the DRAM module mounted in the first to fourth DRAM sockets 4 to 10 according to the DRAM selection signal of the decoder 12. At this time, since there is already a promised 64 Mbyte address map, even if the DRAM module is not mounted in the first to fourth DRAM sockets 4 to 10, no error occurs even when the processor 2 attempts to access the hardware. . In other words, if no limitation is imposed on the decoder 12, no hardware defect occurs even when the DRAM module is not mounted in the first through fourth DRAM sockets 4 through 10.

Of course, when attempting to access the 65 Mbyte memory area with the 64 Mbyte address map set as described above, a hardware error occurs.

In more detail with regard to such an error, the processor 2 generates a start signal for accessing the DRAM module and waits for an end signal. If the address is out of the address map, that is, an address of 65 Mbyte region is generated as described above, 12 does not generate a DRAM selection signal, so the DRAM controller 14 does not give a termination signal to the processor 2.

Therefore, the DRAM controller 14 sends an error signal to the processor 2 after the set time has elapsed, causing the processor 2 to cause an error in its system.

However, in such a conventional technology, when a program is developed in a state in which a memory corresponding to a desired memory capacity is not actually set in hardware, an address outside the actual memory capacity in hardware within a desired memory capacity is provided. After that, there was a flaw that the program would fail if it did not meet the actual desired memory capacity in hardware when running the developed program.

Disclosure of Invention The present invention has been made to solve the above-mentioned shortcomings. In the development of a program, the detection of an address error of a computer system to monitor an access of an address outside an actual hardware real memory area and to improve a program development environment. The object is to provide a device.

In order to achieve the above object, the present invention provides a central processing unit (CPU) and a plurality of sockets mounted on a circuit board to provide total capacity information of memory modules mounted in the respective sockets. A computing system for controlling a read / write operation of a memory module through an address signal, the computing system comprising: comparing an address from the central processing unit with total capacity information of the memory module and comparing the address to the total capacity information of the memory module. And a comparator for providing this fact to the central processing unit when the address is out of the corresponding address map so that the central processing unit can process the address in error.

1 is a block diagram illustrating an embodiment of memory usage according to the prior art;

Figure 2 is a block diagram showing an embodiment of an address error detection apparatus of a computer system according to the present invention.

<Description of the symbols for the main parts of the drawings>

10 memory unit 12 memory detection unit

14,16: first and second decoder 18: memory determination unit

20: central processing unit 22: memory control unit

24: comparison unit

Hereinafter, the embodiment of the present invention as described in detail as follows.

2 is a block diagram illustrating an address error detection apparatus of a computer system according to an exemplary embodiment of the present invention. The memory unit 10 is installed on a main board on which a processor is mounted and includes a plurality of sockets for each bank unit. A plurality of memory modules (hereinafter, referred to as memory modules are DRAM memory modules) are respectively mounted regardless of their capacity. In this case, since each memory module is mounted in each socket regardless of a specific combination, there is no need to consider a bank unit in particular.

Next, the memory detector 12 monitors each socket of the memory unit 10, that is, monitors each pin of the memory module, and detects which socket has a memory having a certain size. At this time, each memory module has a function of outputting a signal indicating its capacity through its own pin. Therefore, the memory detector 12 may detect which socket is equipped with a memory having a certain size, as well as detect which socket is empty.

In addition, the first decoder 14 decodes a detection signal of the memory detector 12 and outputs a signal capable of recognizing the detection information in the system to the memory determiner 18 and the memory controller 22. The decoder 16 decodes the address signal from the central processing unit 20 and outputs a signal for the system to read or write the desired information to the desired position to the memory determining unit 18 and the memory control unit 22.

Therefore, the memory determination unit 18 performs a logical operation on the signals of the first and second decoders 14 and 16 to determine which socket of the memory unit 10 is equipped with a memory having a certain size. The result is reported to the central processing unit 20.

Next, the CPU 20 applies an address signal to the second decoder 16 to read or write the information requested by the system at a desired position with reference to the determination result of the memory determiner 18. The controller 22 performs a logic operation on the signals of the first and second decoders 14 and 16 to control a read or write operation according to a corresponding address desired by the system in each memory mounted in the memory unit 10.

The comparison unit 24 compares the address of the central processing unit 20 with the total capacity information of the memory module from the memory determination unit 18 and the address is out of the address map corresponding to the total capacity information of the memory module. This fact is provided to the central processing unit 20 so that the central processing unit 20 may process the address error. In this case, as an example of address error processing of the central processing unit 20, an error message may be displayed on a monitor screen, a warning sound may be generated through a speaker, or both of the above may be executed.

As described above, the present invention has the effect of improving the program development environment by monitoring the access of addresses outside the current hardware real memory area in the development of the program, thereby improving the program development environment.

Claims (1)

A computing system in which a central processing unit and a plurality of sockets are mounted on a circuit board to provide total capacity information of memory modules mounted in each socket, and the central processing unit controls the read / write operation of the memory module through an address signal. In: Comparing the address from the central processing unit with the total capacity information of the memory module, if the address is out of the address map corresponding to the total capacity information of the memory module, this fact is provided to the central processing unit to provide the central processing unit. And a comparator for causing an error to be processed by the address.