KR19990080026A - Charge pump in phase locked loop circuit - Google Patents

Abstract

The charge pump according to the invention provides pull-up and pull-down control circuits and pull-up / down circuits. The pull-up control circuit controls the pull-up / down circuit by controlling an up signal supplied from a phase comparator. The pull-down control circuit controls the pull-up / down circuit by controlling a down signal supplied from a phase comparator. The pull-up / down circuit supplies a pumping current to the loop filter by control of the pull-up and pull-down control circuits.

Description

CHARGE PUMP OF PHASE LOCKED LOOP CIRCUIT

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to a charge pump that can operate at low voltages.

The charge pump phase locked loop (CPPLL) is a system that synchronizes the input and output frequencies. Among the circuits provided in the phase locked loop circuit, a charge pump is a circuit used when a high voltage of a level higher than an external supply voltage is required.

Referring to FIG. 1, a commonly used phase locked loop circuit includes a phase comparator 100, a charge pump circuit 200, a loop filter 300, a voltage controlled oscillator 400, and a divider 500. The phase comparator 100 compares a reference frequency (Fref) input from the outside with a frequency division (Ffeed) output from the divider (500) and compares the up (DN) signal and the down (DN) signal as comparison signals. Supply to the charge pump circuit 200. The charge pump circuit 200 receives the up / down (UP / DN) signals from the phase comparator 100 and supplies a pumping current Ip to the loop filter 300. The loop filter 300 filters the frequency component of the pumping current Ip supplied from the charge pump 200. The voltage controlled oscillator 400 outputs a frequency Fout corresponding to the potential of the pumping current Ip supplied from the loop filter 300. The divider 500 divides the frequency Fout output from the voltage controlled oscillator 400 and supplies the divided frequency Ffeed to the phase comparator 100.

Referring to FIG. 2, the charge pump according to the related art includes a bandgap reference 210 and a charge pump 220. The charge pump 220 is composed of PMOS transistors PM1 and PM2 and NMOS transistors NM1 and NM2. The PMOS transistor PM1 has a source, a gate and a drain, the source is connected to a voltage power supply, a gate is connected to a first output terminal of the bandgap reference 210, and a drain is the PMOS transistor PM2. Is connected to the drain. The PMOS transistor PM2 has a source, a gate, and a drain, the source is connected to the source of the PMOS transistor PM1, a gate is connected to a first switch terminal, and a drain is of the NMOS transistor NM1. It is connected to the connection point of the drain and the input terminal of the loop filter 300.

The NMOS transistor NM1 has a source, a gate and a drain, the source is connected to a drain of the NMOS transistor NM2, the gate is connected to a second switch terminal, and the drain is the PMOS transistor PM2. Is connected to the drain of the. The NMOS transistor NM2 has a source, a gate and a drain, the source is connected to a ground power supply, the gate is connected to a second output terminal of the bandgap reference 100, and the drain is connected to the NMOS transistor ( NM1).

The bandgap reference 210 may charge the charge pump to the first and second reference voltages having complementary voltage levels by controlling the UP signal and the DN signal output from the phase comparator 100. Supply to 220. The PMOS transistors PM1 and PM2 of the charge pump 220 may control the pumping current Ip by controlling the UP signal and the switch signal SW1 output from the bandgap reference 100. Supply to the loop filter 300. The NMOS transistors NM1 and NM2 discharge the pumping current Ip to the ground power under control of the down signal DN and the switch signal SW2 output from the bandgap reference 100.

The pump circuit according to the related art performs a switch operation while supplying an up signal and a down signal output through a bandgap reference. However, as the low voltage is applied, when the four-stage transistors are used as in the conventional embodiment, the impedance of the transistors increases relatively, which causes a problem that the voltage range required by the pump circuit cannot be satisfied.

It is therefore an object of the present invention to provide a charge pump circuit capable of operating at a wide range of voltages, ie low voltages.

1 is a block diagram of a general phase locked loop circuit;

2 is a circuit diagram of a charge pump according to the prior art;

3 is a detailed circuit diagram of the charge pump of the present invention; And

4 is an operational waveform diagram of a charge pump according to the present invention.

* Explanation of symbols on the main parts of the drawings

100: phase comparator 200: charge pump circuit

210: bandgap reference 220: charge pump

300 loop filter 400 voltage controlled oscillator

500: divider

(Configuration)

According to one aspect of the present invention for achieving the above object, to output the first and second reference voltages of complementary levels in response to the first and second comparison signals informing the operation of the charge pump circuit. A band gap reference; A pull-up control circuit that receives the first reference voltage from the bandgap reference and selectively outputs a pull-up control signal in response to the first comparison signal; A pull-down control circuit that receives a second reference voltage from the bandgap reference and selectively outputs a pull-down control signal in response to a second comparison signal; A pull-up / down circuit that accepts an external voltage and selectively outputs the external voltage in response to the pull-up and pull-down control signals.

In this embodiment, the pull-up / down circuit comprises: an output terminal; A PMOS transistor outputting the external voltage through the output terminal in response to the pull-up signal; And an NMOS transistor that discharges the output terminal in response to the pull-down signal.

(Action)

Such a device can operate in a wide voltage range, that is, low voltage, by reducing the output impedance of the MOS transistor provided in the charge pump circuit.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 3 and 4 according to an embodiment of the present invention.

3, the charge pump circuit according to the present invention provides pull-up and pull-down control circuits and pull-up / down circuits. The pull-up control circuit controls the pull-up / down circuit to supply an up signal output from a bandgap reference to supply a pumping current to the loop filter. The pull-down control circuit controls the pull-up / down circuit to supply a down signal output from a bandgap reference to supply a pumping current to the loop filter.

3 is a detailed circuit diagram of the charge pump of the present invention.

Referring to FIG. 3, the charge pump circuit 200 of the present invention includes a bandgap reference 210 and a charge pump 220. The bandgap reference 210 includes PMOS transistors PM1, PM2, and PM3 and NMOS transistors NM1, NM2, and NM3. The PMOS transistor PM1 has a source, a gate and a drain, the source is connected to the voltage power supply, the gate is connected to the output terminal of the phase comparator 100, and the drain is the PMOS transistor PM2. Is connected to the gate. The PMOS transistor PM2 has a source, a gate and a drain, the source is connected to the voltage power supply, the gate is connected to the source of the PMOS transistor PM1, and the drain is the NMOS transistor NM1. Is connected to the drain.

The PMOS transistor PM3 has a source, a gate and a drain, the source is connected to the voltage power supply, the gate is connected to a drain of an NMOS transistor NM4 of the pull-up control circuit 221 and the A drain is connected to the drain of the NMOS transistor NM3. The NMOS transistor NM1 has a source, a gate, and a drain, the source is connected to a ground power supply, the gate is connected to a drain of the NMOS transistor NM2, and the drain is connected to the PMOS transistor PM2. Connected to the drain. The NMOS transistor NM2 has a source, a gate and a drain, the source is connected to the ground power supply, the gate is connected to an operation signal EN terminal, and a drain is connected to the gate of the NMOS transistor NM1. Connected. The NMOS transistor NM3 has a source, a gate, and a drain, the source is connected to the ground power source, the gate is connected to the gate of the NMOS transistor NM1, and the drain is the PMOS transistor PM3. Is connected to the drain of the.

The charge pump 220 includes a pull-up control circuit 221, a pull-down control circuit 222, and a pull-up / down circuit 223. The pull-up control circuit 221 includes a PMOS transistor PM4 and an NMOS transistor NM4. The PMOS transistor PM4 has a source, a gate and a drain, the source is connected to the voltage power supply, the gate is connected to a first output terminal of the phase comparator 100, and the drain is connected to the NMOS transistor ( NM4). The NMOS transistor NM4 has a source, a gate and a drain, the source is connected to the drain of the PMOS transistor PM4, the gate is connected to the first output terminal of the phase comparator 100 and The drain is connected to the drain of the PMOS transistor PM3.

The pull-down control circuit 222 includes a PMOS transistor PM5 and an NMOS transistor NM5. The PMOS transistor PM5 has a source, a gate and a drain, the source is connected to the drain of the NMOS transistor NM5, the gate is connected to a second output terminal of the phase comparator 100 and the A drain is connected to the source of the NMOS transistor NM5. The NMOS transistor NM5 has a source, a gate and a drain, the source is connected to the ground power supply, the gate is connected to the second output terminal of the phase comparator 100 and the drain is the PMOS transistor. Is linked to the source of (PM5).

The pull-up / down circuit 223 includes a PMOS transistor PM6 and an NMOS transistor NM6. The PMOS transistor PM6 has a source, a gate and a drain, the source is connected to the voltage power supply, the gate is connected to an output terminal of the pull-up control circuit 221 and the drain is the NMOS transistor. Is connected to the drain of NM6. The NMOS transistor NM6 has a source, a gate and a drain, the source is connected to the ground power supply, the gate is connected to an output terminal of the pull-down control circuit 222 and the drain is the PMOS transistor. Is connected to the drain of PM6.

The loop filter 300 includes a resistor R and capacitors C1 and C2. One terminal of the resistor R is connected to a connection point of the source of the PMOS transistor PM6 and the drain of the NMOS transistor NM6, and the other terminal is connected to one terminal of the capacitor C1. One terminal of the capacitor C1 is connected to the other terminal of the resistor R, and the other terminal is connected to the ground power source. One terminal of the capacitor C2 is connected to a connection point of the source of the PMOS transistor PM6 and the drain of the NMOS transistor NM6, and the other terminal is connected to the ground power source.

3, the operation of the charge pump of the present invention will be described.

Referring to FIG. 3 again, the bandgap reference 210 sets first and second reference voltages to the charge pump by controlling the up / down (UP / DN) signals output from the phase comparator 100. 220). The pull-up control circuit 221 controls the PMOS transistor PM6 of the pull-up / down circuit 223 by controlling the up signal supplied from the phase comparator 100. For example, when the UP signal is at a high level, the current path of the NMOS transistor NM4 is turned on and the current path of the PMOS transistor PM4 is shut off to pump the voltage supplied from the voltage power supply. The current Ip is supplied to the loop filter 300. When the UP signal is at a low level, the current path of the NMOS transistor NM4 is blocked and the current path of the PMOS transistor PM4 is turned on to provide the pumping current supplied from the voltage power supply. Block (Ip).

The pull-down control circuit 222 controls the NMOS transistor NM6 of the pull-up / down circuit 223 by controlling the down (DN) signal supplied from the phase comparator 100. For example, when the down (DN) signal is at a high level, the current path of the NMOS transistor NM5 is turned on and the current path of the PMOS transistor PM5 is blocked to discharge the pump to the ground power supply. Shut off current Ip. When the down (DN) signal is at a low level, the current path of the NMOS transistor NM5 is cut off, and the current path of the PMOS transistor PM5 is conducted so that the pumping current Ip to the ground power source. ) Is discharged.

The PMOS transistor PM6 of the pull-up / down circuit 223 supplies the pumping current Ip to the loop filter by controlling the UP signal supplied from the pull-up control circuit 221. Supply to 300. The NMOS transistor NM6 discharges the pumping current Ip to the ground power by controlling the down signal DN supplied from the pull-down control circuit NM6. The loop filter 300 filters and outputs a frequency component of the pumping current Ip supplied from the charge pump 200.

4 is a waveform diagram showing the operation of the charge pump according to the present invention.

4A shows the up / down current when the supply voltage is 3.3 volts.

4B shows the loop filter voltage when the supply voltage is 3.3 volts.

4C shows the up / down currents when the supply voltage is 3.3 volts and the input frequency is 50 MHz.

4B shows the loop filter voltage when the supply voltage is 3.3 volts and the input frequency is 50 MHz.

4E shows the up / down current when the supply voltage is 2.5 volts.

4F shows the loop filter voltage when the supply voltage is 2.5 volts.

4G shows the up / down currents when the supply voltage is 1.5 volts.

4H shows the loop filter voltage when the supply voltage is 1.5 volts.

4A to 4H, the charge pump circuit of the present invention has a smaller input impedance than the conventional charge pump circuit. Accordingly, the output voltage of the charge pump circuit, that is, the voltage of the loop filter 300 is in the range of 0.5 to 2.6 volts, and the up / down current difference is about 1 uA. In addition, the peak current is generated at a small level, and the time at which the pumping current Ip is applied while the input frequency is applied at 50 MHz, that is, the speed of switching the MOS transistors PM6 and NM6 is improved.

As described above, by providing two-stage transistors at the output stage, it is possible to implement a charge pump operating in the low voltage range by preventing a sudden increase in the output impedance in response to the application of a low voltage.

Claims (2)

In a charge pump circuit of a phase locked loop circuit for supplying a voltage at a level higher than the applied voltage: A band gap reference outputting complementary levels of first and second reference voltages in response to first and second comparison signals informing the charge pump circuit of operation; A pull-up control circuit that receives the first reference voltage and selectively outputs a pull-up control signal in response to the first comparison signal; A pull-down control circuit which receives the second reference voltage and selectively outputs a pull-down control signal in response to the second comparison signal; And a pull-up / down circuit that receives an external voltage and selectively outputs the external voltage in response to the pull-up and pull-down control signals. The method of claim 1, The pull-up / down circuit, An output terminal; A PMOS transistor outputting the external voltage through the output terminal in response to the pull-up signal; And an NMOS transistor configured to discharge the output terminal in response to the pull-down signal.